Linux kernel mirror (for testing)
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linux
1/*
2 * arch/powerpc/sysdev/qe_lib/ucc.c
3 *
4 * QE UCC API Set - UCC specific routines implementations.
5 *
6 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
7 *
8 * Authors: Shlomi Gridish <gridish@freescale.com>
9 * Li Yang <leoli@freescale.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/errno.h>
19#include <linux/slab.h>
20#include <linux/stddef.h>
21#include <linux/module.h>
22
23#include <asm/irq.h>
24#include <asm/io.h>
25#include <asm/immap_qe.h>
26#include <asm/qe.h>
27#include <asm/ucc.h>
28
29DEFINE_SPINLOCK(cmxgcr_lock);
30EXPORT_SYMBOL(cmxgcr_lock);
31
32int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
33{
34 unsigned long flags;
35
36 if (ucc_num > UCC_MAX_NUM - 1)
37 return -EINVAL;
38
39 spin_lock_irqsave(&cmxgcr_lock, flags);
40 clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
41 ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
42 spin_unlock_irqrestore(&cmxgcr_lock, flags);
43
44 return 0;
45}
46EXPORT_SYMBOL(ucc_set_qe_mux_mii_mng);
47
48/* Configure the UCC to either Slow or Fast.
49 *
50 * A given UCC can be figured to support either "slow" devices (e.g. UART)
51 * or "fast" devices (e.g. Ethernet).
52 *
53 * 'ucc_num' is the UCC number, from 0 - 7.
54 *
55 * This function also sets the UCC_GUEMR_SET_RESERVED3 bit because that bit
56 * must always be set to 1.
57 */
58int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed)
59{
60 u8 __iomem *guemr;
61
62 /* The GUEMR register is at the same location for both slow and fast
63 devices, so we just use uccX.slow.guemr. */
64 switch (ucc_num) {
65 case 0: guemr = &qe_immr->ucc1.slow.guemr;
66 break;
67 case 1: guemr = &qe_immr->ucc2.slow.guemr;
68 break;
69 case 2: guemr = &qe_immr->ucc3.slow.guemr;
70 break;
71 case 3: guemr = &qe_immr->ucc4.slow.guemr;
72 break;
73 case 4: guemr = &qe_immr->ucc5.slow.guemr;
74 break;
75 case 5: guemr = &qe_immr->ucc6.slow.guemr;
76 break;
77 case 6: guemr = &qe_immr->ucc7.slow.guemr;
78 break;
79 case 7: guemr = &qe_immr->ucc8.slow.guemr;
80 break;
81 default:
82 return -EINVAL;
83 }
84
85 clrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,
86 UCC_GUEMR_SET_RESERVED3 | speed);
87
88 return 0;
89}
90
91static void get_cmxucr_reg(unsigned int ucc_num, __be32 __iomem **cmxucr,
92 unsigned int *reg_num, unsigned int *shift)
93{
94 unsigned int cmx = ((ucc_num & 1) << 1) + (ucc_num > 3);
95
96 *reg_num = cmx + 1;
97 *cmxucr = &qe_immr->qmx.cmxucr[cmx];
98 *shift = 16 - 8 * (ucc_num & 2);
99}
100
101int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask)
102{
103 __be32 __iomem *cmxucr;
104 unsigned int reg_num;
105 unsigned int shift;
106
107 /* check if the UCC number is in range. */
108 if (ucc_num > UCC_MAX_NUM - 1)
109 return -EINVAL;
110
111 get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift);
112
113 if (set)
114 setbits32(cmxucr, mask << shift);
115 else
116 clrbits32(cmxucr, mask << shift);
117
118 return 0;
119}
120
121int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
122 enum comm_dir mode)
123{
124 __be32 __iomem *cmxucr;
125 unsigned int reg_num;
126 unsigned int shift;
127 u32 clock_bits = 0;
128
129 /* check if the UCC number is in range. */
130 if (ucc_num > UCC_MAX_NUM - 1)
131 return -EINVAL;
132
133 /* The communications direction must be RX or TX */
134 if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX)))
135 return -EINVAL;
136
137 get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift);
138
139 switch (reg_num) {
140 case 1:
141 switch (clock) {
142 case QE_BRG1: clock_bits = 1; break;
143 case QE_BRG2: clock_bits = 2; break;
144 case QE_BRG7: clock_bits = 3; break;
145 case QE_BRG8: clock_bits = 4; break;
146 case QE_CLK9: clock_bits = 5; break;
147 case QE_CLK10: clock_bits = 6; break;
148 case QE_CLK11: clock_bits = 7; break;
149 case QE_CLK12: clock_bits = 8; break;
150 case QE_CLK15: clock_bits = 9; break;
151 case QE_CLK16: clock_bits = 10; break;
152 default: break;
153 }
154 break;
155 case 2:
156 switch (clock) {
157 case QE_BRG5: clock_bits = 1; break;
158 case QE_BRG6: clock_bits = 2; break;
159 case QE_BRG7: clock_bits = 3; break;
160 case QE_BRG8: clock_bits = 4; break;
161 case QE_CLK13: clock_bits = 5; break;
162 case QE_CLK14: clock_bits = 6; break;
163 case QE_CLK19: clock_bits = 7; break;
164 case QE_CLK20: clock_bits = 8; break;
165 case QE_CLK15: clock_bits = 9; break;
166 case QE_CLK16: clock_bits = 10; break;
167 default: break;
168 }
169 break;
170 case 3:
171 switch (clock) {
172 case QE_BRG9: clock_bits = 1; break;
173 case QE_BRG10: clock_bits = 2; break;
174 case QE_BRG15: clock_bits = 3; break;
175 case QE_BRG16: clock_bits = 4; break;
176 case QE_CLK3: clock_bits = 5; break;
177 case QE_CLK4: clock_bits = 6; break;
178 case QE_CLK17: clock_bits = 7; break;
179 case QE_CLK18: clock_bits = 8; break;
180 case QE_CLK7: clock_bits = 9; break;
181 case QE_CLK8: clock_bits = 10; break;
182 case QE_CLK16: clock_bits = 11; break;
183 default: break;
184 }
185 break;
186 case 4:
187 switch (clock) {
188 case QE_BRG13: clock_bits = 1; break;
189 case QE_BRG14: clock_bits = 2; break;
190 case QE_BRG15: clock_bits = 3; break;
191 case QE_BRG16: clock_bits = 4; break;
192 case QE_CLK5: clock_bits = 5; break;
193 case QE_CLK6: clock_bits = 6; break;
194 case QE_CLK21: clock_bits = 7; break;
195 case QE_CLK22: clock_bits = 8; break;
196 case QE_CLK7: clock_bits = 9; break;
197 case QE_CLK8: clock_bits = 10; break;
198 case QE_CLK16: clock_bits = 11; break;
199 default: break;
200 }
201 break;
202 default: break;
203 }
204
205 /* Check for invalid combination of clock and UCC number */
206 if (!clock_bits)
207 return -ENOENT;
208
209 if (mode == COMM_DIR_RX)
210 shift += 4;
211
212 clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
213 clock_bits << shift);
214
215 return 0;
216}