tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright(c) 2004 - 2007 Intel Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21#ifndef _IOAT_REGISTERS_H_
22#define _IOAT_REGISTERS_H_
23
24#define IOAT_PCI_DMACTRL_OFFSET 0x48
25#define IOAT_PCI_DMACTRL_DMA_EN 0x00000001
26#define IOAT_PCI_DMACTRL_MSI_EN 0x00000002
27
28#define IOAT_PCI_DEVICE_ID_OFFSET 0x02
29#define IOAT_PCI_DMAUNCERRSTS_OFFSET 0x148
30#define IOAT_PCI_CHANERRMASK_INT_OFFSET 0x184
31
32/* MMIO Device Registers */
33#define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */
34
35#define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */
36#define IOAT_XFERCAP_4KB 12
37#define IOAT_XFERCAP_8KB 13
38#define IOAT_XFERCAP_16KB 14
39#define IOAT_XFERCAP_32KB 15
40#define IOAT_XFERCAP_32GB 0
41
42#define IOAT_GENCTRL_OFFSET 0x02 /* 8-bit */
43#define IOAT_GENCTRL_DEBUG_EN 0x01
44
45#define IOAT_INTRCTRL_OFFSET 0x03 /* 8-bit */
46#define IOAT_INTRCTRL_MASTER_INT_EN 0x01 /* Master Interrupt Enable */
47#define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */
48#define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */
49#define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL 0x08 /* Enable all MSI-X vectors */
50
51#define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */
52
53#define IOAT_VER_OFFSET 0x08 /* 8-bit */
54#define IOAT_VER_MAJOR_MASK 0xF0
55#define IOAT_VER_MINOR_MASK 0x0F
56#define GET_IOAT_VER_MAJOR(x) (((x) & IOAT_VER_MAJOR_MASK) >> 4)
57#define GET_IOAT_VER_MINOR(x) ((x) & IOAT_VER_MINOR_MASK)
58
59#define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */
60
61#define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */
62#define IOAT_INTRDELAY_INT_DELAY_MASK 0x3FFF /* Interrupt Delay Time */
63#define IOAT_INTRDELAY_COALESE_SUPPORT 0x8000 /* Interrupt Coalescing Supported */
64
65#define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */
66#define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x0001
67
68#define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */
69
70/* DMA Channel Registers */
71#define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */
72#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000
73#define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100
74#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020
75#define IOAT_CHANCTRL_ERR_INT_EN 0x0010
76#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008
77#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004
78#define IOAT_CHANCTRL_INT_DISABLE 0x0001
79
80#define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */
81#define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */
82#define IOAT_DMA_COMP_V2 0x0002 /* Compatibility with DMA version 2 */
83
84
85#define IOAT1_CHANSTS_OFFSET 0x04 /* 64-bit Channel Status Register */
86#define IOAT2_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */
87#define IOAT_CHANSTS_OFFSET(ver) ((ver) < IOAT_VER_2_0 \
88 ? IOAT1_CHANSTS_OFFSET : IOAT2_CHANSTS_OFFSET)
89#define IOAT1_CHANSTS_OFFSET_LOW 0x04
90#define IOAT2_CHANSTS_OFFSET_LOW 0x08
91#define IOAT_CHANSTS_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \
92 ? IOAT1_CHANSTS_OFFSET_LOW : IOAT2_CHANSTS_OFFSET_LOW)
93#define IOAT1_CHANSTS_OFFSET_HIGH 0x08
94#define IOAT2_CHANSTS_OFFSET_HIGH 0x0C
95#define IOAT_CHANSTS_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \
96 ? IOAT1_CHANSTS_OFFSET_HIGH : IOAT2_CHANSTS_OFFSET_HIGH)
97#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR ~0x3F
98#define IOAT_CHANSTS_SOFT_ERR 0x0000000000000010
99#define IOAT_CHANSTS_UNAFFILIATED_ERR 0x0000000000000008
100#define IOAT_CHANSTS_DMA_TRANSFER_STATUS 0x0000000000000007
101#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_ACTIVE 0x0
102#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_DONE 0x1
103#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_SUSPENDED 0x2
104#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED 0x3
105
106
107
108#define IOAT_CHAN_DMACOUNT_OFFSET 0x06 /* 16-bit DMA Count register */
109
110#define IOAT_DCACTRL_OFFSET 0x30 /* 32 bit Direct Cache Access Control Register */
111#define IOAT_DCACTRL_CMPL_WRITE_ENABLE 0x10000
112#define IOAT_DCACTRL_TARGET_CPU_MASK 0xFFFF /* APIC ID */
113
114/* CB DCA Memory Space Registers */
115#define IOAT_DCAOFFSET_OFFSET 0x14
116/* CB_BAR + IOAT_DCAOFFSET value */
117#define IOAT_DCA_VER_OFFSET 0x00
118#define IOAT_DCA_VER_MAJOR_MASK 0xF0
119#define IOAT_DCA_VER_MINOR_MASK 0x0F
120
121#define IOAT_DCA_COMP_OFFSET 0x02
122#define IOAT_DCA_COMP_V1 0x1
123
124#define IOAT_FSB_CAPABILITY_OFFSET 0x04
125#define IOAT_FSB_CAPABILITY_PREFETCH 0x1
126
127#define IOAT_PCI_CAPABILITY_OFFSET 0x06
128#define IOAT_PCI_CAPABILITY_MEMWR 0x1
129
130#define IOAT_FSB_CAP_ENABLE_OFFSET 0x08
131#define IOAT_FSB_CAP_ENABLE_PREFETCH 0x1
132
133#define IOAT_PCI_CAP_ENABLE_OFFSET 0x0A
134#define IOAT_PCI_CAP_ENABLE_MEMWR 0x1
135
136#define IOAT_APICID_TAG_MAP_OFFSET 0x0C
137#define IOAT_APICID_TAG_MAP_TAG0 0x0000000F
138#define IOAT_APICID_TAG_MAP_TAG0_SHIFT 0
139#define IOAT_APICID_TAG_MAP_TAG1 0x000000F0
140#define IOAT_APICID_TAG_MAP_TAG1_SHIFT 4
141#define IOAT_APICID_TAG_MAP_TAG2 0x00000F00
142#define IOAT_APICID_TAG_MAP_TAG2_SHIFT 8
143#define IOAT_APICID_TAG_MAP_TAG3 0x0000F000
144#define IOAT_APICID_TAG_MAP_TAG3_SHIFT 12
145#define IOAT_APICID_TAG_MAP_TAG4 0x000F0000
146#define IOAT_APICID_TAG_MAP_TAG4_SHIFT 16
147#define IOAT_APICID_TAG_CB2_VALID 0x8080808080
148
149#define IOAT_DCA_GREQID_OFFSET 0x10
150#define IOAT_DCA_GREQID_SIZE 0x04
151#define IOAT_DCA_GREQID_MASK 0xFFFF
152#define IOAT_DCA_GREQID_IGNOREFUN 0x10000000
153#define IOAT_DCA_GREQID_VALID 0x20000000
154#define IOAT_DCA_GREQID_LASTID 0x80000000
155
156#define IOAT3_CSI_CAPABILITY_OFFSET 0x08
157#define IOAT3_CSI_CAPABILITY_PREFETCH 0x1
158
159#define IOAT3_PCI_CAPABILITY_OFFSET 0x0A
160#define IOAT3_PCI_CAPABILITY_MEMWR 0x1
161
162#define IOAT3_CSI_CONTROL_OFFSET 0x0C
163#define IOAT3_CSI_CONTROL_PREFETCH 0x1
164
165#define IOAT3_PCI_CONTROL_OFFSET 0x0E
166#define IOAT3_PCI_CONTROL_MEMWR 0x1
167
168#define IOAT3_APICID_TAG_MAP_OFFSET 0x10
169#define IOAT3_APICID_TAG_MAP_OFFSET_LOW 0x10
170#define IOAT3_APICID_TAG_MAP_OFFSET_HIGH 0x14
171
172#define IOAT3_DCA_GREQID_OFFSET 0x02
173
174#define IOAT1_CHAINADDR_OFFSET 0x0C /* 64-bit Descriptor Chain Address Register */
175#define IOAT2_CHAINADDR_OFFSET 0x10 /* 64-bit Descriptor Chain Address Register */
176#define IOAT_CHAINADDR_OFFSET(ver) ((ver) < IOAT_VER_2_0 \
177 ? IOAT1_CHAINADDR_OFFSET : IOAT2_CHAINADDR_OFFSET)
178#define IOAT1_CHAINADDR_OFFSET_LOW 0x0C
179#define IOAT2_CHAINADDR_OFFSET_LOW 0x10
180#define IOAT_CHAINADDR_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \
181 ? IOAT1_CHAINADDR_OFFSET_LOW : IOAT2_CHAINADDR_OFFSET_LOW)
182#define IOAT1_CHAINADDR_OFFSET_HIGH 0x10
183#define IOAT2_CHAINADDR_OFFSET_HIGH 0x14
184#define IOAT_CHAINADDR_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \
185 ? IOAT1_CHAINADDR_OFFSET_HIGH : IOAT2_CHAINADDR_OFFSET_HIGH)
186
187#define IOAT1_CHANCMD_OFFSET 0x14 /* 8-bit DMA Channel Command Register */
188#define IOAT2_CHANCMD_OFFSET 0x04 /* 8-bit DMA Channel Command Register */
189#define IOAT_CHANCMD_OFFSET(ver) ((ver) < IOAT_VER_2_0 \
190 ? IOAT1_CHANCMD_OFFSET : IOAT2_CHANCMD_OFFSET)
191#define IOAT_CHANCMD_RESET 0x20
192#define IOAT_CHANCMD_RESUME 0x10
193#define IOAT_CHANCMD_ABORT 0x08
194#define IOAT_CHANCMD_SUSPEND 0x04
195#define IOAT_CHANCMD_APPEND 0x02
196#define IOAT_CHANCMD_START 0x01
197
198#define IOAT_CHANCMP_OFFSET 0x18 /* 64-bit Channel Completion Address Register */
199#define IOAT_CHANCMP_OFFSET_LOW 0x18
200#define IOAT_CHANCMP_OFFSET_HIGH 0x1C
201
202#define IOAT_CDAR_OFFSET 0x20 /* 64-bit Current Descriptor Address Register */
203#define IOAT_CDAR_OFFSET_LOW 0x20
204#define IOAT_CDAR_OFFSET_HIGH 0x24
205
206#define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */
207#define IOAT_CHANERR_DMA_TRANSFER_SRC_ADDR_ERR 0x0001
208#define IOAT_CHANERR_DMA_TRANSFER_DEST_ADDR_ERR 0x0002
209#define IOAT_CHANERR_NEXT_DESCRIPTOR_ADDR_ERR 0x0004
210#define IOAT_CHANERR_NEXT_DESCRIPTOR_ALIGNMENT_ERR 0x0008
211#define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR 0x0010
212#define IOAT_CHANERR_CHANCMD_ERR 0x0020
213#define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0040
214#define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0080
215#define IOAT_CHANERR_READ_DATA_ERR 0x0100
216#define IOAT_CHANERR_WRITE_DATA_ERR 0x0200
217#define IOAT_CHANERR_DESCRIPTOR_CONTROL_ERR 0x0400
218#define IOAT_CHANERR_DESCRIPTOR_LENGTH_ERR 0x0800
219#define IOAT_CHANERR_COMPLETION_ADDR_ERR 0x1000
220#define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000
221#define IOAT_CHANERR_SOFT_ERR 0x4000
222#define IOAT_CHANERR_UNAFFILIATED_ERR 0x8000
223
224#define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */
225
226#endif /* _IOAT_REGISTERS_H_ */