tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * include/asm-arm/arch-at91/at91sam9_smc.h
3 *
4 * Static Memory Controllers (SMC) - System peripherals registers.
5 * Based on AT91SAM9261 datasheet revision D.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef AT91SAM9_SMC_H
14#define AT91SAM9_SMC_H
15
16#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
17#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
18#define AT91_SMC_NWESETUP_(x) ((x) << 0)
19#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
20#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
21#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
22#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
23#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
24#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
25
26#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
27#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
28#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
29#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
30#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
31#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
32#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
33#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
34#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
35
36#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
37#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
38#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
39#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
40#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
41
42#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
43#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
44#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
45#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
46#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
47#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
48#define AT91_SMC_EXNWMODE_READY (3 << 4)
49#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
50#define AT91_SMC_BAT_SELECT (0 << 8)
51#define AT91_SMC_BAT_WRITE (1 << 8)
52#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
53#define AT91_SMC_DBW_8 (0 << 12)
54#define AT91_SMC_DBW_16 (1 << 12)
55#define AT91_SMC_DBW_32 (2 << 12)
56#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
57#define AT91_SMC_TDF_(x) ((x) << 16)
58#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
59#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
60#define AT91_SMC_PS (3 << 28) /* Page Size */
61#define AT91_SMC_PS_4 (0 << 28)
62#define AT91_SMC_PS_8 (1 << 28)
63#define AT91_SMC_PS_16 (2 << 28)
64#define AT91_SMC_PS_32 (3 << 28)
65
66#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
67#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
68#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
69#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
70#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
71#endif
72
73#endif