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kernel / drivers / net / tokenring / 3c359.c
at v2.6.27-rc2 1810 lines 59 kB view raw
1/* 2 * 3c359.c (c) 2000 Mike Phillips (mikep@linuxtr.net) All Rights Reserved 3 * 4 * Linux driver for 3Com 3c359 Tokenlink Velocity XL PCI NIC 5 * 6 * Base Driver Olympic: 7 * Written 1999 Peter De Schrijver & Mike Phillips 8 * 9 * This software may be used and distributed according to the terms 10 * of the GNU General Public License, incorporated herein by reference. 11 * 12 * 7/17/00 - Clean up, version number 0.9.0. Ready to release to the world. 13 * 14 * 2/16/01 - Port up to kernel 2.4.2 ready for submission into the kernel. 15 * 3/05/01 - Last clean up stuff before submission. 16 * 2/15/01 - Finally, update to new pci api. 17 * 18 * To Do: 19 */ 20 21/* 22 * Technical Card Details 23 * 24 * All access to data is done with 16/8 bit transfers. The transfer 25 * method really sucks. You can only read or write one location at a time. 26 * 27 * Also, the microcode for the card must be uploaded if the card does not have 28 * the flashrom on board. This is a 28K bloat in the driver when compiled 29 * as a module. 30 * 31 * Rx is very simple, status into a ring of descriptors, dma data transfer, 32 * interrupts to tell us when a packet is received. 33 * 34 * Tx is a little more interesting. Similar scenario, descriptor and dma data 35 * transfers, but we don't have to interrupt the card to tell it another packet 36 * is ready for transmission, we are just doing simple memory writes, not io or mmio 37 * writes. The card can be set up to simply poll on the next 38 * descriptor pointer and when this value is non-zero will automatically download 39 * the next packet. The card then interrupts us when the packet is done. 40 * 41 */ 42 43#define XL_DEBUG 0 44 45#include <linux/jiffies.h> 46#include <linux/module.h> 47#include <linux/kernel.h> 48#include <linux/errno.h> 49#include <linux/timer.h> 50#include <linux/in.h> 51#include <linux/ioport.h> 52#include <linux/string.h> 53#include <linux/proc_fs.h> 54#include <linux/ptrace.h> 55#include <linux/skbuff.h> 56#include <linux/interrupt.h> 57#include <linux/delay.h> 58#include <linux/netdevice.h> 59#include <linux/trdevice.h> 60#include <linux/stddef.h> 61#include <linux/init.h> 62#include <linux/pci.h> 63#include <linux/spinlock.h> 64#include <linux/bitops.h> 65 66#include <net/checksum.h> 67 68#include <asm/io.h> 69#include <asm/system.h> 70 71#include "3c359.h" 72 73static char version[] __devinitdata = 74"3c359.c v1.2.0 2/17/01 - Mike Phillips (mikep@linuxtr.net)" ; 75 76MODULE_AUTHOR("Mike Phillips <mikep@linuxtr.net>") ; 77MODULE_DESCRIPTION("3Com 3C359 Velocity XL Token Ring Adapter Driver \n") ; 78 79/* Module paramters */ 80 81/* Ring Speed 0,4,16 82 * 0 = Autosense 83 * 4,16 = Selected speed only, no autosense 84 * This allows the card to be the first on the ring 85 * and become the active monitor. 86 * 87 * WARNING: Some hubs will allow you to insert 88 * at the wrong speed. 89 * 90 * The adapter will _not_ fail to open if there are no 91 * active monitors on the ring, it will simply open up in 92 * its last known ringspeed if no ringspeed is specified. 93 */ 94 95static int ringspeed[XL_MAX_ADAPTERS] = {0,} ; 96 97module_param_array(ringspeed, int, NULL, 0); 98MODULE_PARM_DESC(ringspeed,"3c359: Ringspeed selection - 4,16 or 0") ; 99 100/* Packet buffer size */ 101 102static int pkt_buf_sz[XL_MAX_ADAPTERS] = {0,} ; 103 104module_param_array(pkt_buf_sz, int, NULL, 0) ; 105MODULE_PARM_DESC(pkt_buf_sz,"3c359: Initial buffer size") ; 106/* Message Level */ 107 108static int message_level[XL_MAX_ADAPTERS] = {0,} ; 109 110module_param_array(message_level, int, NULL, 0) ; 111MODULE_PARM_DESC(message_level, "3c359: Level of reported messages") ; 112/* 113 * This is a real nasty way of doing this, but otherwise you 114 * will be stuck with 1555 lines of hex #'s in the code. 115 */ 116 117#include "3c359_microcode.h" 118 119static struct pci_device_id xl_pci_tbl[] = 120{ 121 {PCI_VENDOR_ID_3COM,PCI_DEVICE_ID_3COM_3C359, PCI_ANY_ID, PCI_ANY_ID, }, 122 { } /* terminate list */ 123}; 124MODULE_DEVICE_TABLE(pci,xl_pci_tbl) ; 125 126static int xl_init(struct net_device *dev); 127static int xl_open(struct net_device *dev); 128static int xl_open_hw(struct net_device *dev) ; 129static int xl_hw_reset(struct net_device *dev); 130static int xl_xmit(struct sk_buff *skb, struct net_device *dev); 131static void xl_dn_comp(struct net_device *dev); 132static int xl_close(struct net_device *dev); 133static void xl_set_rx_mode(struct net_device *dev); 134static irqreturn_t xl_interrupt(int irq, void *dev_id); 135static int xl_set_mac_address(struct net_device *dev, void *addr) ; 136static void xl_arb_cmd(struct net_device *dev); 137static void xl_asb_cmd(struct net_device *dev) ; 138static void xl_srb_cmd(struct net_device *dev, int srb_cmd) ; 139static void xl_wait_misr_flags(struct net_device *dev) ; 140static int xl_change_mtu(struct net_device *dev, int mtu); 141static void xl_srb_bh(struct net_device *dev) ; 142static void xl_asb_bh(struct net_device *dev) ; 143static void xl_reset(struct net_device *dev) ; 144static void xl_freemem(struct net_device *dev) ; 145 146 147/* EEProm Access Functions */ 148static u16 xl_ee_read(struct net_device *dev, int ee_addr) ; 149static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value) ; 150 151/* Debugging functions */ 152#if XL_DEBUG 153static void print_tx_state(struct net_device *dev) ; 154static void print_rx_state(struct net_device *dev) ; 155 156static void print_tx_state(struct net_device *dev) 157{ 158 159 struct xl_private *xl_priv = netdev_priv(dev); 160 struct xl_tx_desc *txd ; 161 u8 __iomem *xl_mmio = xl_priv->xl_mmio ; 162 int i ; 163 164 printk("tx_ring_head: %d, tx_ring_tail: %d, free_ent: %d \n",xl_priv->tx_ring_head, 165 xl_priv->tx_ring_tail, xl_priv->free_ring_entries) ; 166 printk("Ring , Address , FSH , DnNextPtr, Buffer, Buffer_Len \n"); 167 for (i = 0; i < 16; i++) { 168 txd = &(xl_priv->xl_tx_ring[i]) ; 169 printk("%d, %08lx, %08x, %08x, %08x, %08x \n", i, virt_to_bus(txd), 170 txd->framestartheader, txd->dnnextptr, txd->buffer, txd->buffer_length ) ; 171 } 172 173 printk("DNLISTPTR = %04x \n", readl(xl_mmio + MMIO_DNLISTPTR) ); 174 175 printk("DmaCtl = %04x \n", readl(xl_mmio + MMIO_DMA_CTRL) ); 176 printk("Queue status = %0x \n",netif_running(dev) ) ; 177} 178 179static void print_rx_state(struct net_device *dev) 180{ 181 182 struct xl_private *xl_priv = netdev_priv(dev); 183 struct xl_rx_desc *rxd ; 184 u8 __iomem *xl_mmio = xl_priv->xl_mmio ; 185 int i ; 186 187 printk("rx_ring_tail: %d \n", xl_priv->rx_ring_tail) ; 188 printk("Ring , Address , FrameState , UPNextPtr, FragAddr, Frag_Len \n"); 189 for (i = 0; i < 16; i++) { 190 /* rxd = (struct xl_rx_desc *)xl_priv->rx_ring_dma_addr + (i * sizeof(struct xl_rx_desc)) ; */ 191 rxd = &(xl_priv->xl_rx_ring[i]) ; 192 printk("%d, %08lx, %08x, %08x, %08x, %08x \n", i, virt_to_bus(rxd), 193 rxd->framestatus, rxd->upnextptr, rxd->upfragaddr, rxd->upfraglen ) ; 194 } 195 196 printk("UPLISTPTR = %04x \n", readl(xl_mmio + MMIO_UPLISTPTR) ); 197 198 printk("DmaCtl = %04x \n", readl(xl_mmio + MMIO_DMA_CTRL) ); 199 printk("Queue status = %0x \n",netif_running(dev) ) ; 200} 201#endif 202 203/* 204 * Read values from the on-board EEProm. This looks very strange 205 * but you have to wait for the EEProm to get/set the value before 206 * passing/getting the next value from the nic. As with all requests 207 * on this nic it has to be done in two stages, a) tell the nic which 208 * memory address you want to access and b) pass/get the value from the nic. 209 * With the EEProm, you have to wait before and inbetween access a) and b). 210 * As this is only read at initialization time and the wait period is very 211 * small we shouldn't have to worry about scheduling issues. 212 */ 213 214static u16 xl_ee_read(struct net_device *dev, int ee_addr) 215{ 216 struct xl_private *xl_priv = netdev_priv(dev); 217 u8 __iomem *xl_mmio = xl_priv->xl_mmio ; 218 219 /* Wait for EEProm to not be busy */ 220 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 221 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ; 222 223 /* Tell EEProm what we want to do and where */ 224 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 225 writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ; 226 227 /* Wait for EEProm to not be busy */ 228 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 229 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ; 230 231 /* Tell EEProm what we want to do and where */ 232 writel(IO_WORD_WRITE | EECONTROL , xl_mmio + MMIO_MAC_ACCESS_CMD) ; 233 writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ; 234 235 /* Finally read the value from the EEProm */ 236 writel(IO_WORD_READ | EEDATA , xl_mmio + MMIO_MAC_ACCESS_CMD) ; 237 return readw(xl_mmio + MMIO_MACDATA) ; 238} 239 240/* 241 * Write values to the onboard eeprom. As with eeprom read you need to 242 * set which location to write, wait, value to write, wait, with the 243 * added twist of having to enable eeprom writes as well. 244 */ 245 246static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value) 247{ 248 struct xl_private *xl_priv = netdev_priv(dev); 249 u8 __iomem *xl_mmio = xl_priv->xl_mmio ; 250 251 /* Wait for EEProm to not be busy */ 252 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 253 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ; 254 255 /* Enable write/erase */ 256 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 257 writew(EE_ENABLE_WRITE, xl_mmio + MMIO_MACDATA) ; 258 259 /* Wait for EEProm to not be busy */ 260 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 261 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ; 262 263 /* Put the value we want to write into EEDATA */ 264 writel(IO_WORD_WRITE | EEDATA, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 265 writew(ee_value, xl_mmio + MMIO_MACDATA) ; 266 267 /* Tell EEProm to write eevalue into ee_addr */ 268 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 269 writew(EEWRITE + ee_addr, xl_mmio + MMIO_MACDATA) ; 270 271 /* Wait for EEProm to not be busy, to ensure write gets done */ 272 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 273 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ; 274 275 return ; 276} 277 278static int __devinit xl_probe(struct pci_dev *pdev, 279 const struct pci_device_id *ent) 280{ 281 struct net_device *dev ; 282 struct xl_private *xl_priv ; 283 static int card_no = -1 ; 284 int i ; 285 286 card_no++ ; 287 288 if (pci_enable_device(pdev)) { 289 return -ENODEV ; 290 } 291 292 pci_set_master(pdev); 293 294 if ((i = pci_request_regions(pdev,"3c359"))) { 295 return i ; 296 } ; 297 298 /* 299 * Allowing init_trdev to allocate the dev->priv structure will align xl_private 300 * on a 32 bytes boundary which we need for the rx/tx descriptors 301 */ 302 303 dev = alloc_trdev(sizeof(struct xl_private)) ; 304 if (!dev) { 305 pci_release_regions(pdev) ; 306 return -ENOMEM ; 307 } 308 xl_priv = netdev_priv(dev); 309 310#if XL_DEBUG 311 printk("pci_device: %p, dev:%p, dev->priv: %p, ba[0]: %10x, ba[1]:%10x\n", 312 pdev, dev, netdev_priv(dev), (unsigned int)pdev->resource[0].start, (unsigned int)pdev->resource[1].start); 313#endif 314 315 dev->irq=pdev->irq; 316 dev->base_addr=pci_resource_start(pdev,0) ; 317 xl_priv->xl_card_name = pci_name(pdev); 318 xl_priv->xl_mmio=ioremap(pci_resource_start(pdev,1), XL_IO_SPACE); 319 xl_priv->pdev = pdev ; 320 321 if ((pkt_buf_sz[card_no] < 100) || (pkt_buf_sz[card_no] > 18000) ) 322 xl_priv->pkt_buf_sz = PKT_BUF_SZ ; 323 else 324 xl_priv->pkt_buf_sz = pkt_buf_sz[card_no] ; 325 326 dev->mtu = xl_priv->pkt_buf_sz - TR_HLEN ; 327 xl_priv->xl_ring_speed = ringspeed[card_no] ; 328 xl_priv->xl_message_level = message_level[card_no] ; 329 xl_priv->xl_functional_addr[0] = xl_priv->xl_functional_addr[1] = xl_priv->xl_functional_addr[2] = xl_priv->xl_functional_addr[3] = 0 ; 330 xl_priv->xl_copy_all_options = 0 ; 331 332 if((i = xl_init(dev))) { 333 iounmap(xl_priv->xl_mmio) ; 334 free_netdev(dev) ; 335 pci_release_regions(pdev) ; 336 return i ; 337 } 338 339 dev->open=&xl_open; 340 dev->hard_start_xmit=&xl_xmit; 341 dev->change_mtu=&xl_change_mtu; 342 dev->stop=&xl_close; 343 dev->do_ioctl=NULL; 344 dev->set_multicast_list=&xl_set_rx_mode; 345 dev->set_mac_address=&xl_set_mac_address ; 346 SET_NETDEV_DEV(dev, &pdev->dev); 347 348 pci_set_drvdata(pdev,dev) ; 349 if ((i = register_netdev(dev))) { 350 printk(KERN_ERR "3C359, register netdev failed\n") ; 351 pci_set_drvdata(pdev,NULL) ; 352 iounmap(xl_priv->xl_mmio) ; 353 free_netdev(dev) ; 354 pci_release_regions(pdev) ; 355 return i ; 356 } 357 358 printk(KERN_INFO "3C359: %s registered as: %s\n",xl_priv->xl_card_name,dev->name) ; 359 360 return 0; 361} 362 363 364static int __devinit xl_init(struct net_device *dev) 365{ 366 struct xl_private *xl_priv = netdev_priv(dev); 367 368 printk(KERN_INFO "%s \n", version); 369 printk(KERN_INFO "%s: I/O at %hx, MMIO at %p, using irq %d\n", 370 xl_priv->xl_card_name, (unsigned int)dev->base_addr ,xl_priv->xl_mmio, dev->irq); 371 372 spin_lock_init(&xl_priv->xl_lock) ; 373 374 return xl_hw_reset(dev) ; 375 376} 377 378 379/* 380 * Hardware reset. This needs to be a separate entity as we need to reset the card 381 * when we change the EEProm settings. 382 */ 383 384static int xl_hw_reset(struct net_device *dev) 385{ 386 struct xl_private *xl_priv = netdev_priv(dev); 387 u8 __iomem *xl_mmio = xl_priv->xl_mmio ; 388 unsigned long t ; 389 u16 i ; 390 u16 result_16 ; 391 u8 result_8 ; 392 u16 start ; 393 int j ; 394 395 /* 396 * Reset the card. If the card has got the microcode on board, we have 397 * missed the initialization interrupt, so we must always do this. 398 */ 399 400 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ; 401 402 /* 403 * Must wait for cmdInProgress bit (12) to clear before continuing with 404 * card configuration. 405 */ 406 407 t=jiffies; 408 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { 409 schedule(); 410 if (time_after(jiffies, t + 40 * HZ)) { 411 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL card not responding to global reset.\n", dev->name); 412 return -ENODEV; 413 } 414 } 415 416 /* 417 * Enable pmbar by setting bit in CPAttention 418 */ 419 420 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 421 result_8 = readb(xl_mmio + MMIO_MACDATA) ; 422 result_8 = result_8 | CPA_PMBARVIS ; 423 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 424 writeb(result_8, xl_mmio + MMIO_MACDATA) ; 425 426 /* 427 * Read cpHold bit in pmbar, if cleared we have got Flashrom on board. 428 * If not, we need to upload the microcode to the card 429 */ 430 431 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD); 432 433#if XL_DEBUG 434 printk(KERN_INFO "Read from PMBAR = %04x \n", readw(xl_mmio + MMIO_MACDATA)) ; 435#endif 436 437 if ( readw( (xl_mmio + MMIO_MACDATA)) & PMB_CPHOLD ) { 438 439 /* Set PmBar, privateMemoryBase bits (8:2) to 0 */ 440 441 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD); 442 result_16 = readw(xl_mmio + MMIO_MACDATA) ; 443 result_16 = result_16 & ~((0x7F) << 2) ; 444 writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 445 writew(result_16,xl_mmio + MMIO_MACDATA) ; 446 447 /* Set CPAttention, memWrEn bit */ 448 449 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 450 result_8 = readb(xl_mmio + MMIO_MACDATA) ; 451 result_8 = result_8 | CPA_MEMWREN ; 452 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 453 writeb(result_8, xl_mmio + MMIO_MACDATA) ; 454 455 /* 456 * Now to write the microcode into the shared ram 457 * The microcode must finish at position 0xFFFF, so we must subtract 458 * to get the start position for the code 459 */ 460 461 start = (0xFFFF - (mc_size) + 1 ) ; /* Looks strange but ensures compiler only uses 16 bit unsigned int for this */ 462 463 printk(KERN_INFO "3C359: Uploading Microcode: "); 464 465 for (i = start, j = 0; j < mc_size; i++, j++) { 466 writel(MEM_BYTE_WRITE | 0XD0000 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 467 writeb(microcode[j],xl_mmio + MMIO_MACDATA) ; 468 if (j % 1024 == 0) 469 printk("."); 470 } 471 printk("\n") ; 472 473 for (i=0;i < 16; i++) { 474 writel( (MEM_BYTE_WRITE | 0xDFFF0) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 475 writeb(microcode[mc_size - 16 + i], xl_mmio + MMIO_MACDATA) ; 476 } 477 478 /* 479 * Have to write the start address of the upload to FFF4, but 480 * the address must be >> 4. You do not want to know how long 481 * it took me to discover this. 482 */ 483 484 writel(MEM_WORD_WRITE | 0xDFFF4, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 485 writew(start >> 4, xl_mmio + MMIO_MACDATA); 486 487 /* Clear the CPAttention, memWrEn Bit */ 488 489 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 490 result_8 = readb(xl_mmio + MMIO_MACDATA) ; 491 result_8 = result_8 & ~CPA_MEMWREN ; 492 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 493 writeb(result_8, xl_mmio + MMIO_MACDATA) ; 494 495 /* Clear the cpHold bit in pmbar */ 496 497 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD); 498 result_16 = readw(xl_mmio + MMIO_MACDATA) ; 499 result_16 = result_16 & ~PMB_CPHOLD ; 500 writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 501 writew(result_16,xl_mmio + MMIO_MACDATA) ; 502 503 504 } /* If microcode upload required */ 505 506 /* 507 * The card should now go though a self test procedure and get itself ready 508 * to be opened, we must wait for an srb response with the initialization 509 * information. 510 */ 511 512#if XL_DEBUG 513 printk(KERN_INFO "%s: Microcode uploaded, must wait for the self test to complete\n", dev->name); 514#endif 515 516 writew(SETINDENABLE | 0xFFF, xl_mmio + MMIO_COMMAND) ; 517 518 t=jiffies; 519 while ( !(readw(xl_mmio + MMIO_INTSTATUS_AUTO) & INTSTAT_SRB) ) { 520 schedule(); 521 if (time_after(jiffies, t + 15 * HZ)) { 522 printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n"); 523 return -ENODEV; 524 } 525 } 526 527 /* 528 * Write the RxBufArea with D000, RxEarlyThresh, TxStartThresh, 529 * DnPriReqThresh, read the tech docs if you want to know what 530 * values they need to be. 531 */ 532 533 writel(MMIO_WORD_WRITE | RXBUFAREA, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 534 writew(0xD000, xl_mmio + MMIO_MACDATA) ; 535 536 writel(MMIO_WORD_WRITE | RXEARLYTHRESH, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 537 writew(0X0020, xl_mmio + MMIO_MACDATA) ; 538 539 writew( SETTXSTARTTHRESH | 0x40 , xl_mmio + MMIO_COMMAND) ; 540 541 writeb(0x04, xl_mmio + MMIO_DNBURSTTHRESH) ; 542 writeb(0x04, xl_mmio + DNPRIREQTHRESH) ; 543 544 /* 545 * Read WRBR to provide the location of the srb block, have to use byte reads not word reads. 546 * Tech docs have this wrong !!!! 547 */ 548 549 writel(MMIO_BYTE_READ | WRBR, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 550 xl_priv->srb = readb(xl_mmio + MMIO_MACDATA) << 8 ; 551 writel( (MMIO_BYTE_READ | WRBR) + 1, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 552 xl_priv->srb = xl_priv->srb | readb(xl_mmio + MMIO_MACDATA) ; 553 554#if XL_DEBUG 555 writel(IO_WORD_READ | SWITCHSETTINGS, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 556 if ( readw(xl_mmio + MMIO_MACDATA) & 2) { 557 printk(KERN_INFO "Default ring speed 4 mbps \n") ; 558 } else { 559 printk(KERN_INFO "Default ring speed 16 mbps \n") ; 560 } 561 printk(KERN_INFO "%s: xl_priv->srb = %04x\n",xl_priv->xl_card_name, xl_priv->srb); 562#endif 563 564 return 0; 565} 566 567static int xl_open(struct net_device *dev) 568{ 569 struct xl_private *xl_priv=netdev_priv(dev); 570 u8 __iomem *xl_mmio = xl_priv->xl_mmio ; 571 u8 i ; 572 __le16 hwaddr[3] ; /* Should be u8[6] but we get word return values */ 573 int open_err ; 574 575 u16 switchsettings, switchsettings_eeprom ; 576 577 if(request_irq(dev->irq, &xl_interrupt, IRQF_SHARED , "3c359", dev)) { 578 return -EAGAIN; 579 } 580 581 /* 582 * Read the information from the EEPROM that we need. 583 */ 584 585 hwaddr[0] = cpu_to_le16(xl_ee_read(dev,0x10)); 586 hwaddr[1] = cpu_to_le16(xl_ee_read(dev,0x11)); 587 hwaddr[2] = cpu_to_le16(xl_ee_read(dev,0x12)); 588 589 /* Ring speed */ 590 591 switchsettings_eeprom = xl_ee_read(dev,0x08) ; 592 switchsettings = switchsettings_eeprom ; 593 594 if (xl_priv->xl_ring_speed != 0) { 595 if (xl_priv->xl_ring_speed == 4) 596 switchsettings = switchsettings | 0x02 ; 597 else 598 switchsettings = switchsettings & ~0x02 ; 599 } 600 601 /* Only write EEProm if there has been a change */ 602 if (switchsettings != switchsettings_eeprom) { 603 xl_ee_write(dev,0x08,switchsettings) ; 604 /* Hardware reset after changing EEProm */ 605 xl_hw_reset(dev) ; 606 } 607 608 memcpy(dev->dev_addr,hwaddr,dev->addr_len) ; 609 610 open_err = xl_open_hw(dev) ; 611 612 /* 613 * This really needs to be cleaned up with better error reporting. 614 */ 615 616 if (open_err != 0) { /* Something went wrong with the open command */ 617 if (open_err & 0x07) { /* Wrong speed, retry at different speed */ 618 printk(KERN_WARNING "%s: Open Error, retrying at different ringspeed \n", dev->name) ; 619 switchsettings = switchsettings ^ 2 ; 620 xl_ee_write(dev,0x08,switchsettings) ; 621 xl_hw_reset(dev) ; 622 open_err = xl_open_hw(dev) ; 623 if (open_err != 0) { 624 printk(KERN_WARNING "%s: Open error returned a second time, we're bombing out now\n", dev->name); 625 free_irq(dev->irq,dev) ; 626 return -ENODEV ; 627 } 628 } else { 629 printk(KERN_WARNING "%s: Open Error = %04x\n", dev->name, open_err) ; 630 free_irq(dev->irq,dev) ; 631 return -ENODEV ; 632 } 633 } 634 635 /* 636 * Now to set up the Rx and Tx buffer structures 637 */ 638 /* These MUST be on 8 byte boundaries */ 639 xl_priv->xl_tx_ring = kzalloc((sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE) + 7, GFP_DMA | GFP_KERNEL); 640 if (xl_priv->xl_tx_ring == NULL) { 641 printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers.\n", 642 dev->name); 643 free_irq(dev->irq,dev); 644 return -ENOMEM; 645 } 646 xl_priv->xl_rx_ring = kzalloc((sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE) +7, GFP_DMA | GFP_KERNEL); 647 if (xl_priv->xl_tx_ring == NULL) { 648 printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers.\n", 649 dev->name); 650 free_irq(dev->irq,dev); 651 kfree(xl_priv->xl_tx_ring); 652 return -ENOMEM; 653 } 654 655 /* Setup Rx Ring */ 656 for (i=0 ; i < XL_RX_RING_SIZE ; i++) { 657 struct sk_buff *skb ; 658 659 skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ; 660 if (skb==NULL) 661 break ; 662 663 skb->dev = dev ; 664 xl_priv->xl_rx_ring[i].upfragaddr = cpu_to_le32(pci_map_single(xl_priv->pdev, skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE)); 665 xl_priv->xl_rx_ring[i].upfraglen = cpu_to_le32(xl_priv->pkt_buf_sz) | RXUPLASTFRAG; 666 xl_priv->rx_ring_skb[i] = skb ; 667 } 668 669 if (i==0) { 670 printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers. Adapter disabled \n",dev->name) ; 671 free_irq(dev->irq,dev) ; 672 return -EIO ; 673 } 674 675 xl_priv->rx_ring_no = i ; 676 xl_priv->rx_ring_tail = 0 ; 677 xl_priv->rx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_rx_ring, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_TODEVICE) ; 678 for (i=0;i<(xl_priv->rx_ring_no-1);i++) { 679 xl_priv->xl_rx_ring[i].upnextptr = cpu_to_le32(xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * (i+1))); 680 } 681 xl_priv->xl_rx_ring[i].upnextptr = 0 ; 682 683 writel(xl_priv->rx_ring_dma_addr, xl_mmio + MMIO_UPLISTPTR) ; 684 685 /* Setup Tx Ring */ 686 687 xl_priv->tx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_tx_ring, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE,PCI_DMA_TODEVICE) ; 688 689 xl_priv->tx_ring_head = 1 ; 690 xl_priv->tx_ring_tail = 255 ; /* Special marker for first packet */ 691 xl_priv->free_ring_entries = XL_TX_RING_SIZE ; 692 693 /* 694 * Setup the first dummy DPD entry for polling to start working. 695 */ 696 697 xl_priv->xl_tx_ring[0].framestartheader = TXDPDEMPTY; 698 xl_priv->xl_tx_ring[0].buffer = 0 ; 699 xl_priv->xl_tx_ring[0].buffer_length = 0 ; 700 xl_priv->xl_tx_ring[0].dnnextptr = 0 ; 701 702 writel(xl_priv->tx_ring_dma_addr, xl_mmio + MMIO_DNLISTPTR) ; 703 writel(DNUNSTALL, xl_mmio + MMIO_COMMAND) ; 704 writel(UPUNSTALL, xl_mmio + MMIO_COMMAND) ; 705 writel(DNENABLE, xl_mmio + MMIO_COMMAND) ; 706 writeb(0x40, xl_mmio + MMIO_DNPOLL) ; 707 708 /* 709 * Enable interrupts on the card 710 */ 711 712 writel(SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ; 713 writel(SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ; 714 715 netif_start_queue(dev) ; 716 return 0; 717 718} 719 720static int xl_open_hw(struct net_device *dev) 721{ 722 struct xl_private *xl_priv=netdev_priv(dev); 723 u8 __iomem *xl_mmio = xl_priv->xl_mmio ; 724 u16 vsoff ; 725 char ver_str[33]; 726 int open_err ; 727 int i ; 728 unsigned long t ; 729 730 /* 731 * Okay, let's build up the Open.NIC srb command 732 * 733 */ 734 735 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 736 writeb(OPEN_NIC, xl_mmio + MMIO_MACDATA) ; 737 738 /* 739 * Use this as a test byte, if it comes back with the same value, the command didn't work 740 */ 741 742 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb)+ 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 743 writeb(0xff,xl_mmio + MMIO_MACDATA) ; 744 745 /* Open options */ 746 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 747 writeb(0x00, xl_mmio + MMIO_MACDATA) ; 748 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 9, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 749 writeb(0x00, xl_mmio + MMIO_MACDATA) ; 750 751 /* 752 * Node address, be careful here, the docs say you can just put zeros here and it will use 753 * the hardware address, it doesn't, you must include the node address in the open command. 754 */ 755 756 if (xl_priv->xl_laa[0]) { /* If using a LAA address */ 757 for (i=10;i<16;i++) { 758 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 759 writeb(xl_priv->xl_laa[i-10],xl_mmio + MMIO_MACDATA) ; 760 } 761 memcpy(dev->dev_addr,xl_priv->xl_laa,dev->addr_len) ; 762 } else { /* Regular hardware address */ 763 for (i=10;i<16;i++) { 764 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 765 writeb(dev->dev_addr[i-10], xl_mmio + MMIO_MACDATA) ; 766 } 767 } 768 769 /* Default everything else to 0 */ 770 for (i = 16; i < 34; i++) { 771 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 772 writeb(0x00,xl_mmio + MMIO_MACDATA) ; 773 } 774 775 /* 776 * Set the csrb bit in the MISR register 777 */ 778 779 xl_wait_misr_flags(dev) ; 780 writel(MEM_BYTE_WRITE | MF_CSRB, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 781 writeb(0xFF, xl_mmio + MMIO_MACDATA) ; 782 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 783 writeb(MISR_CSRB , xl_mmio + MMIO_MACDATA) ; 784 785 /* 786 * Now wait for the command to run 787 */ 788 789 t=jiffies; 790 while (! (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) { 791 schedule(); 792 if (time_after(jiffies, t + 40 * HZ)) { 793 printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n"); 794 break ; 795 } 796 } 797 798 /* 799 * Let's interpret the open response 800 */ 801 802 writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb)+2, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 803 if (readb(xl_mmio + MMIO_MACDATA)!=0) { 804 open_err = readb(xl_mmio + MMIO_MACDATA) << 8 ; 805 writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb) + 7, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 806 open_err |= readb(xl_mmio + MMIO_MACDATA) ; 807 return open_err ; 808 } else { 809 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 810 xl_priv->asb = swab16(readw(xl_mmio + MMIO_MACDATA)) ; 811 printk(KERN_INFO "%s: Adapter Opened Details: ",dev->name) ; 812 printk("ASB: %04x",xl_priv->asb ) ; 813 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 10, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 814 printk(", SRB: %04x",swab16(readw(xl_mmio + MMIO_MACDATA)) ) ; 815 816 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 12, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 817 xl_priv->arb = swab16(readw(xl_mmio + MMIO_MACDATA)) ; 818 printk(", ARB: %04x \n",xl_priv->arb ) ; 819 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 14, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 820 vsoff = swab16(readw(xl_mmio + MMIO_MACDATA)) ; 821 822 /* 823 * Interesting, sending the individual characters directly to printk was causing klogd to use 824 * use 100% of processor time, so we build up the string and print that instead. 825 */ 826 827 for (i=0;i<0x20;i++) { 828 writel( (MEM_BYTE_READ | 0xD0000 | vsoff) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 829 ver_str[i] = readb(xl_mmio + MMIO_MACDATA) ; 830 } 831 ver_str[i] = '\0' ; 832 printk(KERN_INFO "%s: Microcode version String: %s \n",dev->name,ver_str); 833 } 834 835 /* 836 * Issue the AckInterrupt 837 */ 838 writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; 839 840 return 0 ; 841} 842 843/* 844 * There are two ways of implementing rx on the 359 NIC, either 845 * interrupt driven or polling. We are going to uses interrupts, 846 * it is the easier way of doing things. 847 * 848 * The Rx works with a ring of Rx descriptors. At initialise time the ring 849 * entries point to the next entry except for the last entry in the ring 850 * which points to 0. The card is programmed with the location of the first 851 * available descriptor and keeps reading the next_ptr until next_ptr is set 852 * to 0. Hopefully with a ring size of 16 the card will never get to read a next_ptr 853 * of 0. As the Rx interrupt is received we copy the frame up to the protocol layers 854 * and then point the end of the ring to our current position and point our current 855 * position to 0, therefore making the current position the last position on the ring. 856 * The last position on the ring therefore loops continually loops around the rx ring. 857 * 858 * rx_ring_tail is the position on the ring to process next. (Think of a snake, the head 859 * expands as the card adds new packets and we go around eating the tail processing the 860 * packets.) 861 * 862 * Undoubtably it could be streamlined and improved upon, but at the moment it works 863 * and the fast path through the routine is fine. 864 * 865 * adv_rx_ring could be inlined to increase performance, but its called a *lot* of times 866 * in xl_rx so would increase the size of the function significantly. 867 */ 868 869static void adv_rx_ring(struct net_device *dev) /* Advance rx_ring, cut down on bloat in xl_rx */ 870{ 871 struct xl_private *xl_priv=netdev_priv(dev); 872 int n = xl_priv->rx_ring_tail; 873 int prev_ring_loc; 874 875 prev_ring_loc = (n + XL_RX_RING_SIZE - 1) & (XL_RX_RING_SIZE - 1); 876 xl_priv->xl_rx_ring[prev_ring_loc].upnextptr = cpu_to_le32(xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * n)); 877 xl_priv->xl_rx_ring[n].framestatus = 0; 878 xl_priv->xl_rx_ring[n].upnextptr = 0; 879 xl_priv->rx_ring_tail++; 880 xl_priv->rx_ring_tail &= (XL_RX_RING_SIZE-1); 881} 882 883static void xl_rx(struct net_device *dev) 884{ 885 struct xl_private *xl_priv=netdev_priv(dev); 886 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 887 struct sk_buff *skb, *skb2 ; 888 int frame_length = 0, copy_len = 0 ; 889 int temp_ring_loc ; 890 891 /* 892 * Receive the next frame, loop around the ring until all frames 893 * have been received. 894 */ 895 896 while (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & (RXUPDCOMPLETE | RXUPDFULL) ) { /* Descriptor to process */ 897 898 if (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & RXUPDFULL ) { /* UpdFull, Multiple Descriptors used for the frame */ 899 900 /* 901 * This is a pain, you need to go through all the descriptors until the last one 902 * for this frame to find the framelength 903 */ 904 905 temp_ring_loc = xl_priv->rx_ring_tail ; 906 907 while (xl_priv->xl_rx_ring[temp_ring_loc].framestatus & RXUPDFULL ) { 908 temp_ring_loc++ ; 909 temp_ring_loc &= (XL_RX_RING_SIZE-1) ; 910 } 911 912 frame_length = le32_to_cpu(xl_priv->xl_rx_ring[temp_ring_loc].framestatus) & 0x7FFF; 913 914 skb = dev_alloc_skb(frame_length) ; 915 916 if (skb==NULL) { /* No memory for frame, still need to roll forward the rx ring */ 917 printk(KERN_WARNING "%s: dev_alloc_skb failed - multi buffer !\n", dev->name) ; 918 while (xl_priv->rx_ring_tail != temp_ring_loc) 919 adv_rx_ring(dev) ; 920 921 adv_rx_ring(dev) ; /* One more time just for luck :) */ 922 dev->stats.rx_dropped++ ; 923 924 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ; 925 return ; 926 } 927 928 while (xl_priv->rx_ring_tail != temp_ring_loc) { 929 copy_len = le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen) & 0x7FFF; 930 frame_length -= copy_len ; 931 pci_dma_sync_single_for_cpu(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE); 932 skb_copy_from_linear_data(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail], 933 skb_put(skb, copy_len), 934 copy_len); 935 pci_dma_sync_single_for_device(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE); 936 adv_rx_ring(dev) ; 937 } 938 939 /* Now we have found the last fragment */ 940 pci_dma_sync_single_for_cpu(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE); 941 skb_copy_from_linear_data(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail], 942 skb_put(skb,copy_len), frame_length); 943/* memcpy(skb_put(skb,frame_length), bus_to_virt(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), frame_length) ; */ 944 pci_dma_sync_single_for_device(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE); 945 adv_rx_ring(dev) ; 946 skb->protocol = tr_type_trans(skb,dev) ; 947 netif_rx(skb) ; 948 949 } else { /* Single Descriptor Used, simply swap buffers over, fast path */ 950 951 frame_length = le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus) & 0x7FFF; 952 953 skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ; 954 955 if (skb==NULL) { /* Still need to fix the rx ring */ 956 printk(KERN_WARNING "%s: dev_alloc_skb failed in rx, single buffer \n",dev->name) ; 957 adv_rx_ring(dev) ; 958 dev->stats.rx_dropped++ ; 959 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ; 960 return ; 961 } 962 963 skb2 = xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] ; 964 pci_unmap_single(xl_priv->pdev, le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ; 965 skb_put(skb2, frame_length) ; 966 skb2->protocol = tr_type_trans(skb2,dev) ; 967 968 xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] = skb ; 969 xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr = cpu_to_le32(pci_map_single(xl_priv->pdev,skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE)); 970 xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen = cpu_to_le32(xl_priv->pkt_buf_sz) | RXUPLASTFRAG; 971 adv_rx_ring(dev) ; 972 dev->stats.rx_packets++ ; 973 dev->stats.rx_bytes += frame_length ; 974 975 netif_rx(skb2) ; 976 } /* if multiple buffers */ 977 dev->last_rx = jiffies ; 978 } /* while packet to do */ 979 980 /* Clear the updComplete interrupt */ 981 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ; 982 return ; 983} 984 985/* 986 * This is ruthless, it doesn't care what state the card is in it will 987 * completely reset the adapter. 988 */ 989 990static void xl_reset(struct net_device *dev) 991{ 992 struct xl_private *xl_priv=netdev_priv(dev); 993 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 994 unsigned long t; 995 996 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ; 997 998 /* 999 * Must wait for cmdInProgress bit (12) to clear before continuing with 1000 * card configuration. 1001 */ 1002 1003 t=jiffies; 1004 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { 1005 if (time_after(jiffies, t + 40 * HZ)) { 1006 printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n"); 1007 break ; 1008 } 1009 } 1010 1011} 1012 1013static void xl_freemem(struct net_device *dev) 1014{ 1015 struct xl_private *xl_priv=netdev_priv(dev); 1016 int i ; 1017 1018 for (i=0;i<XL_RX_RING_SIZE;i++) { 1019 dev_kfree_skb_irq(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail]) ; 1020 pci_unmap_single(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE); 1021 xl_priv->rx_ring_tail++ ; 1022 xl_priv->rx_ring_tail &= XL_RX_RING_SIZE-1; 1023 } 1024 1025 /* unmap ring */ 1026 pci_unmap_single(xl_priv->pdev,xl_priv->rx_ring_dma_addr, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_FROMDEVICE) ; 1027 1028 pci_unmap_single(xl_priv->pdev,xl_priv->tx_ring_dma_addr, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE, PCI_DMA_TODEVICE) ; 1029 1030 kfree(xl_priv->xl_rx_ring) ; 1031 kfree(xl_priv->xl_tx_ring) ; 1032 1033 return ; 1034} 1035 1036static irqreturn_t xl_interrupt(int irq, void *dev_id) 1037{ 1038 struct net_device *dev = (struct net_device *)dev_id; 1039 struct xl_private *xl_priv =netdev_priv(dev); 1040 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 1041 u16 intstatus, macstatus ; 1042 1043 intstatus = readw(xl_mmio + MMIO_INTSTATUS) ; 1044 1045 if (!(intstatus & 1)) /* We didn't generate the interrupt */ 1046 return IRQ_NONE; 1047 1048 spin_lock(&xl_priv->xl_lock) ; 1049 1050 /* 1051 * Process the interrupt 1052 */ 1053 /* 1054 * Something fishy going on here, we shouldn't get 0001 ints, not fatal though. 1055 */ 1056 if (intstatus == 0x0001) { 1057 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; 1058 printk(KERN_INFO "%s: 00001 int received \n",dev->name) ; 1059 } else { 1060 if (intstatus & (HOSTERRINT | SRBRINT | ARBCINT | UPCOMPINT | DNCOMPINT | HARDERRINT | (1<<8) | TXUNDERRUN | ASBFINT)) { 1061 1062 /* 1063 * Host Error. 1064 * It may be possible to recover from this, but usually it means something 1065 * is seriously fubar, so we just close the adapter. 1066 */ 1067 1068 if (intstatus & HOSTERRINT) { 1069 printk(KERN_WARNING "%s: Host Error, performing global reset, intstatus = %04x \n",dev->name,intstatus) ; 1070 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ; 1071 printk(KERN_WARNING "%s: Resetting hardware: \n", dev->name); 1072 netif_stop_queue(dev) ; 1073 xl_freemem(dev) ; 1074 free_irq(dev->irq,dev); 1075 xl_reset(dev) ; 1076 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; 1077 spin_unlock(&xl_priv->xl_lock) ; 1078 return IRQ_HANDLED; 1079 } /* Host Error */ 1080 1081 if (intstatus & SRBRINT ) { /* Srbc interrupt */ 1082 writel(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; 1083 if (xl_priv->srb_queued) 1084 xl_srb_bh(dev) ; 1085 } /* SRBR Interrupt */ 1086 1087 if (intstatus & TXUNDERRUN) { /* Issue DnReset command */ 1088 writel(DNRESET, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1089 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { /* Wait for command to run */ 1090 /* !!! FIX-ME !!!! 1091 Must put a timeout check here ! */ 1092 /* Empty Loop */ 1093 } 1094 printk(KERN_WARNING "%s: TX Underrun received \n",dev->name) ; 1095 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; 1096 } /* TxUnderRun */ 1097 1098 if (intstatus & ARBCINT ) { /* Arbc interrupt */ 1099 xl_arb_cmd(dev) ; 1100 } /* Arbc */ 1101 1102 if (intstatus & ASBFINT) { 1103 if (xl_priv->asb_queued == 1) { 1104 xl_asb_cmd(dev) ; 1105 } else if (xl_priv->asb_queued == 2) { 1106 xl_asb_bh(dev) ; 1107 } else { 1108 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ; 1109 } 1110 } /* Asbf */ 1111 1112 if (intstatus & UPCOMPINT ) /* UpComplete */ 1113 xl_rx(dev) ; 1114 1115 if (intstatus & DNCOMPINT ) /* DnComplete */ 1116 xl_dn_comp(dev) ; 1117 1118 if (intstatus & HARDERRINT ) { /* Hardware error */ 1119 writel(MMIO_WORD_READ | MACSTATUS, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1120 macstatus = readw(xl_mmio + MMIO_MACDATA) ; 1121 printk(KERN_WARNING "%s: MacStatusError, details: ", dev->name); 1122 if (macstatus & (1<<14)) 1123 printk(KERN_WARNING "tchk error: Unrecoverable error \n") ; 1124 if (macstatus & (1<<3)) 1125 printk(KERN_WARNING "eint error: Internal watchdog timer expired \n") ; 1126 if (macstatus & (1<<2)) 1127 printk(KERN_WARNING "aint error: Host tried to perform invalid operation \n") ; 1128 printk(KERN_WARNING "Instatus = %02x, macstatus = %02x\n",intstatus,macstatus) ; 1129 printk(KERN_WARNING "%s: Resetting hardware: \n", dev->name); 1130 netif_stop_queue(dev) ; 1131 xl_freemem(dev) ; 1132 free_irq(dev->irq,dev); 1133 unregister_netdev(dev) ; 1134 free_netdev(dev) ; 1135 xl_reset(dev) ; 1136 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; 1137 spin_unlock(&xl_priv->xl_lock) ; 1138 return IRQ_HANDLED; 1139 } 1140 } else { 1141 printk(KERN_WARNING "%s: Received Unknown interrupt : %04x \n", dev->name, intstatus) ; 1142 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; 1143 } 1144 } 1145 1146 /* Turn interrupts back on */ 1147 1148 writel( SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ; 1149 writel( SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ; 1150 1151 spin_unlock(&xl_priv->xl_lock) ; 1152 return IRQ_HANDLED; 1153} 1154 1155/* 1156 * Tx - Polling configuration 1157 */ 1158 1159static int xl_xmit(struct sk_buff *skb, struct net_device *dev) 1160{ 1161 struct xl_private *xl_priv=netdev_priv(dev); 1162 struct xl_tx_desc *txd ; 1163 int tx_head, tx_tail, tx_prev ; 1164 unsigned long flags ; 1165 1166 spin_lock_irqsave(&xl_priv->xl_lock,flags) ; 1167 1168 netif_stop_queue(dev) ; 1169 1170 if (xl_priv->free_ring_entries > 1 ) { 1171 /* 1172 * Set up the descriptor for the packet 1173 */ 1174 tx_head = xl_priv->tx_ring_head ; 1175 tx_tail = xl_priv->tx_ring_tail ; 1176 1177 txd = &(xl_priv->xl_tx_ring[tx_head]) ; 1178 txd->dnnextptr = 0 ; 1179 txd->framestartheader = cpu_to_le32(skb->len) | TXDNINDICATE; 1180 txd->buffer = cpu_to_le32(pci_map_single(xl_priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE)); 1181 txd->buffer_length = cpu_to_le32(skb->len) | TXDNFRAGLAST; 1182 xl_priv->tx_ring_skb[tx_head] = skb ; 1183 dev->stats.tx_packets++ ; 1184 dev->stats.tx_bytes += skb->len ; 1185 1186 /* 1187 * Set the nextptr of the previous descriptor equal to this descriptor, add XL_TX_RING_SIZE -1 1188 * to ensure no negative numbers in unsigned locations. 1189 */ 1190 1191 tx_prev = (xl_priv->tx_ring_head + XL_TX_RING_SIZE - 1) & (XL_TX_RING_SIZE - 1) ; 1192 1193 xl_priv->tx_ring_head++ ; 1194 xl_priv->tx_ring_head &= (XL_TX_RING_SIZE - 1) ; 1195 xl_priv->free_ring_entries-- ; 1196 1197 xl_priv->xl_tx_ring[tx_prev].dnnextptr = cpu_to_le32(xl_priv->tx_ring_dma_addr + (sizeof (struct xl_tx_desc) * tx_head)); 1198 1199 /* Sneaky, by doing a read on DnListPtr we can force the card to poll on the DnNextPtr */ 1200 /* readl(xl_mmio + MMIO_DNLISTPTR) ; */ 1201 1202 netif_wake_queue(dev) ; 1203 1204 spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ; 1205 1206 return 0; 1207 } else { 1208 spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ; 1209 return 1; 1210 } 1211 1212} 1213 1214/* 1215 * The NIC has told us that a packet has been downloaded onto the card, we must 1216 * find out which packet it has done, clear the skb and information for the packet 1217 * then advance around the ring for all tranmitted packets 1218 */ 1219 1220static void xl_dn_comp(struct net_device *dev) 1221{ 1222 struct xl_private *xl_priv=netdev_priv(dev); 1223 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 1224 struct xl_tx_desc *txd ; 1225 1226 1227 if (xl_priv->tx_ring_tail == 255) {/* First time */ 1228 xl_priv->xl_tx_ring[0].framestartheader = 0 ; 1229 xl_priv->xl_tx_ring[0].dnnextptr = 0 ; 1230 xl_priv->tx_ring_tail = 1 ; 1231 } 1232 1233 while (xl_priv->xl_tx_ring[xl_priv->tx_ring_tail].framestartheader & TXDNCOMPLETE ) { 1234 txd = &(xl_priv->xl_tx_ring[xl_priv->tx_ring_tail]) ; 1235 pci_unmap_single(xl_priv->pdev, le32_to_cpu(txd->buffer), xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]->len, PCI_DMA_TODEVICE); 1236 txd->framestartheader = 0 ; 1237 txd->buffer = cpu_to_le32(0xdeadbeef); 1238 txd->buffer_length = 0 ; 1239 dev_kfree_skb_irq(xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]) ; 1240 xl_priv->tx_ring_tail++ ; 1241 xl_priv->tx_ring_tail &= (XL_TX_RING_SIZE - 1) ; 1242 xl_priv->free_ring_entries++ ; 1243 } 1244 1245 netif_wake_queue(dev) ; 1246 1247 writel(ACK_INTERRUPT | DNCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ; 1248} 1249 1250/* 1251 * Close the adapter properly. 1252 * This srb reply cannot be handled from interrupt context as we have 1253 * to free the interrupt from the driver. 1254 */ 1255 1256static int xl_close(struct net_device *dev) 1257{ 1258 struct xl_private *xl_priv = netdev_priv(dev); 1259 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 1260 unsigned long t ; 1261 1262 netif_stop_queue(dev) ; 1263 1264 /* 1265 * Close the adapter, need to stall the rx and tx queues. 1266 */ 1267 1268 writew(DNSTALL, xl_mmio + MMIO_COMMAND) ; 1269 t=jiffies; 1270 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { 1271 schedule(); 1272 if (time_after(jiffies, t + 10 * HZ)) { 1273 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNSTALL not responding.\n", dev->name); 1274 break ; 1275 } 1276 } 1277 writew(DNDISABLE, xl_mmio + MMIO_COMMAND) ; 1278 t=jiffies; 1279 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { 1280 schedule(); 1281 if (time_after(jiffies, t + 10 * HZ)) { 1282 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNDISABLE not responding.\n", dev->name); 1283 break ; 1284 } 1285 } 1286 writew(UPSTALL, xl_mmio + MMIO_COMMAND) ; 1287 t=jiffies; 1288 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { 1289 schedule(); 1290 if (time_after(jiffies, t + 10 * HZ)) { 1291 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPSTALL not responding.\n", dev->name); 1292 break ; 1293 } 1294 } 1295 1296 /* Turn off interrupts, we will still get the indication though 1297 * so we can trap it 1298 */ 1299 1300 writel(SETINTENABLE, xl_mmio + MMIO_COMMAND) ; 1301 1302 xl_srb_cmd(dev,CLOSE_NIC) ; 1303 1304 t=jiffies; 1305 while (!(readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) { 1306 schedule(); 1307 if (time_after(jiffies, t + 10 * HZ)) { 1308 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-CLOSENIC not responding.\n", dev->name); 1309 break ; 1310 } 1311 } 1312 /* Read the srb response from the adapter */ 1313 1314 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD); 1315 if (readb(xl_mmio + MMIO_MACDATA) != CLOSE_NIC) { 1316 printk(KERN_INFO "%s: CLOSE_NIC did not get a CLOSE_NIC response \n",dev->name) ; 1317 } else { 1318 writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1319 if (readb(xl_mmio + MMIO_MACDATA)==0) { 1320 printk(KERN_INFO "%s: Adapter has been closed \n",dev->name) ; 1321 writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; 1322 1323 xl_freemem(dev) ; 1324 free_irq(dev->irq,dev) ; 1325 } else { 1326 printk(KERN_INFO "%s: Close nic command returned error code %02x\n",dev->name, readb(xl_mmio + MMIO_MACDATA)) ; 1327 } 1328 } 1329 1330 /* Reset the upload and download logic */ 1331 1332 writew(UPRESET, xl_mmio + MMIO_COMMAND) ; 1333 t=jiffies; 1334 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { 1335 schedule(); 1336 if (time_after(jiffies, t + 10 * HZ)) { 1337 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPRESET not responding.\n", dev->name); 1338 break ; 1339 } 1340 } 1341 writew(DNRESET, xl_mmio + MMIO_COMMAND) ; 1342 t=jiffies; 1343 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { 1344 schedule(); 1345 if (time_after(jiffies, t + 10 * HZ)) { 1346 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNRESET not responding.\n", dev->name); 1347 break ; 1348 } 1349 } 1350 xl_hw_reset(dev) ; 1351 return 0 ; 1352} 1353 1354static void xl_set_rx_mode(struct net_device *dev) 1355{ 1356 struct xl_private *xl_priv = netdev_priv(dev); 1357 struct dev_mc_list *dmi ; 1358 unsigned char dev_mc_address[4] ; 1359 u16 options ; 1360 int i ; 1361 1362 if (dev->flags & IFF_PROMISC) 1363 options = 0x0004 ; 1364 else 1365 options = 0x0000 ; 1366 1367 if (options ^ xl_priv->xl_copy_all_options) { /* Changed, must send command */ 1368 xl_priv->xl_copy_all_options = options ; 1369 xl_srb_cmd(dev, SET_RECEIVE_MODE) ; 1370 return ; 1371 } 1372 1373 dev_mc_address[0] = dev_mc_address[1] = dev_mc_address[2] = dev_mc_address[3] = 0 ; 1374 1375 for (i=0,dmi=dev->mc_list;i < dev->mc_count; i++,dmi = dmi->next) { 1376 dev_mc_address[0] |= dmi->dmi_addr[2] ; 1377 dev_mc_address[1] |= dmi->dmi_addr[3] ; 1378 dev_mc_address[2] |= dmi->dmi_addr[4] ; 1379 dev_mc_address[3] |= dmi->dmi_addr[5] ; 1380 } 1381 1382 if (memcmp(xl_priv->xl_functional_addr,dev_mc_address,4) != 0) { /* Options have changed, run the command */ 1383 memcpy(xl_priv->xl_functional_addr, dev_mc_address,4) ; 1384 xl_srb_cmd(dev, SET_FUNC_ADDRESS) ; 1385 } 1386 return ; 1387} 1388 1389 1390/* 1391 * We issued an srb command and now we must read 1392 * the response from the completed command. 1393 */ 1394 1395static void xl_srb_bh(struct net_device *dev) 1396{ 1397 struct xl_private *xl_priv = netdev_priv(dev); 1398 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 1399 u8 srb_cmd, ret_code ; 1400 int i ; 1401 1402 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1403 srb_cmd = readb(xl_mmio + MMIO_MACDATA) ; 1404 writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1405 ret_code = readb(xl_mmio + MMIO_MACDATA) ; 1406 1407 /* Ret_code is standard across all commands */ 1408 1409 switch (ret_code) { 1410 case 1: 1411 printk(KERN_INFO "%s: Command: %d - Invalid Command code\n",dev->name,srb_cmd) ; 1412 break ; 1413 case 4: 1414 printk(KERN_INFO "%s: Command: %d - Adapter is closed, must be open for this command \n",dev->name,srb_cmd) ; 1415 break ; 1416 1417 case 6: 1418 printk(KERN_INFO "%s: Command: %d - Options Invalid for command \n",dev->name,srb_cmd) ; 1419 break ; 1420 1421 case 0: /* Successful command execution */ 1422 switch (srb_cmd) { 1423 case READ_LOG: /* Returns 14 bytes of data from the NIC */ 1424 if(xl_priv->xl_message_level) 1425 printk(KERN_INFO "%s: READ.LOG 14 bytes of data ",dev->name) ; 1426 /* 1427 * We still have to read the log even if message_level = 0 and we don't want 1428 * to see it 1429 */ 1430 for (i=0;i<14;i++) { 1431 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1432 if(xl_priv->xl_message_level) 1433 printk("%02x:",readb(xl_mmio + MMIO_MACDATA)) ; 1434 } 1435 printk("\n") ; 1436 break ; 1437 case SET_FUNC_ADDRESS: 1438 if(xl_priv->xl_message_level) 1439 printk(KERN_INFO "%s: Functional Address Set \n",dev->name) ; 1440 break ; 1441 case CLOSE_NIC: 1442 if(xl_priv->xl_message_level) 1443 printk(KERN_INFO "%s: Received CLOSE_NIC interrupt in interrupt handler \n",dev->name) ; 1444 break ; 1445 case SET_MULTICAST_MODE: 1446 if(xl_priv->xl_message_level) 1447 printk(KERN_INFO "%s: Multicast options successfully changed\n",dev->name) ; 1448 break ; 1449 case SET_RECEIVE_MODE: 1450 if(xl_priv->xl_message_level) { 1451 if (xl_priv->xl_copy_all_options == 0x0004) 1452 printk(KERN_INFO "%s: Entering promiscuous mode \n", dev->name) ; 1453 else 1454 printk(KERN_INFO "%s: Entering normal receive mode \n",dev->name) ; 1455 } 1456 break ; 1457 1458 } /* switch */ 1459 break ; 1460 } /* switch */ 1461 return ; 1462} 1463 1464static int xl_set_mac_address (struct net_device *dev, void *addr) 1465{ 1466 struct sockaddr *saddr = addr ; 1467 struct xl_private *xl_priv = netdev_priv(dev); 1468 1469 if (netif_running(dev)) { 1470 printk(KERN_WARNING "%s: Cannot set mac/laa address while card is open\n", dev->name) ; 1471 return -EIO ; 1472 } 1473 1474 memcpy(xl_priv->xl_laa, saddr->sa_data,dev->addr_len) ; 1475 1476 if (xl_priv->xl_message_level) { 1477 printk(KERN_INFO "%s: MAC/LAA Set to = %x.%x.%x.%x.%x.%x\n",dev->name, xl_priv->xl_laa[0], 1478 xl_priv->xl_laa[1], xl_priv->xl_laa[2], 1479 xl_priv->xl_laa[3], xl_priv->xl_laa[4], 1480 xl_priv->xl_laa[5]); 1481 } 1482 1483 return 0 ; 1484} 1485 1486static void xl_arb_cmd(struct net_device *dev) 1487{ 1488 struct xl_private *xl_priv = netdev_priv(dev); 1489 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 1490 u8 arb_cmd ; 1491 u16 lan_status, lan_status_diff ; 1492 1493 writel( ( MEM_BYTE_READ | 0xD0000 | xl_priv->arb), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1494 arb_cmd = readb(xl_mmio + MMIO_MACDATA) ; 1495 1496 if (arb_cmd == RING_STATUS_CHANGE) { /* Ring.Status.Change */ 1497 writel( ( (MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1498 1499 printk(KERN_INFO "%s: Ring Status Change: New Status = %04x\n", dev->name, swab16(readw(xl_mmio + MMIO_MACDATA) )) ; 1500 1501 lan_status = swab16(readw(xl_mmio + MMIO_MACDATA)); 1502 1503 /* Acknowledge interrupt, this tells nic we are done with the arb */ 1504 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; 1505 1506 lan_status_diff = xl_priv->xl_lan_status ^ lan_status ; 1507 1508 if (lan_status_diff & (LSC_LWF | LSC_ARW | LSC_FPE | LSC_RR) ) { 1509 if (lan_status_diff & LSC_LWF) 1510 printk(KERN_WARNING "%s: Short circuit detected on the lobe\n",dev->name); 1511 if (lan_status_diff & LSC_ARW) 1512 printk(KERN_WARNING "%s: Auto removal error\n",dev->name); 1513 if (lan_status_diff & LSC_FPE) 1514 printk(KERN_WARNING "%s: FDX Protocol Error\n",dev->name); 1515 if (lan_status_diff & LSC_RR) 1516 printk(KERN_WARNING "%s: Force remove MAC frame received\n",dev->name); 1517 1518 /* Adapter has been closed by the hardware */ 1519 1520 netif_stop_queue(dev); 1521 xl_freemem(dev) ; 1522 free_irq(dev->irq,dev); 1523 1524 printk(KERN_WARNING "%s: Adapter has been closed \n", dev->name) ; 1525 } /* If serious error */ 1526 1527 if (xl_priv->xl_message_level) { 1528 if (lan_status_diff & LSC_SIG_LOSS) 1529 printk(KERN_WARNING "%s: No receive signal detected \n", dev->name) ; 1530 if (lan_status_diff & LSC_HARD_ERR) 1531 printk(KERN_INFO "%s: Beaconing \n",dev->name); 1532 if (lan_status_diff & LSC_SOFT_ERR) 1533 printk(KERN_WARNING "%s: Adapter transmitted Soft Error Report Mac Frame \n",dev->name); 1534 if (lan_status_diff & LSC_TRAN_BCN) 1535 printk(KERN_INFO "%s: We are tranmitting the beacon, aaah\n",dev->name); 1536 if (lan_status_diff & LSC_SS) 1537 printk(KERN_INFO "%s: Single Station on the ring \n", dev->name); 1538 if (lan_status_diff & LSC_RING_REC) 1539 printk(KERN_INFO "%s: Ring recovery ongoing\n",dev->name); 1540 if (lan_status_diff & LSC_FDX_MODE) 1541 printk(KERN_INFO "%s: Operating in FDX mode\n",dev->name); 1542 } 1543 1544 if (lan_status_diff & LSC_CO) { 1545 if (xl_priv->xl_message_level) 1546 printk(KERN_INFO "%s: Counter Overflow \n", dev->name); 1547 /* Issue READ.LOG command */ 1548 xl_srb_cmd(dev, READ_LOG) ; 1549 } 1550 1551 /* There is no command in the tech docs to issue the read_sr_counters */ 1552 if (lan_status_diff & LSC_SR_CO) { 1553 if (xl_priv->xl_message_level) 1554 printk(KERN_INFO "%s: Source routing counters overflow\n", dev->name); 1555 } 1556 1557 xl_priv->xl_lan_status = lan_status ; 1558 1559 } /* Lan.change.status */ 1560 else if ( arb_cmd == RECEIVE_DATA) { /* Received.Data */ 1561#if XL_DEBUG 1562 printk(KERN_INFO "Received.Data \n") ; 1563#endif 1564 writel( ((MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1565 xl_priv->mac_buffer = swab16(readw(xl_mmio + MMIO_MACDATA)) ; 1566 1567 /* Now we are going to be really basic here and not do anything 1568 * with the data at all. The tech docs do not give me enough 1569 * information to calculate the buffers properly so we're 1570 * just going to tell the nic that we've dealt with the frame 1571 * anyway. 1572 */ 1573 1574 dev->last_rx = jiffies ; 1575 /* Acknowledge interrupt, this tells nic we are done with the arb */ 1576 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; 1577 1578 /* Is the ASB free ? */ 1579 1580 xl_priv->asb_queued = 0 ; 1581 writel( ((MEM_BYTE_READ | 0xD0000 | xl_priv->asb) + 2), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1582 if (readb(xl_mmio + MMIO_MACDATA) != 0xff) { 1583 xl_priv->asb_queued = 1 ; 1584 1585 xl_wait_misr_flags(dev) ; 1586 1587 writel(MEM_BYTE_WRITE | MF_ASBFR, xl_mmio + MMIO_MAC_ACCESS_CMD); 1588 writeb(0xff, xl_mmio + MMIO_MACDATA) ; 1589 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1590 writeb(MISR_ASBFR, xl_mmio + MMIO_MACDATA) ; 1591 return ; 1592 /* Drop out and wait for the bottom half to be run */ 1593 } 1594 1595 xl_asb_cmd(dev) ; 1596 1597 } else { 1598 printk(KERN_WARNING "%s: Received unknown arb (xl_priv) command: %02x \n",dev->name,arb_cmd) ; 1599 } 1600 1601 /* Acknowledge the arb interrupt */ 1602 1603 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ; 1604 1605 return ; 1606} 1607 1608 1609/* 1610 * There is only one asb command, but we can get called from different 1611 * places. 1612 */ 1613 1614static void xl_asb_cmd(struct net_device *dev) 1615{ 1616 struct xl_private *xl_priv = netdev_priv(dev); 1617 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 1618 1619 if (xl_priv->asb_queued == 1) 1620 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ; 1621 1622 writel(MEM_BYTE_WRITE | 0xd0000 | xl_priv->asb, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1623 writeb(0x81, xl_mmio + MMIO_MACDATA) ; 1624 1625 writel(MEM_WORD_WRITE | 0xd0000 | xl_priv->asb | 6, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1626 writew(swab16(xl_priv->mac_buffer), xl_mmio + MMIO_MACDATA) ; 1627 1628 xl_wait_misr_flags(dev) ; 1629 1630 writel(MEM_BYTE_WRITE | MF_RASB, xl_mmio + MMIO_MAC_ACCESS_CMD); 1631 writeb(0xff, xl_mmio + MMIO_MACDATA) ; 1632 1633 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1634 writeb(MISR_RASB, xl_mmio + MMIO_MACDATA) ; 1635 1636 xl_priv->asb_queued = 2 ; 1637 1638 return ; 1639} 1640 1641/* 1642 * This will only get called if there was an error 1643 * from the asb cmd. 1644 */ 1645static void xl_asb_bh(struct net_device *dev) 1646{ 1647 struct xl_private *xl_priv = netdev_priv(dev); 1648 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 1649 u8 ret_code ; 1650 1651 writel(MMIO_BYTE_READ | 0xd0000 | xl_priv->asb | 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1652 ret_code = readb(xl_mmio + MMIO_MACDATA) ; 1653 switch (ret_code) { 1654 case 0x01: 1655 printk(KERN_INFO "%s: ASB Command, unrecognized command code \n",dev->name) ; 1656 break ; 1657 case 0x26: 1658 printk(KERN_INFO "%s: ASB Command, unexpected receive buffer \n", dev->name) ; 1659 break ; 1660 case 0x40: 1661 printk(KERN_INFO "%s: ASB Command, Invalid Station ID \n", dev->name) ; 1662 break ; 1663 } 1664 xl_priv->asb_queued = 0 ; 1665 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ; 1666 return ; 1667} 1668 1669/* 1670 * Issue srb commands to the nic 1671 */ 1672 1673static void xl_srb_cmd(struct net_device *dev, int srb_cmd) 1674{ 1675 struct xl_private *xl_priv = netdev_priv(dev); 1676 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 1677 1678 switch (srb_cmd) { 1679 case READ_LOG: 1680 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1681 writeb(READ_LOG, xl_mmio + MMIO_MACDATA) ; 1682 break; 1683 1684 case CLOSE_NIC: 1685 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1686 writeb(CLOSE_NIC, xl_mmio + MMIO_MACDATA) ; 1687 break ; 1688 1689 case SET_RECEIVE_MODE: 1690 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1691 writeb(SET_RECEIVE_MODE, xl_mmio + MMIO_MACDATA) ; 1692 writel(MEM_WORD_WRITE | 0xD0000 | xl_priv->srb | 4, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1693 writew(xl_priv->xl_copy_all_options, xl_mmio + MMIO_MACDATA) ; 1694 break ; 1695 1696 case SET_FUNC_ADDRESS: 1697 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1698 writeb(SET_FUNC_ADDRESS, xl_mmio + MMIO_MACDATA) ; 1699 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 6 , xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1700 writeb(xl_priv->xl_functional_addr[0], xl_mmio + MMIO_MACDATA) ; 1701 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 7 , xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1702 writeb(xl_priv->xl_functional_addr[1], xl_mmio + MMIO_MACDATA) ; 1703 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 8 , xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1704 writeb(xl_priv->xl_functional_addr[2], xl_mmio + MMIO_MACDATA) ; 1705 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 9 , xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1706 writeb(xl_priv->xl_functional_addr[3], xl_mmio + MMIO_MACDATA) ; 1707 break ; 1708 } /* switch */ 1709 1710 1711 xl_wait_misr_flags(dev) ; 1712 1713 /* Write 0xff to the CSRB flag */ 1714 writel(MEM_BYTE_WRITE | MF_CSRB , xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1715 writeb(0xFF, xl_mmio + MMIO_MACDATA) ; 1716 /* Set csrb bit in MISR register to process command */ 1717 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1718 writeb(MISR_CSRB, xl_mmio + MMIO_MACDATA) ; 1719 xl_priv->srb_queued = 1 ; 1720 1721 return ; 1722} 1723 1724/* 1725 * This is nasty, to use the MISR command you have to wait for 6 memory locations 1726 * to be zero. This is the way the driver does on other OS'es so we should be ok with 1727 * the empty loop. 1728 */ 1729 1730static void xl_wait_misr_flags(struct net_device *dev) 1731{ 1732 struct xl_private *xl_priv = netdev_priv(dev); 1733 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 1734 1735 int i ; 1736 1737 writel(MMIO_BYTE_READ | MISR_RW, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1738 if (readb(xl_mmio + MMIO_MACDATA) != 0) { /* Misr not clear */ 1739 for (i=0; i<6; i++) { 1740 writel(MEM_BYTE_READ | 0xDFFE0 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1741 while (readb(xl_mmio + MMIO_MACDATA) != 0 ) {} ; /* Empty Loop */ 1742 } 1743 } 1744 1745 writel(MMIO_BYTE_WRITE | MISR_AND, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1746 writeb(0x80, xl_mmio + MMIO_MACDATA) ; 1747 1748 return ; 1749} 1750 1751/* 1752 * Change mtu size, this should work the same as olympic 1753 */ 1754 1755static int xl_change_mtu(struct net_device *dev, int mtu) 1756{ 1757 struct xl_private *xl_priv = netdev_priv(dev); 1758 u16 max_mtu ; 1759 1760 if (xl_priv->xl_ring_speed == 4) 1761 max_mtu = 4500 ; 1762 else 1763 max_mtu = 18000 ; 1764 1765 if (mtu > max_mtu) 1766 return -EINVAL ; 1767 if (mtu < 100) 1768 return -EINVAL ; 1769 1770 dev->mtu = mtu ; 1771 xl_priv->pkt_buf_sz = mtu + TR_HLEN ; 1772 1773 return 0 ; 1774} 1775 1776static void __devexit xl_remove_one (struct pci_dev *pdev) 1777{ 1778 struct net_device *dev = pci_get_drvdata(pdev); 1779 struct xl_private *xl_priv=netdev_priv(dev); 1780 1781 unregister_netdev(dev); 1782 iounmap(xl_priv->xl_mmio) ; 1783 pci_release_regions(pdev) ; 1784 pci_set_drvdata(pdev,NULL) ; 1785 free_netdev(dev); 1786 return ; 1787} 1788 1789static struct pci_driver xl_3c359_driver = { 1790 .name = "3c359", 1791 .id_table = xl_pci_tbl, 1792 .probe = xl_probe, 1793 .remove = __devexit_p(xl_remove_one), 1794}; 1795 1796static int __init xl_pci_init (void) 1797{ 1798 return pci_register_driver(&xl_3c359_driver); 1799} 1800 1801 1802static void __exit xl_pci_cleanup (void) 1803{ 1804 pci_unregister_driver (&xl_3c359_driver); 1805} 1806 1807module_init(xl_pci_init); 1808module_exit(xl_pci_cleanup); 1809 1810MODULE_LICENSE("GPL") ;