tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * QUICC Engine (QE) external definitions and structure.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef _ASM_POWERPC_QE_H
16#define _ASM_POWERPC_QE_H
17#ifdef __KERNEL__
18
19#include <asm/immap_qe.h>
20
21#define QE_NUM_OF_SNUM 28
22#define QE_NUM_OF_BRGS 16
23#define QE_NUM_OF_PORTS 1024
24
25/* Memory partitions
26*/
27#define MEM_PART_SYSTEM 0
28#define MEM_PART_SECONDARY 1
29#define MEM_PART_MURAM 2
30
31/* Clocks and BRGs */
32enum qe_clock {
33 QE_CLK_NONE = 0,
34 QE_BRG1, /* Baud Rate Generator 1 */
35 QE_BRG2, /* Baud Rate Generator 2 */
36 QE_BRG3, /* Baud Rate Generator 3 */
37 QE_BRG4, /* Baud Rate Generator 4 */
38 QE_BRG5, /* Baud Rate Generator 5 */
39 QE_BRG6, /* Baud Rate Generator 6 */
40 QE_BRG7, /* Baud Rate Generator 7 */
41 QE_BRG8, /* Baud Rate Generator 8 */
42 QE_BRG9, /* Baud Rate Generator 9 */
43 QE_BRG10, /* Baud Rate Generator 10 */
44 QE_BRG11, /* Baud Rate Generator 11 */
45 QE_BRG12, /* Baud Rate Generator 12 */
46 QE_BRG13, /* Baud Rate Generator 13 */
47 QE_BRG14, /* Baud Rate Generator 14 */
48 QE_BRG15, /* Baud Rate Generator 15 */
49 QE_BRG16, /* Baud Rate Generator 16 */
50 QE_CLK1, /* Clock 1 */
51 QE_CLK2, /* Clock 2 */
52 QE_CLK3, /* Clock 3 */
53 QE_CLK4, /* Clock 4 */
54 QE_CLK5, /* Clock 5 */
55 QE_CLK6, /* Clock 6 */
56 QE_CLK7, /* Clock 7 */
57 QE_CLK8, /* Clock 8 */
58 QE_CLK9, /* Clock 9 */
59 QE_CLK10, /* Clock 10 */
60 QE_CLK11, /* Clock 11 */
61 QE_CLK12, /* Clock 12 */
62 QE_CLK13, /* Clock 13 */
63 QE_CLK14, /* Clock 14 */
64 QE_CLK15, /* Clock 15 */
65 QE_CLK16, /* Clock 16 */
66 QE_CLK17, /* Clock 17 */
67 QE_CLK18, /* Clock 18 */
68 QE_CLK19, /* Clock 19 */
69 QE_CLK20, /* Clock 20 */
70 QE_CLK21, /* Clock 21 */
71 QE_CLK22, /* Clock 22 */
72 QE_CLK23, /* Clock 23 */
73 QE_CLK24, /* Clock 24 */
74 QE_CLK_DUMMY
75};
76
77/* Export QE common operations */
78extern void qe_reset(void);
79extern int par_io_init(struct device_node *np);
80extern int par_io_of_config(struct device_node *np);
81extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
82 int assignment, int has_irq);
83extern int par_io_data_set(u8 port, u8 pin, u8 val);
84
85/* QE internal API */
86int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
87enum qe_clock qe_clock_source(const char *source);
88unsigned int qe_get_brg_clk(void);
89int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
90int qe_get_snum(void);
91void qe_put_snum(u8 snum);
92unsigned long qe_muram_alloc(int size, int align);
93int qe_muram_free(unsigned long offset);
94unsigned long qe_muram_alloc_fixed(unsigned long offset, int size);
95void qe_muram_dump(void);
96
97static inline void __iomem *qe_muram_addr(unsigned long offset)
98{
99 return (void __iomem *)&qe_immr->muram[offset];
100}
101
102static inline unsigned long qe_muram_offset(void __iomem *addr)
103{
104 return addr - (void __iomem *)qe_immr->muram;
105}
106
107/* Structure that defines QE firmware binary files.
108 *
109 * See Documentation/powerpc/qe-firmware.txt for a description of these
110 * fields.
111 */
112struct qe_firmware {
113 struct qe_header {
114 __be32 length; /* Length of the entire structure, in bytes */
115 u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
116 u8 version; /* Version of this layout. First ver is '1' */
117 } header;
118 u8 id[62]; /* Null-terminated identifier string */
119 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
120 u8 count; /* Number of microcode[] structures */
121 struct {
122 __be16 model; /* The SOC model */
123 u8 major; /* The SOC revision major */
124 u8 minor; /* The SOC revision minor */
125 } __attribute__ ((packed)) soc;
126 u8 padding[4]; /* Reserved, for alignment */
127 __be64 extended_modes; /* Extended modes */
128 __be32 vtraps[8]; /* Virtual trap addresses */
129 u8 reserved[4]; /* Reserved, for future expansion */
130 struct qe_microcode {
131 u8 id[32]; /* Null-terminated identifier */
132 __be32 traps[16]; /* Trap addresses, 0 == ignore */
133 __be32 eccr; /* The value for the ECCR register */
134 __be32 iram_offset; /* Offset into I-RAM for the code */
135 __be32 count; /* Number of 32-bit words of the code */
136 __be32 code_offset; /* Offset of the actual microcode */
137 u8 major; /* The microcode version major */
138 u8 minor; /* The microcode version minor */
139 u8 revision; /* The microcode version revision */
140 u8 padding; /* Reserved, for alignment */
141 u8 reserved[4]; /* Reserved, for future expansion */
142 } __attribute__ ((packed)) microcode[1];
143 /* All microcode binaries should be located here */
144 /* CRC32 should be located here, after the microcode binaries */
145} __attribute__ ((packed));
146
147struct qe_firmware_info {
148 char id[64]; /* Firmware name */
149 u32 vtraps[8]; /* Virtual trap addresses */
150 u64 extended_modes; /* Extended modes */
151};
152
153/* Upload a firmware to the QE */
154int qe_upload_firmware(const struct qe_firmware *firmware);
155
156/* Obtain information on the uploaded firmware */
157struct qe_firmware_info *qe_get_firmware_info(void);
158
159/* Buffer descriptors */
160struct qe_bd {
161 __be16 status;
162 __be16 length;
163 __be32 buf;
164} __attribute__ ((packed));
165
166#define BD_STATUS_MASK 0xffff0000
167#define BD_LENGTH_MASK 0x0000ffff
168
169#define BD_SC_EMPTY 0x8000 /* Receive is empty */
170#define BD_SC_READY 0x8000 /* Transmit is ready */
171#define BD_SC_WRAP 0x2000 /* Last buffer descriptor */
172#define BD_SC_INTRPT 0x1000 /* Interrupt on change */
173#define BD_SC_LAST 0x0800 /* Last buffer in frame */
174#define BD_SC_CM 0x0200 /* Continous mode */
175#define BD_SC_ID 0x0100 /* Rec'd too many idles */
176#define BD_SC_P 0x0100 /* xmt preamble */
177#define BD_SC_BR 0x0020 /* Break received */
178#define BD_SC_FR 0x0010 /* Framing error */
179#define BD_SC_PR 0x0008 /* Parity error */
180#define BD_SC_OV 0x0002 /* Overrun */
181#define BD_SC_CD 0x0001 /* ?? */
182
183/* Alignment */
184#define QE_INTR_TABLE_ALIGN 16 /* ??? */
185#define QE_ALIGNMENT_OF_BD 8
186#define QE_ALIGNMENT_OF_PRAM 64
187
188/* RISC allocation */
189enum qe_risc_allocation {
190 QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */
191 QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */
192 QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* Dynamically choose
193 RISC 1 or RISC 2 */
194};
195
196/* QE extended filtering Table Lookup Key Size */
197enum qe_fltr_tbl_lookup_key_size {
198 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
199 = 0x3f, /* LookupKey parsed by the Generate LookupKey
200 CMD is truncated to 8 bytes */
201 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
202 = 0x5f, /* LookupKey parsed by the Generate LookupKey
203 CMD is truncated to 16 bytes */
204};
205
206/* QE FLTR extended filtering Largest External Table Lookup Key Size */
207enum qe_fltr_largest_external_tbl_lookup_key_size {
208 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
209 = 0x0,/* not used */
210 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
211 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */
212 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
213 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */
214};
215
216/* structure representing QE parameter RAM */
217struct qe_timer_tables {
218 u16 tm_base; /* QE timer table base adr */
219 u16 tm_ptr; /* QE timer table pointer */
220 u16 r_tmr; /* QE timer mode register */
221 u16 r_tmv; /* QE timer valid register */
222 u32 tm_cmd; /* QE timer cmd register */
223 u32 tm_cnt; /* QE timer internal cnt */
224} __attribute__ ((packed));
225
226#define QE_FLTR_TAD_SIZE 8
227
228/* QE extended filtering Termination Action Descriptor (TAD) */
229struct qe_fltr_tad {
230 u8 serialized[QE_FLTR_TAD_SIZE];
231} __attribute__ ((packed));
232
233/* Communication Direction */
234enum comm_dir {
235 COMM_DIR_NONE = 0,
236 COMM_DIR_RX = 1,
237 COMM_DIR_TX = 2,
238 COMM_DIR_RX_AND_TX = 3
239};
240
241/* QE CMXUCR Registers.
242 * There are two UCCs represented in each of the four CMXUCR registers.
243 * These values are for the UCC in the LSBs
244 */
245#define QE_CMXUCR_MII_ENET_MNG 0x00007000
246#define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
247#define QE_CMXUCR_GRANT 0x00008000
248#define QE_CMXUCR_TSA 0x00004000
249#define QE_CMXUCR_BKPT 0x00000100
250#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
251
252/* QE CMXGCR Registers.
253*/
254#define QE_CMXGCR_MII_ENET_MNG 0x00007000
255#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
256#define QE_CMXGCR_USBCS 0x0000000f
257
258/* QE CECR Commands.
259*/
260#define QE_CR_FLG 0x00010000
261#define QE_RESET 0x80000000
262#define QE_INIT_TX_RX 0x00000000
263#define QE_INIT_RX 0x00000001
264#define QE_INIT_TX 0x00000002
265#define QE_ENTER_HUNT_MODE 0x00000003
266#define QE_STOP_TX 0x00000004
267#define QE_GRACEFUL_STOP_TX 0x00000005
268#define QE_RESTART_TX 0x00000006
269#define QE_CLOSE_RX_BD 0x00000007
270#define QE_SWITCH_COMMAND 0x00000007
271#define QE_SET_GROUP_ADDRESS 0x00000008
272#define QE_START_IDMA 0x00000009
273#define QE_MCC_STOP_RX 0x00000009
274#define QE_ATM_TRANSMIT 0x0000000a
275#define QE_HPAC_CLEAR_ALL 0x0000000b
276#define QE_GRACEFUL_STOP_RX 0x0000001a
277#define QE_RESTART_RX 0x0000001b
278#define QE_HPAC_SET_PRIORITY 0x0000010b
279#define QE_HPAC_STOP_TX 0x0000020b
280#define QE_HPAC_STOP_RX 0x0000030b
281#define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
282#define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
283#define QE_HPAC_START_TX 0x0000060b
284#define QE_HPAC_START_RX 0x0000070b
285#define QE_USB_STOP_TX 0x0000000a
286#define QE_USB_RESTART_TX 0x0000000b
287#define QE_QMC_STOP_TX 0x0000000c
288#define QE_QMC_STOP_RX 0x0000000d
289#define QE_SS7_SU_FIL_RESET 0x0000000e
290/* jonathbr added from here down for 83xx */
291#define QE_RESET_BCS 0x0000000a
292#define QE_MCC_INIT_TX_RX_16 0x00000003
293#define QE_MCC_STOP_TX 0x00000004
294#define QE_MCC_INIT_TX_1 0x00000005
295#define QE_MCC_INIT_RX_1 0x00000006
296#define QE_MCC_RESET 0x00000007
297#define QE_SET_TIMER 0x00000008
298#define QE_RANDOM_NUMBER 0x0000000c
299#define QE_ATM_MULTI_THREAD_INIT 0x00000011
300#define QE_ASSIGN_PAGE 0x00000012
301#define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
302#define QE_START_FLOW_CONTROL 0x00000014
303#define QE_STOP_FLOW_CONTROL 0x00000015
304#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
305
306#define QE_ASSIGN_RISC 0x00000010
307#define QE_CR_MCN_NORMAL_SHIFT 6
308#define QE_CR_MCN_USB_SHIFT 4
309#define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
310#define QE_CR_SNUM_SHIFT 17
311
312/* QE CECR Sub Block - sub block of QE command.
313*/
314#define QE_CR_SUBBLOCK_INVALID 0x00000000
315#define QE_CR_SUBBLOCK_USB 0x03200000
316#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
317#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
318#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
319#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
320#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
321#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
322#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
323#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
324#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
325#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
326#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
327#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
328#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
329#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
330#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
331#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
332#define QE_CR_SUBBLOCK_MCC1 0x03800000
333#define QE_CR_SUBBLOCK_MCC2 0x03a00000
334#define QE_CR_SUBBLOCK_MCC3 0x03000000
335#define QE_CR_SUBBLOCK_IDMA1 0x02800000
336#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
337#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
338#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
339#define QE_CR_SUBBLOCK_HPAC 0x01e00000
340#define QE_CR_SUBBLOCK_SPI1 0x01400000
341#define QE_CR_SUBBLOCK_SPI2 0x01600000
342#define QE_CR_SUBBLOCK_RAND 0x01c00000
343#define QE_CR_SUBBLOCK_TIMER 0x01e00000
344#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
345
346/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
347#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
348#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
349#define QE_CR_PROTOCOL_QMC 0x02
350#define QE_CR_PROTOCOL_UART 0x04
351#define QE_CR_PROTOCOL_ATM_POS 0x0A
352#define QE_CR_PROTOCOL_ETHERNET 0x0C
353#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
354
355/* BRG configuration register */
356#define QE_BRGC_ENABLE 0x00010000
357#define QE_BRGC_DIVISOR_SHIFT 1
358#define QE_BRGC_DIVISOR_MAX 0xFFF
359#define QE_BRGC_DIV16 1
360
361/* QE Timers registers */
362#define QE_GTCFR1_PCAS 0x80
363#define QE_GTCFR1_STP2 0x20
364#define QE_GTCFR1_RST2 0x10
365#define QE_GTCFR1_GM2 0x08
366#define QE_GTCFR1_GM1 0x04
367#define QE_GTCFR1_STP1 0x02
368#define QE_GTCFR1_RST1 0x01
369
370/* SDMA registers */
371#define QE_SDSR_BER1 0x02000000
372#define QE_SDSR_BER2 0x01000000
373
374#define QE_SDMR_GLB_1_MSK 0x80000000
375#define QE_SDMR_ADR_SEL 0x20000000
376#define QE_SDMR_BER1_MSK 0x02000000
377#define QE_SDMR_BER2_MSK 0x01000000
378#define QE_SDMR_EB1_MSK 0x00800000
379#define QE_SDMR_ER1_MSK 0x00080000
380#define QE_SDMR_ER2_MSK 0x00040000
381#define QE_SDMR_CEN_MASK 0x0000E000
382#define QE_SDMR_SBER_1 0x00000200
383#define QE_SDMR_SBER_2 0x00000200
384#define QE_SDMR_EB1_PR_MASK 0x000000C0
385#define QE_SDMR_ER1_PR 0x00000008
386
387#define QE_SDMR_CEN_SHIFT 13
388#define QE_SDMR_EB1_PR_SHIFT 6
389
390#define QE_SDTM_MSNUM_SHIFT 24
391
392#define QE_SDEBCR_BA_MASK 0x01FFFFFF
393
394/* Communication Processor */
395#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
396#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
397#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
398
399/* I-RAM */
400#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
401#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
402
403/* UPC */
404#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
405#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
406#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
407#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
408#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
409
410/* UCC GUEMR register */
411#define UCC_GUEMR_MODE_MASK_RX 0x02
412#define UCC_GUEMR_MODE_FAST_RX 0x02
413#define UCC_GUEMR_MODE_SLOW_RX 0x00
414#define UCC_GUEMR_MODE_MASK_TX 0x01
415#define UCC_GUEMR_MODE_FAST_TX 0x01
416#define UCC_GUEMR_MODE_SLOW_TX 0x00
417#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
418#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
419 must be set 1 */
420
421/* structure representing UCC SLOW parameter RAM */
422struct ucc_slow_pram {
423 __be16 rbase; /* RX BD base address */
424 __be16 tbase; /* TX BD base address */
425 u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */
426 u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */
427 __be16 mrblr; /* Rx buffer length */
428 __be32 rstate; /* Rx internal state */
429 __be32 rptr; /* Rx internal data pointer */
430 __be16 rbptr; /* rb BD Pointer */
431 __be16 rcount; /* Rx internal byte count */
432 __be32 rtemp; /* Rx temp */
433 __be32 tstate; /* Tx internal state */
434 __be32 tptr; /* Tx internal data pointer */
435 __be16 tbptr; /* Tx BD pointer */
436 __be16 tcount; /* Tx byte count */
437 __be32 ttemp; /* Tx temp */
438 __be32 rcrc; /* temp receive CRC */
439 __be32 tcrc; /* temp transmit CRC */
440} __attribute__ ((packed));
441
442/* General UCC SLOW Mode Register (GUMRH & GUMRL) */
443#define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000
444#define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000
445#define UCC_SLOW_GUMR_H_REVD 0x00002000
446#define UCC_SLOW_GUMR_H_TRX 0x00001000
447#define UCC_SLOW_GUMR_H_TTX 0x00000800
448#define UCC_SLOW_GUMR_H_CDP 0x00000400
449#define UCC_SLOW_GUMR_H_CTSP 0x00000200
450#define UCC_SLOW_GUMR_H_CDS 0x00000100
451#define UCC_SLOW_GUMR_H_CTSS 0x00000080
452#define UCC_SLOW_GUMR_H_TFL 0x00000040
453#define UCC_SLOW_GUMR_H_RFW 0x00000020
454#define UCC_SLOW_GUMR_H_TXSY 0x00000010
455#define UCC_SLOW_GUMR_H_4SYNC 0x00000004
456#define UCC_SLOW_GUMR_H_8SYNC 0x00000008
457#define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
458#define UCC_SLOW_GUMR_H_RTSM 0x00000002
459#define UCC_SLOW_GUMR_H_RSYN 0x00000001
460
461#define UCC_SLOW_GUMR_L_TCI 0x10000000
462#define UCC_SLOW_GUMR_L_RINV 0x02000000
463#define UCC_SLOW_GUMR_L_TINV 0x01000000
464#define UCC_SLOW_GUMR_L_TEND 0x00040000
465#define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000
466#define UCC_SLOW_GUMR_L_TDCR_32 0x00030000
467#define UCC_SLOW_GUMR_L_TDCR_16 0x00020000
468#define UCC_SLOW_GUMR_L_TDCR_8 0x00010000
469#define UCC_SLOW_GUMR_L_TDCR_1 0x00000000
470#define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000
471#define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000
472#define UCC_SLOW_GUMR_L_RDCR_16 0x00008000
473#define UCC_SLOW_GUMR_L_RDCR_8 0x00004000
474#define UCC_SLOW_GUMR_L_RDCR_1 0x00000000
475#define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800
476#define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000
477#define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100
478#define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000
479#define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0
480#define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0
481#define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080
482#define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040
483#define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000
484#define UCC_SLOW_GUMR_L_ENR 0x00000020
485#define UCC_SLOW_GUMR_L_ENT 0x00000010
486#define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F
487#define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008
488#define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006
489#define UCC_SLOW_GUMR_L_MODE_UART 0x00000004
490#define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
491
492/* General UCC FAST Mode Register */
493#define UCC_FAST_GUMR_TCI 0x20000000
494#define UCC_FAST_GUMR_TRX 0x10000000
495#define UCC_FAST_GUMR_TTX 0x08000000
496#define UCC_FAST_GUMR_CDP 0x04000000
497#define UCC_FAST_GUMR_CTSP 0x02000000
498#define UCC_FAST_GUMR_CDS 0x01000000
499#define UCC_FAST_GUMR_CTSS 0x00800000
500#define UCC_FAST_GUMR_TXSY 0x00020000
501#define UCC_FAST_GUMR_RSYN 0x00010000
502#define UCC_FAST_GUMR_RTSM 0x00002000
503#define UCC_FAST_GUMR_REVD 0x00000400
504#define UCC_FAST_GUMR_ENR 0x00000020
505#define UCC_FAST_GUMR_ENT 0x00000010
506
507/* UART Slow UCC Event Register (UCCE) */
508#define UCC_UART_UCCE_AB 0x0200
509#define UCC_UART_UCCE_IDLE 0x0100
510#define UCC_UART_UCCE_GRA 0x0080
511#define UCC_UART_UCCE_BRKE 0x0040
512#define UCC_UART_UCCE_BRKS 0x0020
513#define UCC_UART_UCCE_CCR 0x0008
514#define UCC_UART_UCCE_BSY 0x0004
515#define UCC_UART_UCCE_TX 0x0002
516#define UCC_UART_UCCE_RX 0x0001
517
518/* HDLC Slow UCC Event Register (UCCE) */
519#define UCC_HDLC_UCCE_GLR 0x1000
520#define UCC_HDLC_UCCE_GLT 0x0800
521#define UCC_HDLC_UCCE_IDLE 0x0100
522#define UCC_HDLC_UCCE_BRKE 0x0040
523#define UCC_HDLC_UCCE_BRKS 0x0020
524#define UCC_HDLC_UCCE_TXE 0x0010
525#define UCC_HDLC_UCCE_RXF 0x0008
526#define UCC_HDLC_UCCE_BSY 0x0004
527#define UCC_HDLC_UCCE_TXB 0x0002
528#define UCC_HDLC_UCCE_RXB 0x0001
529
530/* BISYNC Slow UCC Event Register (UCCE) */
531#define UCC_BISYNC_UCCE_GRA 0x0080
532#define UCC_BISYNC_UCCE_TXE 0x0010
533#define UCC_BISYNC_UCCE_RCH 0x0008
534#define UCC_BISYNC_UCCE_BSY 0x0004
535#define UCC_BISYNC_UCCE_TXB 0x0002
536#define UCC_BISYNC_UCCE_RXB 0x0001
537
538/* Gigabit Ethernet Fast UCC Event Register (UCCE) */
539#define UCC_GETH_UCCE_MPD 0x80000000
540#define UCC_GETH_UCCE_SCAR 0x40000000
541#define UCC_GETH_UCCE_GRA 0x20000000
542#define UCC_GETH_UCCE_CBPR 0x10000000
543#define UCC_GETH_UCCE_BSY 0x08000000
544#define UCC_GETH_UCCE_RXC 0x04000000
545#define UCC_GETH_UCCE_TXC 0x02000000
546#define UCC_GETH_UCCE_TXE 0x01000000
547#define UCC_GETH_UCCE_TXB7 0x00800000
548#define UCC_GETH_UCCE_TXB6 0x00400000
549#define UCC_GETH_UCCE_TXB5 0x00200000
550#define UCC_GETH_UCCE_TXB4 0x00100000
551#define UCC_GETH_UCCE_TXB3 0x00080000
552#define UCC_GETH_UCCE_TXB2 0x00040000
553#define UCC_GETH_UCCE_TXB1 0x00020000
554#define UCC_GETH_UCCE_TXB0 0x00010000
555#define UCC_GETH_UCCE_RXB7 0x00008000
556#define UCC_GETH_UCCE_RXB6 0x00004000
557#define UCC_GETH_UCCE_RXB5 0x00002000
558#define UCC_GETH_UCCE_RXB4 0x00001000
559#define UCC_GETH_UCCE_RXB3 0x00000800
560#define UCC_GETH_UCCE_RXB2 0x00000400
561#define UCC_GETH_UCCE_RXB1 0x00000200
562#define UCC_GETH_UCCE_RXB0 0x00000100
563#define UCC_GETH_UCCE_RXF7 0x00000080
564#define UCC_GETH_UCCE_RXF6 0x00000040
565#define UCC_GETH_UCCE_RXF5 0x00000020
566#define UCC_GETH_UCCE_RXF4 0x00000010
567#define UCC_GETH_UCCE_RXF3 0x00000008
568#define UCC_GETH_UCCE_RXF2 0x00000004
569#define UCC_GETH_UCCE_RXF1 0x00000002
570#define UCC_GETH_UCCE_RXF0 0x00000001
571
572/* UPSMR, when used as a UART */
573#define UCC_UART_UPSMR_FLC 0x8000
574#define UCC_UART_UPSMR_SL 0x4000
575#define UCC_UART_UPSMR_CL_MASK 0x3000
576#define UCC_UART_UPSMR_CL_8 0x3000
577#define UCC_UART_UPSMR_CL_7 0x2000
578#define UCC_UART_UPSMR_CL_6 0x1000
579#define UCC_UART_UPSMR_CL_5 0x0000
580#define UCC_UART_UPSMR_UM_MASK 0x0c00
581#define UCC_UART_UPSMR_UM_NORMAL 0x0000
582#define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400
583#define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00
584#define UCC_UART_UPSMR_FRZ 0x0200
585#define UCC_UART_UPSMR_RZS 0x0100
586#define UCC_UART_UPSMR_SYN 0x0080
587#define UCC_UART_UPSMR_DRT 0x0040
588#define UCC_UART_UPSMR_PEN 0x0010
589#define UCC_UART_UPSMR_RPM_MASK 0x000c
590#define UCC_UART_UPSMR_RPM_ODD 0x0000
591#define UCC_UART_UPSMR_RPM_LOW 0x0004
592#define UCC_UART_UPSMR_RPM_EVEN 0x0008
593#define UCC_UART_UPSMR_RPM_HIGH 0x000C
594#define UCC_UART_UPSMR_TPM_MASK 0x0003
595#define UCC_UART_UPSMR_TPM_ODD 0x0000
596#define UCC_UART_UPSMR_TPM_LOW 0x0001
597#define UCC_UART_UPSMR_TPM_EVEN 0x0002
598#define UCC_UART_UPSMR_TPM_HIGH 0x0003
599
600/* UCC Transmit On Demand Register (UTODR) */
601#define UCC_SLOW_TOD 0x8000
602#define UCC_FAST_TOD 0x8000
603
604/* UCC Bus Mode Register masks */
605/* Not to be confused with the Bundle Mode Register */
606#define UCC_BMR_GBL 0x20
607#define UCC_BMR_BO_BE 0x10
608#define UCC_BMR_CETM 0x04
609#define UCC_BMR_DTB 0x02
610#define UCC_BMR_BDB 0x01
611
612/* Function code masks */
613#define FC_GBL 0x20
614#define FC_DTB_LCL 0x02
615#define UCC_FAST_FUNCTION_CODE_GBL 0x20
616#define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
617#define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
618
619#endif /* __KERNEL__ */
620#endif /* _ASM_POWERPC_QE_H */