Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34#include <linux/init.h>
35#include <linux/interrupt.h>
36#include <linux/dma-mapping.h>
37
38#include <linux/mlx4/cmd.h>
39
40#include "mlx4.h"
41#include "fw.h"
42
43enum {
44 MLX4_NUM_ASYNC_EQE = 0x100,
45 MLX4_NUM_SPARE_EQE = 0x80,
46 MLX4_EQ_ENTRY_SIZE = 0x20
47};
48
49/*
50 * Must be packed because start is 64 bits but only aligned to 32 bits.
51 */
52struct mlx4_eq_context {
53 __be32 flags;
54 u16 reserved1[3];
55 __be16 page_offset;
56 u8 log_eq_size;
57 u8 reserved2[4];
58 u8 eq_period;
59 u8 reserved3;
60 u8 eq_max_count;
61 u8 reserved4[3];
62 u8 intr;
63 u8 log_page_size;
64 u8 reserved5[2];
65 u8 mtt_base_addr_h;
66 __be32 mtt_base_addr_l;
67 u32 reserved6[2];
68 __be32 consumer_index;
69 __be32 producer_index;
70 u32 reserved7[4];
71};
72
73#define MLX4_EQ_STATUS_OK ( 0 << 28)
74#define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28)
75#define MLX4_EQ_OWNER_SW ( 0 << 24)
76#define MLX4_EQ_OWNER_HW ( 1 << 24)
77#define MLX4_EQ_FLAG_EC ( 1 << 18)
78#define MLX4_EQ_FLAG_OI ( 1 << 17)
79#define MLX4_EQ_STATE_ARMED ( 9 << 8)
80#define MLX4_EQ_STATE_FIRED (10 << 8)
81#define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8)
82
83#define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \
84 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \
85 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \
86 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \
87 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \
88 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \
89 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \
90 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
91 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \
92 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \
93 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \
94 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \
95 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
96 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
97 (1ull << MLX4_EVENT_TYPE_CMD))
98
99struct mlx4_eqe {
100 u8 reserved1;
101 u8 type;
102 u8 reserved2;
103 u8 subtype;
104 union {
105 u32 raw[6];
106 struct {
107 __be32 cqn;
108 } __attribute__((packed)) comp;
109 struct {
110 u16 reserved1;
111 __be16 token;
112 u32 reserved2;
113 u8 reserved3[3];
114 u8 status;
115 __be64 out_param;
116 } __attribute__((packed)) cmd;
117 struct {
118 __be32 qpn;
119 } __attribute__((packed)) qp;
120 struct {
121 __be32 srqn;
122 } __attribute__((packed)) srq;
123 struct {
124 __be32 cqn;
125 u32 reserved1;
126 u8 reserved2[3];
127 u8 syndrome;
128 } __attribute__((packed)) cq_err;
129 struct {
130 u32 reserved1[2];
131 __be32 port;
132 } __attribute__((packed)) port_change;
133 } event;
134 u8 reserved3[3];
135 u8 owner;
136} __attribute__((packed));
137
138static void eq_set_ci(struct mlx4_eq *eq, int req_not)
139{
140 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
141 req_not << 31),
142 eq->doorbell);
143 /* We still want ordering, just not swabbing, so add a barrier */
144 mb();
145}
146
147static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry)
148{
149 unsigned long off = (entry & (eq->nent - 1)) * MLX4_EQ_ENTRY_SIZE;
150 return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE;
151}
152
153static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq)
154{
155 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index);
156 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
157}
158
159static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
160{
161 struct mlx4_eqe *eqe;
162 int cqn;
163 int eqes_found = 0;
164 int set_ci = 0;
165
166 while ((eqe = next_eqe_sw(eq))) {
167 /*
168 * Make sure we read EQ entry contents after we've
169 * checked the ownership bit.
170 */
171 rmb();
172
173 switch (eqe->type) {
174 case MLX4_EVENT_TYPE_COMP:
175 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
176 mlx4_cq_completion(dev, cqn);
177 break;
178
179 case MLX4_EVENT_TYPE_PATH_MIG:
180 case MLX4_EVENT_TYPE_COMM_EST:
181 case MLX4_EVENT_TYPE_SQ_DRAINED:
182 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
183 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
184 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
185 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
186 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
187 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,
188 eqe->type);
189 break;
190
191 case MLX4_EVENT_TYPE_SRQ_LIMIT:
192 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
193 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 0xffffff,
194 eqe->type);
195 break;
196
197 case MLX4_EVENT_TYPE_CMD:
198 mlx4_cmd_event(dev,
199 be16_to_cpu(eqe->event.cmd.token),
200 eqe->event.cmd.status,
201 be64_to_cpu(eqe->event.cmd.out_param));
202 break;
203
204 case MLX4_EVENT_TYPE_PORT_CHANGE:
205 mlx4_dispatch_event(dev,
206 eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_ACTIVE ?
207 MLX4_DEV_EVENT_PORT_UP :
208 MLX4_DEV_EVENT_PORT_DOWN,
209 be32_to_cpu(eqe->event.port_change.port) >> 28);
210 break;
211
212 case MLX4_EVENT_TYPE_CQ_ERROR:
213 mlx4_warn(dev, "CQ %s on CQN %06x\n",
214 eqe->event.cq_err.syndrome == 1 ?
215 "overrun" : "access violation",
216 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
217 mlx4_cq_event(dev, be32_to_cpu(eqe->event.cq_err.cqn),
218 eqe->type);
219 break;
220
221 case MLX4_EVENT_TYPE_EQ_OVERFLOW:
222 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
223 break;
224
225 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
226 case MLX4_EVENT_TYPE_ECC_DETECT:
227 default:
228 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u\n",
229 eqe->type, eqe->subtype, eq->eqn, eq->cons_index);
230 break;
231 };
232
233 ++eq->cons_index;
234 eqes_found = 1;
235 ++set_ci;
236
237 /*
238 * The HCA will think the queue has overflowed if we
239 * don't tell it we've been processing events. We
240 * create our EQs with MLX4_NUM_SPARE_EQE extra
241 * entries, so we must update our consumer index at
242 * least that often.
243 */
244 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
245 /*
246 * Conditional on hca_type is OK here because
247 * this is a rare case, not the fast path.
248 */
249 eq_set_ci(eq, 0);
250 set_ci = 0;
251 }
252 }
253
254 eq_set_ci(eq, 1);
255
256 return eqes_found;
257}
258
259static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
260{
261 struct mlx4_dev *dev = dev_ptr;
262 struct mlx4_priv *priv = mlx4_priv(dev);
263 int work = 0;
264 int i;
265
266 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
267
268 for (i = 0; i < MLX4_NUM_EQ; ++i)
269 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
270
271 return IRQ_RETVAL(work);
272}
273
274static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
275{
276 struct mlx4_eq *eq = eq_ptr;
277 struct mlx4_dev *dev = eq->dev;
278
279 mlx4_eq_int(dev, eq);
280
281 /* MSI-X vectors always belong to us */
282 return IRQ_HANDLED;
283}
284
285static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
286 int eq_num)
287{
288 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
289 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B);
290}
291
292static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
293 int eq_num)
294{
295 return mlx4_cmd(dev, mailbox->dma, eq_num, 0, MLX4_CMD_SW2HW_EQ,
296 MLX4_CMD_TIME_CLASS_A);
297}
298
299static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
300 int eq_num)
301{
302 return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num, 0, MLX4_CMD_HW2SW_EQ,
303 MLX4_CMD_TIME_CLASS_A);
304}
305
306static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
307{
308 struct mlx4_priv *priv = mlx4_priv(dev);
309 int index;
310
311 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
312
313 if (!priv->eq_table.uar_map[index]) {
314 priv->eq_table.uar_map[index] =
315 ioremap(pci_resource_start(dev->pdev, 2) +
316 ((eq->eqn / 4) << PAGE_SHIFT),
317 PAGE_SIZE);
318 if (!priv->eq_table.uar_map[index]) {
319 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
320 eq->eqn);
321 return NULL;
322 }
323 }
324
325 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
326}
327
328static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
329 u8 intr, struct mlx4_eq *eq)
330{
331 struct mlx4_priv *priv = mlx4_priv(dev);
332 struct mlx4_cmd_mailbox *mailbox;
333 struct mlx4_eq_context *eq_context;
334 int npages;
335 u64 *dma_list = NULL;
336 dma_addr_t t;
337 u64 mtt_addr;
338 int err = -ENOMEM;
339 int i;
340
341 eq->dev = dev;
342 eq->nent = roundup_pow_of_two(max(nent, 2));
343 npages = PAGE_ALIGN(eq->nent * MLX4_EQ_ENTRY_SIZE) / PAGE_SIZE;
344
345 eq->page_list = kmalloc(npages * sizeof *eq->page_list,
346 GFP_KERNEL);
347 if (!eq->page_list)
348 goto err_out;
349
350 for (i = 0; i < npages; ++i)
351 eq->page_list[i].buf = NULL;
352
353 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
354 if (!dma_list)
355 goto err_out_free;
356
357 mailbox = mlx4_alloc_cmd_mailbox(dev);
358 if (IS_ERR(mailbox))
359 goto err_out_free;
360 eq_context = mailbox->buf;
361
362 for (i = 0; i < npages; ++i) {
363 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
364 PAGE_SIZE, &t, GFP_KERNEL);
365 if (!eq->page_list[i].buf)
366 goto err_out_free_pages;
367
368 dma_list[i] = t;
369 eq->page_list[i].map = t;
370
371 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
372 }
373
374 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
375 if (eq->eqn == -1)
376 goto err_out_free_pages;
377
378 eq->doorbell = mlx4_get_eq_uar(dev, eq);
379 if (!eq->doorbell) {
380 err = -ENOMEM;
381 goto err_out_free_eq;
382 }
383
384 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
385 if (err)
386 goto err_out_free_eq;
387
388 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
389 if (err)
390 goto err_out_free_mtt;
391
392 memset(eq_context, 0, sizeof *eq_context);
393 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK |
394 MLX4_EQ_STATE_ARMED);
395 eq_context->log_eq_size = ilog2(eq->nent);
396 eq_context->intr = intr;
397 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
398
399 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
400 eq_context->mtt_base_addr_h = mtt_addr >> 32;
401 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
402
403 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
404 if (err) {
405 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
406 goto err_out_free_mtt;
407 }
408
409 kfree(dma_list);
410 mlx4_free_cmd_mailbox(dev, mailbox);
411
412 eq->cons_index = 0;
413
414 return err;
415
416err_out_free_mtt:
417 mlx4_mtt_cleanup(dev, &eq->mtt);
418
419err_out_free_eq:
420 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
421
422err_out_free_pages:
423 for (i = 0; i < npages; ++i)
424 if (eq->page_list[i].buf)
425 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
426 eq->page_list[i].buf,
427 eq->page_list[i].map);
428
429 mlx4_free_cmd_mailbox(dev, mailbox);
430
431err_out_free:
432 kfree(eq->page_list);
433 kfree(dma_list);
434
435err_out:
436 return err;
437}
438
439static void mlx4_free_eq(struct mlx4_dev *dev,
440 struct mlx4_eq *eq)
441{
442 struct mlx4_priv *priv = mlx4_priv(dev);
443 struct mlx4_cmd_mailbox *mailbox;
444 int err;
445 int npages = PAGE_ALIGN(MLX4_EQ_ENTRY_SIZE * eq->nent) / PAGE_SIZE;
446 int i;
447
448 mailbox = mlx4_alloc_cmd_mailbox(dev);
449 if (IS_ERR(mailbox))
450 return;
451
452 err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn);
453 if (err)
454 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
455
456 if (0) {
457 mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
458 for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) {
459 if (i % 4 == 0)
460 printk("[%02x] ", i * 4);
461 printk(" %08x", be32_to_cpup(mailbox->buf + i * 4));
462 if ((i + 1) % 4 == 0)
463 printk("\n");
464 }
465 }
466
467 mlx4_mtt_cleanup(dev, &eq->mtt);
468 for (i = 0; i < npages; ++i)
469 pci_free_consistent(dev->pdev, PAGE_SIZE,
470 eq->page_list[i].buf,
471 eq->page_list[i].map);
472
473 kfree(eq->page_list);
474 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
475 mlx4_free_cmd_mailbox(dev, mailbox);
476}
477
478static void mlx4_free_irqs(struct mlx4_dev *dev)
479{
480 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
481 int i;
482
483 if (eq_table->have_irq)
484 free_irq(dev->pdev->irq, dev);
485 for (i = 0; i < MLX4_NUM_EQ; ++i)
486 if (eq_table->eq[i].have_irq)
487 free_irq(eq_table->eq[i].irq, eq_table->eq + i);
488}
489
490static int mlx4_map_clr_int(struct mlx4_dev *dev)
491{
492 struct mlx4_priv *priv = mlx4_priv(dev);
493
494 priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) +
495 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
496 if (!priv->clr_base) {
497 mlx4_err(dev, "Couldn't map interrupt clear register, aborting.\n");
498 return -ENOMEM;
499 }
500
501 return 0;
502}
503
504static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
505{
506 struct mlx4_priv *priv = mlx4_priv(dev);
507
508 iounmap(priv->clr_base);
509}
510
511int mlx4_map_eq_icm(struct mlx4_dev *dev, u64 icm_virt)
512{
513 struct mlx4_priv *priv = mlx4_priv(dev);
514 int ret;
515
516 /*
517 * We assume that mapping one page is enough for the whole EQ
518 * context table. This is fine with all current HCAs, because
519 * we only use 32 EQs and each EQ uses 64 bytes of context
520 * memory, or 1 KB total.
521 */
522 priv->eq_table.icm_virt = icm_virt;
523 priv->eq_table.icm_page = alloc_page(GFP_HIGHUSER);
524 if (!priv->eq_table.icm_page)
525 return -ENOMEM;
526 priv->eq_table.icm_dma = pci_map_page(dev->pdev, priv->eq_table.icm_page, 0,
527 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
528 if (pci_dma_mapping_error(priv->eq_table.icm_dma)) {
529 __free_page(priv->eq_table.icm_page);
530 return -ENOMEM;
531 }
532
533 ret = mlx4_MAP_ICM_page(dev, priv->eq_table.icm_dma, icm_virt);
534 if (ret) {
535 pci_unmap_page(dev->pdev, priv->eq_table.icm_dma, PAGE_SIZE,
536 PCI_DMA_BIDIRECTIONAL);
537 __free_page(priv->eq_table.icm_page);
538 }
539
540 return ret;
541}
542
543void mlx4_unmap_eq_icm(struct mlx4_dev *dev)
544{
545 struct mlx4_priv *priv = mlx4_priv(dev);
546
547 mlx4_UNMAP_ICM(dev, priv->eq_table.icm_virt, 1);
548 pci_unmap_page(dev->pdev, priv->eq_table.icm_dma, PAGE_SIZE,
549 PCI_DMA_BIDIRECTIONAL);
550 __free_page(priv->eq_table.icm_page);
551}
552
553int mlx4_init_eq_table(struct mlx4_dev *dev)
554{
555 struct mlx4_priv *priv = mlx4_priv(dev);
556 int err;
557 int i;
558
559 err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs,
560 dev->caps.num_eqs - 1, dev->caps.reserved_eqs);
561 if (err)
562 return err;
563
564 for (i = 0; i < ARRAY_SIZE(priv->eq_table.uar_map); ++i)
565 priv->eq_table.uar_map[i] = NULL;
566
567 err = mlx4_map_clr_int(dev);
568 if (err)
569 goto err_out_free;
570
571 priv->eq_table.clr_mask =
572 swab32(1 << (priv->eq_table.inta_pin & 31));
573 priv->eq_table.clr_int = priv->clr_base +
574 (priv->eq_table.inta_pin < 32 ? 4 : 0);
575
576 err = mlx4_create_eq(dev, dev->caps.num_cqs + MLX4_NUM_SPARE_EQE,
577 (dev->flags & MLX4_FLAG_MSI_X) ? MLX4_EQ_COMP : 0,
578 &priv->eq_table.eq[MLX4_EQ_COMP]);
579 if (err)
580 goto err_out_unmap;
581
582 err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
583 (dev->flags & MLX4_FLAG_MSI_X) ? MLX4_EQ_ASYNC : 0,
584 &priv->eq_table.eq[MLX4_EQ_ASYNC]);
585 if (err)
586 goto err_out_comp;
587
588 if (dev->flags & MLX4_FLAG_MSI_X) {
589 static const char *eq_name[] = {
590 [MLX4_EQ_COMP] = DRV_NAME " (comp)",
591 [MLX4_EQ_ASYNC] = DRV_NAME " (async)"
592 };
593
594 for (i = 0; i < MLX4_NUM_EQ; ++i) {
595 err = request_irq(priv->eq_table.eq[i].irq,
596 mlx4_msi_x_interrupt,
597 0, eq_name[i], priv->eq_table.eq + i);
598 if (err)
599 goto err_out_async;
600
601 priv->eq_table.eq[i].have_irq = 1;
602 }
603
604 } else {
605 err = request_irq(dev->pdev->irq, mlx4_interrupt,
606 IRQF_SHARED, DRV_NAME, dev);
607 if (err)
608 goto err_out_async;
609
610 priv->eq_table.have_irq = 1;
611 }
612
613 err = mlx4_MAP_EQ(dev, MLX4_ASYNC_EVENT_MASK, 0,
614 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn);
615 if (err)
616 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
617 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn, err);
618
619 for (i = 0; i < MLX4_NUM_EQ; ++i)
620 eq_set_ci(&priv->eq_table.eq[i], 1);
621
622 return 0;
623
624err_out_async:
625 mlx4_free_eq(dev, &priv->eq_table.eq[MLX4_EQ_ASYNC]);
626
627err_out_comp:
628 mlx4_free_eq(dev, &priv->eq_table.eq[MLX4_EQ_COMP]);
629
630err_out_unmap:
631 mlx4_unmap_clr_int(dev);
632 mlx4_free_irqs(dev);
633
634err_out_free:
635 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
636 return err;
637}
638
639void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
640{
641 struct mlx4_priv *priv = mlx4_priv(dev);
642 int i;
643
644 mlx4_MAP_EQ(dev, MLX4_ASYNC_EVENT_MASK, 1,
645 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn);
646
647 mlx4_free_irqs(dev);
648
649 for (i = 0; i < MLX4_NUM_EQ; ++i)
650 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
651
652 mlx4_unmap_clr_int(dev);
653
654 for (i = 0; i < ARRAY_SIZE(priv->eq_table.uar_map); ++i)
655 if (priv->eq_table.uar_map[i])
656 iounmap(priv->eq_table.uar_map[i]);
657
658 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
659}