tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * linux/drivers/serial/cpm_uart.c
3 *
4 * Driver for CPM (SCC/SMC) serial ports; CPM1 definitions
5 *
6 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
7 * Pantelis Antoniou (panto@intracom.gr) (CPM1)
8 *
9 * Copyright (C) 2004 Freescale Semiconductor, Inc.
10 * (C) 2004 Intracom, S.A.
11 * (C) 2006 MontaVista Software, Inc.
12 * Vitaly Bordug <vbordug@ru.mvista.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 */
29
30#include <linux/module.h>
31#include <linux/tty.h>
32#include <linux/ioport.h>
33#include <linux/init.h>
34#include <linux/serial.h>
35#include <linux/console.h>
36#include <linux/sysrq.h>
37#include <linux/device.h>
38#include <linux/bootmem.h>
39#include <linux/dma-mapping.h>
40
41#include <asm/io.h>
42#include <asm/irq.h>
43#include <asm/fs_pd.h>
44
45#include <linux/serial_core.h>
46#include <linux/kernel.h>
47
48#include <linux/of.h>
49
50#include "cpm_uart.h"
51
52/**************************************************************/
53
54#ifdef CONFIG_PPC_CPM_NEW_BINDING
55void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
56{
57 cpm_command(port->command, cmd);
58}
59
60void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port,
61 struct device_node *np)
62{
63 return of_iomap(np, 1);
64}
65
66void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram)
67{
68 iounmap(pram);
69}
70
71#else
72void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
73{
74 ushort val;
75 int line = port - cpm_uart_ports;
76 volatile cpm8xx_t *cp = cpmp;
77
78 switch (line) {
79 case UART_SMC1:
80 val = mk_cr_cmd(CPM_CR_CH_SMC1, cmd) | CPM_CR_FLG;
81 break;
82 case UART_SMC2:
83 val = mk_cr_cmd(CPM_CR_CH_SMC2, cmd) | CPM_CR_FLG;
84 break;
85 case UART_SCC1:
86 val = mk_cr_cmd(CPM_CR_CH_SCC1, cmd) | CPM_CR_FLG;
87 break;
88 case UART_SCC2:
89 val = mk_cr_cmd(CPM_CR_CH_SCC2, cmd) | CPM_CR_FLG;
90 break;
91 case UART_SCC3:
92 val = mk_cr_cmd(CPM_CR_CH_SCC3, cmd) | CPM_CR_FLG;
93 break;
94 case UART_SCC4:
95 val = mk_cr_cmd(CPM_CR_CH_SCC4, cmd) | CPM_CR_FLG;
96 break;
97 default:
98 return;
99
100 }
101 cp->cp_cpcr = val;
102 while (cp->cp_cpcr & CPM_CR_FLG) ;
103}
104
105void smc1_lineif(struct uart_cpm_port *pinfo)
106{
107 pinfo->brg = 1;
108}
109
110void smc2_lineif(struct uart_cpm_port *pinfo)
111{
112 pinfo->brg = 2;
113}
114
115void scc1_lineif(struct uart_cpm_port *pinfo)
116{
117 /* XXX SCC1: insert port configuration here */
118 pinfo->brg = 1;
119}
120
121void scc2_lineif(struct uart_cpm_port *pinfo)
122{
123 /* XXX SCC2: insert port configuration here */
124 pinfo->brg = 2;
125}
126
127void scc3_lineif(struct uart_cpm_port *pinfo)
128{
129 /* XXX SCC3: insert port configuration here */
130 pinfo->brg = 3;
131}
132
133void scc4_lineif(struct uart_cpm_port *pinfo)
134{
135 /* XXX SCC4: insert port configuration here */
136 pinfo->brg = 4;
137}
138#endif
139
140/*
141 * Allocate DP-Ram and memory buffers. We need to allocate a transmit and
142 * receive buffer descriptors from dual port ram, and a character
143 * buffer area from host mem. If we are allocating for the console we need
144 * to do it from bootmem
145 */
146int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
147{
148 int dpmemsz, memsz;
149 u8 *dp_mem;
150 unsigned long dp_offset;
151 u8 *mem_addr;
152 dma_addr_t dma_addr = 0;
153
154 pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
155
156 dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
157 dp_offset = cpm_dpalloc(dpmemsz, 8);
158 if (IS_ERR_VALUE(dp_offset)) {
159 printk(KERN_ERR
160 "cpm_uart_cpm1.c: could not allocate buffer descriptors\n");
161 return -ENOMEM;
162 }
163 dp_mem = cpm_dpram_addr(dp_offset);
164
165 memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
166 L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
167 if (is_con) {
168 /* was hostalloc but changed cause it blows away the */
169 /* large tlb mapping when pinning the kernel area */
170 mem_addr = (u8 *) cpm_dpram_addr(cpm_dpalloc(memsz, 8));
171 dma_addr = (u32)cpm_dpram_phys(mem_addr);
172 } else
173 mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
174 GFP_KERNEL);
175
176 if (mem_addr == NULL) {
177 cpm_dpfree(dp_offset);
178 printk(KERN_ERR
179 "cpm_uart_cpm1.c: could not allocate coherent memory\n");
180 return -ENOMEM;
181 }
182
183 pinfo->dp_addr = dp_offset;
184 pinfo->mem_addr = mem_addr; /* virtual address*/
185 pinfo->dma_addr = dma_addr; /* physical address*/
186 pinfo->mem_size = memsz;
187
188 pinfo->rx_buf = mem_addr;
189 pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
190 * pinfo->rx_fifosize);
191
192 pinfo->rx_bd_base = (cbd_t __iomem __force *)dp_mem;
193 pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
194
195 return 0;
196}
197
198void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
199{
200 dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
201 pinfo->rx_fifosize) +
202 L1_CACHE_ALIGN(pinfo->tx_nrfifos *
203 pinfo->tx_fifosize), pinfo->mem_addr,
204 pinfo->dma_addr);
205
206 cpm_dpfree(pinfo->dp_addr);
207}
208
209#ifndef CONFIG_PPC_CPM_NEW_BINDING
210/* Setup any dynamic params in the uart desc */
211int cpm_uart_init_portdesc(void)
212{
213 pr_debug("CPM uart[-]:init portdesc\n");
214
215 cpm_uart_nr = 0;
216#ifdef CONFIG_SERIAL_CPM_SMC1
217 cpm_uart_ports[UART_SMC1].smcp = &cpmp->cp_smc[0];
218/*
219 * Is SMC1 being relocated?
220 */
221# ifdef CONFIG_I2C_SPI_SMC1_UCODE_PATCH
222 cpm_uart_ports[UART_SMC1].smcup =
223 (smc_uart_t *) & cpmp->cp_dparam[0x3C0];
224# else
225 cpm_uart_ports[UART_SMC1].smcup =
226 (smc_uart_t *) & cpmp->cp_dparam[PROFF_SMC1];
227# endif
228 cpm_uart_ports[UART_SMC1].port.mapbase =
229 (unsigned long)&cpmp->cp_smc[0];
230 cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
231 cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
232 cpm_uart_ports[UART_SMC1].port.uartclk = uart_clock();
233 cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1;
234#endif
235
236#ifdef CONFIG_SERIAL_CPM_SMC2
237 cpm_uart_ports[UART_SMC2].smcp = &cpmp->cp_smc[1];
238 cpm_uart_ports[UART_SMC2].smcup =
239 (smc_uart_t *) & cpmp->cp_dparam[PROFF_SMC2];
240 cpm_uart_ports[UART_SMC2].port.mapbase =
241 (unsigned long)&cpmp->cp_smc[1];
242 cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
243 cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
244 cpm_uart_ports[UART_SMC2].port.uartclk = uart_clock();
245 cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2;
246#endif
247
248#ifdef CONFIG_SERIAL_CPM_SCC1
249 cpm_uart_ports[UART_SCC1].sccp = &cpmp->cp_scc[0];
250 cpm_uart_ports[UART_SCC1].sccup =
251 (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC1];
252 cpm_uart_ports[UART_SCC1].port.mapbase =
253 (unsigned long)&cpmp->cp_scc[0];
254 cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
255 ~(UART_SCCM_TX | UART_SCCM_RX);
256 cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
257 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
258 cpm_uart_ports[UART_SCC1].port.uartclk = uart_clock();
259 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1;
260#endif
261
262#ifdef CONFIG_SERIAL_CPM_SCC2
263 cpm_uart_ports[UART_SCC2].sccp = &cpmp->cp_scc[1];
264 cpm_uart_ports[UART_SCC2].sccup =
265 (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC2];
266 cpm_uart_ports[UART_SCC2].port.mapbase =
267 (unsigned long)&cpmp->cp_scc[1];
268 cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
269 ~(UART_SCCM_TX | UART_SCCM_RX);
270 cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
271 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
272 cpm_uart_ports[UART_SCC2].port.uartclk = uart_clock();
273 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2;
274#endif
275
276#ifdef CONFIG_SERIAL_CPM_SCC3
277 cpm_uart_ports[UART_SCC3].sccp = &cpmp->cp_scc[2];
278 cpm_uart_ports[UART_SCC3].sccup =
279 (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC3];
280 cpm_uart_ports[UART_SCC3].port.mapbase =
281 (unsigned long)&cpmp->cp_scc[2];
282 cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
283 ~(UART_SCCM_TX | UART_SCCM_RX);
284 cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
285 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
286 cpm_uart_ports[UART_SCC3].port.uartclk = uart_clock();
287 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3;
288#endif
289
290#ifdef CONFIG_SERIAL_CPM_SCC4
291 cpm_uart_ports[UART_SCC4].sccp = &cpmp->cp_scc[3];
292 cpm_uart_ports[UART_SCC4].sccup =
293 (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC4];
294 cpm_uart_ports[UART_SCC4].port.mapbase =
295 (unsigned long)&cpmp->cp_scc[3];
296 cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
297 ~(UART_SCCM_TX | UART_SCCM_RX);
298 cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=
299 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
300 cpm_uart_ports[UART_SCC4].port.uartclk = uart_clock();
301 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4;
302#endif
303 return 0;
304}
305#endif