tjh.dev
Linux kernel mirror (for testing)
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1/*
2 * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
3 *
4 * Author: Shlomi Gridish <gridish@freescale.com>
5 *
6 * Description:
7 * Internal header file for UCC Gigabit Ethernet unit routines.
8 *
9 * Changelog:
10 * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
11 * - Rearrange code and style fixes
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18#ifndef __UCC_GETH_H__
19#define __UCC_GETH_H__
20
21#include <linux/kernel.h>
22#include <linux/list.h>
23#include <linux/fsl_devices.h>
24
25#include <asm/immap_qe.h>
26#include <asm/qe.h>
27
28#include <asm/ucc.h>
29#include <asm/ucc_fast.h>
30
31#include "ucc_geth_mii.h"
32
33#define DRV_DESC "QE UCC Gigabit Ethernet Controller"
34#define DRV_NAME "ucc_geth"
35#define DRV_VERSION "1.1"
36
37#define NUM_TX_QUEUES 8
38#define NUM_RX_QUEUES 8
39#define NUM_BDS_IN_PREFETCHED_BDS 4
40#define TX_IP_OFFSET_ENTRY_MAX 8
41#define NUM_OF_PADDRS 4
42#define ENET_INIT_PARAM_MAX_ENTRIES_RX 9
43#define ENET_INIT_PARAM_MAX_ENTRIES_TX 8
44
45struct ucc_geth {
46 struct ucc_fast uccf;
47 u8 res0[0x100 - sizeof(struct ucc_fast)];
48
49 u32 maccfg1; /* mac configuration reg. 1 */
50 u32 maccfg2; /* mac configuration reg. 2 */
51 u32 ipgifg; /* interframe gap reg. */
52 u32 hafdup; /* half-duplex reg. */
53 u8 res1[0x10];
54 u8 miimng[0x18]; /* MII management structure moved to _mii.h */
55 u32 ifctl; /* interface control reg */
56 u32 ifstat; /* interface statux reg */
57 u32 macstnaddr1; /* mac station address part 1 reg */
58 u32 macstnaddr2; /* mac station address part 2 reg */
59 u8 res2[0x8];
60 u32 uempr; /* UCC Ethernet Mac parameter reg */
61 u32 utbipar; /* UCC tbi address reg */
62 u16 uescr; /* UCC Ethernet statistics control reg */
63 u8 res3[0x180 - 0x15A];
64 u32 tx64; /* Total number of frames (including bad
65 frames) transmitted that were exactly of the
66 minimal length (64 for un tagged, 68 for
67 tagged, or with length exactly equal to the
68 parameter MINLength */
69 u32 tx127; /* Total number of frames (including bad
70 frames) transmitted that were between
71 MINLength (Including FCS length==4) and 127
72 octets */
73 u32 tx255; /* Total number of frames (including bad
74 frames) transmitted that were between 128
75 (Including FCS length==4) and 255 octets */
76 u32 rx64; /* Total number of frames received including
77 bad frames that were exactly of the mninimal
78 length (64 bytes) */
79 u32 rx127; /* Total number of frames (including bad
80 frames) received that were between MINLength
81 (Including FCS length==4) and 127 octets */
82 u32 rx255; /* Total number of frames (including bad
83 frames) received that were between 128
84 (Including FCS length==4) and 255 octets */
85 u32 txok; /* Total number of octets residing in frames
86 that where involved in succesfull
87 transmission */
88 u16 txcf; /* Total number of PAUSE control frames
89 transmitted by this MAC */
90 u8 res4[0x2];
91 u32 tmca; /* Total number of frames that were transmitted
92 succesfully with the group address bit set
93 that are not broadcast frames */
94 u32 tbca; /* Total number of frames transmitted
95 succesfully that had destination address
96 field equal to the broadcast address */
97 u32 rxfok; /* Total number of frames received OK */
98 u32 rxbok; /* Total number of octets received OK */
99 u32 rbyt; /* Total number of octets received including
100 octets in bad frames. Must be implemented in
101 HW because it includes octets in frames that
102 never even reach the UCC */
103 u32 rmca; /* Total number of frames that were received
104 succesfully with the group address bit set
105 that are not broadcast frames */
106 u32 rbca; /* Total number of frames received succesfully
107 that had destination address equal to the
108 broadcast address */
109 u32 scar; /* Statistics carry register */
110 u32 scam; /* Statistics caryy mask register */
111 u8 res5[0x200 - 0x1c4];
112} __attribute__ ((packed));
113
114/* UCC GETH TEMODR Register */
115#define TEMODER_TX_RMON_STATISTICS_ENABLE 0x0100 /* enable Tx statistics
116 */
117#define TEMODER_SCHEDULER_ENABLE 0x2000 /* enable scheduler */
118#define TEMODER_IP_CHECKSUM_GENERATE 0x0400 /* generate IPv4
119 checksums */
120#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200 /* enable performance
121 optimization
122 enhancement (mode1) */
123#define TEMODER_RMON_STATISTICS 0x0100 /* enable tx statistics
124 */
125#define TEMODER_NUM_OF_QUEUES_SHIFT (15-15) /* Number of queues <<
126 shift */
127
128/* UCC GETH TEMODR Register */
129#define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000 /* enable Rx
130 statistics */
131#define REMODER_RX_EXTENDED_FEATURES 0x80000000 /* enable
132 extended
133 features */
134#define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 ) /* vlan operation
135 tagged << shift */
136#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) /* vlan operation non
137 tagged << shift */
138#define REMODER_RX_QOS_MODE_SHIFT (31-15) /* rx QoS mode << shift
139 */
140#define REMODER_RMON_STATISTICS 0x00001000 /* enable rx
141 statistics */
142#define REMODER_RX_EXTENDED_FILTERING 0x00000800 /* extended
143 filtering
144 vs.
145 mpc82xx-like
146 filtering */
147#define REMODER_NUM_OF_QUEUES_SHIFT (31-23) /* Number of queues <<
148 shift */
149#define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008 /* enable
150 dynamic max
151 frame length
152 */
153#define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004 /* enable
154 dynamic min
155 frame length
156 */
157#define REMODER_IP_CHECKSUM_CHECK 0x00000002 /* check IPv4
158 checksums */
159#define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001 /* align ip
160 address to
161 4-byte
162 boundary */
163
164/* UCC GETH Event Register */
165#define UCCE_MPD 0x80000000 /* Magic packet
166 detection */
167#define UCCE_SCAR 0x40000000
168#define UCCE_GRA 0x20000000 /* Tx graceful
169 stop
170 complete */
171#define UCCE_CBPR 0x10000000
172#define UCCE_BSY 0x08000000
173#define UCCE_RXC 0x04000000
174#define UCCE_TXC 0x02000000
175#define UCCE_TXE 0x01000000
176#define UCCE_TXB7 0x00800000
177#define UCCE_TXB6 0x00400000
178#define UCCE_TXB5 0x00200000
179#define UCCE_TXB4 0x00100000
180#define UCCE_TXB3 0x00080000
181#define UCCE_TXB2 0x00040000
182#define UCCE_TXB1 0x00020000
183#define UCCE_TXB0 0x00010000
184#define UCCE_RXB7 0x00008000
185#define UCCE_RXB6 0x00004000
186#define UCCE_RXB5 0x00002000
187#define UCCE_RXB4 0x00001000
188#define UCCE_RXB3 0x00000800
189#define UCCE_RXB2 0x00000400
190#define UCCE_RXB1 0x00000200
191#define UCCE_RXB0 0x00000100
192#define UCCE_RXF7 0x00000080
193#define UCCE_RXF6 0x00000040
194#define UCCE_RXF5 0x00000020
195#define UCCE_RXF4 0x00000010
196#define UCCE_RXF3 0x00000008
197#define UCCE_RXF2 0x00000004
198#define UCCE_RXF1 0x00000002
199#define UCCE_RXF0 0x00000001
200
201#define UCCE_RXBF_SINGLE_MASK (UCCE_RXF0)
202#define UCCE_TXBF_SINGLE_MASK (UCCE_TXB0)
203
204#define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 |\
205 UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
206#define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 |\
207 UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
208#define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 |\
209 UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
210#define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY |\
211 UCCE_RXC | UCCE_TXC | UCCE_TXE)
212
213#define UCCE_RX_EVENTS (UCCE_RXF | UCCE_BSY)
214#define UCCE_TX_EVENTS (UCCE_TXB | UCCE_TXE)
215
216/* UCC GETH UPSMR (Protocol Specific Mode Register) */
217#define UPSMR_ECM 0x04000000 /* Enable CAM
218 Miss or
219 Enable
220 Filtering
221 Miss */
222#define UPSMR_HSE 0x02000000 /* Hardware
223 Statistics
224 Enable */
225#define UPSMR_PRO 0x00400000 /* Promiscuous*/
226#define UPSMR_CAP 0x00200000 /* CAM polarity
227 */
228#define UPSMR_RSH 0x00100000 /* Receive
229 Short Frames
230 */
231#define UPSMR_RPM 0x00080000 /* Reduced Pin
232 Mode
233 interfaces */
234#define UPSMR_R10M 0x00040000 /* RGMII/RMII
235 10 Mode */
236#define UPSMR_RLPB 0x00020000 /* RMII
237 Loopback
238 Mode */
239#define UPSMR_TBIM 0x00010000 /* Ten-bit
240 Interface
241 Mode */
242#define UPSMR_RMM 0x00001000 /* RMII/RGMII
243 Mode */
244#define UPSMR_CAM 0x00000400 /* CAM Address
245 Matching */
246#define UPSMR_BRO 0x00000200 /* Broadcast
247 Address */
248#define UPSMR_RES1 0x00002000 /* Reserved
249 feild - must
250 be 1 */
251
252/* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
253#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control
254 Rx */
255#define MACCFG1_FLOW_TX 0x00000010 /* Flow Control
256 Tx */
257#define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Rx Enable
258 synchronized
259 to Rx stream
260 */
261#define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */
262#define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Tx Enable
263 synchronized
264 to Tx stream
265 */
266#define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */
267
268/* UCC GETH MACCFG2 (MAC Configuration 2 Register) */
269#define MACCFG2_PREL_SHIFT (31 - 19) /* Preamble
270 Length <<
271 shift */
272#define MACCFG2_PREL_MASK 0x0000f000 /* Preamble
273 Length mask */
274#define MACCFG2_SRP 0x00000080 /* Soft Receive
275 Preamble */
276#define MACCFG2_STP 0x00000040 /* Soft
277 Transmit
278 Preamble */
279#define MACCFG2_RESERVED_1 0x00000020 /* Reserved -
280 must be set
281 to 1 */
282#define MACCFG2_LC 0x00000010 /* Length Check
283 */
284#define MACCFG2_MPE 0x00000008 /* Magic packet
285 detect */
286#define MACCFG2_FDX 0x00000001 /* Full Duplex */
287#define MACCFG2_FDX_MASK 0x00000001 /* Full Duplex
288 mask */
289#define MACCFG2_PAD_CRC 0x00000004
290#define MACCFG2_CRC_EN 0x00000002
291#define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000 /* Neither
292 Padding
293 short frames
294 nor CRC */
295#define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002 /* Append CRC
296 only */
297#define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004
298#define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100 /* nibble mode
299 (MII/RMII/RGMII
300 10/100bps) */
301#define MACCFG2_INTERFACE_MODE_BYTE 0x00000200 /* byte mode
302 (GMII/TBI/RTB/RGMII
303 1000bps ) */
304#define MACCFG2_INTERFACE_MODE_MASK 0x00000300 /* mask
305 covering all
306 relevant
307 bits */
308
309/* UCC GETH IPGIFG (Inter-frame Gap / Inter-Frame Gap Register) */
310#define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 - 7) /* Non
311 back-to-back
312 inter frame
313 gap part 1.
314 << shift */
315#define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15) /* Non
316 back-to-back
317 inter frame
318 gap part 2.
319 << shift */
320#define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT (31 - 23) /* Mimimum IFG
321 Enforcement
322 << shift */
323#define IPGIFG_BACK_TO_BACK_IFG_SHIFT (31 - 31) /* back-to-back
324 inter frame
325 gap << shift
326 */
327#define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX 127 /* Non back-to-back
328 inter frame gap part
329 1. max val */
330#define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX 127 /* Non back-to-back
331 inter frame gap part
332 2. max val */
333#define IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX 255 /* Mimimum IFG
334 Enforcement max val */
335#define IPGIFG_BACK_TO_BACK_IFG_MAX 127 /* back-to-back inter
336 frame gap max val */
337#define IPGIFG_NBTB_CS_IPG_MASK 0x7F000000
338#define IPGIFG_NBTB_IPG_MASK 0x007F0000
339#define IPGIFG_MIN_IFG_MASK 0x0000FF00
340#define IPGIFG_BTB_IPG_MASK 0x0000007F
341
342/* UCC GETH HAFDUP (Half Duplex Register) */
343#define HALFDUP_ALT_BEB_TRUNCATION_SHIFT (31 - 11) /* Alternate
344 Binary
345 Exponential
346 Backoff
347 Truncation
348 << shift */
349#define HALFDUP_ALT_BEB_TRUNCATION_MAX 0xf /* Alternate Binary
350 Exponential Backoff
351 Truncation max val */
352#define HALFDUP_ALT_BEB 0x00080000 /* Alternate
353 Binary
354 Exponential
355 Backoff */
356#define HALFDUP_BACK_PRESSURE_NO_BACKOFF 0x00040000 /* Back
357 pressure no
358 backoff */
359#define HALFDUP_NO_BACKOFF 0x00020000 /* No Backoff */
360#define HALFDUP_EXCESSIVE_DEFER 0x00010000 /* Excessive
361 Defer */
362#define HALFDUP_MAX_RETRANSMISSION_SHIFT (31 - 19) /* Maximum
363 Retransmission
364 << shift */
365#define HALFDUP_MAX_RETRANSMISSION_MAX 0xf /* Maximum
366 Retransmission max
367 val */
368#define HALFDUP_COLLISION_WINDOW_SHIFT (31 - 31) /* Collision
369 Window <<
370 shift */
371#define HALFDUP_COLLISION_WINDOW_MAX 0x3f /* Collision Window max
372 val */
373#define HALFDUP_ALT_BEB_TR_MASK 0x00F00000
374#define HALFDUP_RETRANS_MASK 0x0000F000
375#define HALFDUP_COL_WINDOW_MASK 0x0000003F
376
377/* UCC GETH UCCS (Ethernet Status Register) */
378#define UCCS_BPR 0x02 /* Back pressure (in
379 half duplex mode) */
380#define UCCS_PAU 0x02 /* Pause state (in full
381 duplex mode) */
382#define UCCS_MPD 0x01 /* Magic Packet
383 Detected */
384
385/* UCC GETH IFSTAT (Interface Status Register) */
386#define IFSTAT_EXCESS_DEFER 0x00000200 /* Excessive
387 transmission
388 defer */
389
390/* UCC GETH MACSTNADDR1 (Station Address Part 1 Register) */
391#define MACSTNADDR1_OCTET_6_SHIFT (31 - 7) /* Station
392 address 6th
393 octet <<
394 shift */
395#define MACSTNADDR1_OCTET_5_SHIFT (31 - 15) /* Station
396 address 5th
397 octet <<
398 shift */
399#define MACSTNADDR1_OCTET_4_SHIFT (31 - 23) /* Station
400 address 4th
401 octet <<
402 shift */
403#define MACSTNADDR1_OCTET_3_SHIFT (31 - 31) /* Station
404 address 3rd
405 octet <<
406 shift */
407
408/* UCC GETH MACSTNADDR2 (Station Address Part 2 Register) */
409#define MACSTNADDR2_OCTET_2_SHIFT (31 - 7) /* Station
410 address 2nd
411 octet <<
412 shift */
413#define MACSTNADDR2_OCTET_1_SHIFT (31 - 15) /* Station
414 address 1st
415 octet <<
416 shift */
417
418/* UCC GETH UEMPR (Ethernet Mac Parameter Register) */
419#define UEMPR_PAUSE_TIME_VALUE_SHIFT (31 - 15) /* Pause time
420 value <<
421 shift */
422#define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT (31 - 31) /* Extended
423 pause time
424 value <<
425 shift */
426
427/* UCC GETH UTBIPAR (Ten Bit Interface Physical Address Register) */
428#define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31) /* Phy address
429 << shift */
430#define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f /* Phy address
431 mask */
432
433/* UCC GETH UESCR (Ethernet Statistics Control Register) */
434#define UESCR_AUTOZ 0x8000 /* Automatically zero
435 addressed
436 statistical counter
437 values */
438#define UESCR_CLRCNT 0x4000 /* Clear all statistics
439 counters */
440#define UESCR_MAXCOV_SHIFT (15 - 7) /* Max
441 Coalescing
442 Value <<
443 shift */
444#define UESCR_SCOV_SHIFT (15 - 15) /* Status
445 Coalescing
446 Value <<
447 shift */
448
449/* UCC GETH UDSR (Data Synchronization Register) */
450#define UDSR_MAGIC 0x067E
451
452struct ucc_geth_thread_data_tx {
453 u8 res0[104];
454} __attribute__ ((packed));
455
456struct ucc_geth_thread_data_rx {
457 u8 res0[40];
458} __attribute__ ((packed));
459
460/* Send Queue Queue-Descriptor */
461struct ucc_geth_send_queue_qd {
462 u32 bd_ring_base; /* pointer to BD ring base address */
463 u8 res0[0x8];
464 u32 last_bd_completed_address;/* initialize to last entry in BD ring */
465 u8 res1[0x30];
466} __attribute__ ((packed));
467
468struct ucc_geth_send_queue_mem_region {
469 struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES];
470} __attribute__ ((packed));
471
472struct ucc_geth_thread_tx_pram {
473 u8 res0[64];
474} __attribute__ ((packed));
475
476struct ucc_geth_thread_rx_pram {
477 u8 res0[128];
478} __attribute__ ((packed));
479
480#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING 64
481#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8 64
482#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16 96
483
484struct ucc_geth_scheduler {
485 u16 cpucount0; /* CPU packet counter */
486 u16 cpucount1; /* CPU packet counter */
487 u16 cecount0; /* QE packet counter */
488 u16 cecount1; /* QE packet counter */
489 u16 cpucount2; /* CPU packet counter */
490 u16 cpucount3; /* CPU packet counter */
491 u16 cecount2; /* QE packet counter */
492 u16 cecount3; /* QE packet counter */
493 u16 cpucount4; /* CPU packet counter */
494 u16 cpucount5; /* CPU packet counter */
495 u16 cecount4; /* QE packet counter */
496 u16 cecount5; /* QE packet counter */
497 u16 cpucount6; /* CPU packet counter */
498 u16 cpucount7; /* CPU packet counter */
499 u16 cecount6; /* QE packet counter */
500 u16 cecount7; /* QE packet counter */
501 u32 weightstatus[NUM_TX_QUEUES]; /* accumulated weight factor */
502 u32 rtsrshadow; /* temporary variable handled by QE */
503 u32 time; /* temporary variable handled by QE */
504 u32 ttl; /* temporary variable handled by QE */
505 u32 mblinterval; /* max burst length interval */
506 u16 nortsrbytetime; /* normalized value of byte time in tsr units */
507 u8 fracsiz; /* radix 2 log value of denom. of
508 NorTSRByteTime */
509 u8 res0[1];
510 u8 strictpriorityq; /* Strict Priority Mask register */
511 u8 txasap; /* Transmit ASAP register */
512 u8 extrabw; /* Extra BandWidth register */
513 u8 oldwfqmask; /* temporary variable handled by QE */
514 u8 weightfactor[NUM_TX_QUEUES];
515 /**< weight factor for queues */
516 u32 minw; /* temporary variable handled by QE */
517 u8 res1[0x70 - 0x64];
518} __attribute__ ((packed));
519
520struct ucc_geth_tx_firmware_statistics_pram {
521 u32 sicoltx; /* single collision */
522 u32 mulcoltx; /* multiple collision */
523 u32 latecoltxfr; /* late collision */
524 u32 frabortduecol; /* frames aborted due to transmit collision */
525 u32 frlostinmactxer; /* frames lost due to internal MAC error
526 transmission that are not counted on any
527 other counter */
528 u32 carriersenseertx; /* carrier sense error */
529 u32 frtxok; /* frames transmitted OK */
530 u32 txfrexcessivedefer; /* frames with defferal time greater than
531 specified threshold */
532 u32 txpkts256; /* total packets (including bad) between 256
533 and 511 octets */
534 u32 txpkts512; /* total packets (including bad) between 512
535 and 1023 octets */
536 u32 txpkts1024; /* total packets (including bad) between 1024
537 and 1518 octets */
538 u32 txpktsjumbo; /* total packets (including bad) between 1024
539 and MAXLength octets */
540} __attribute__ ((packed));
541
542struct ucc_geth_rx_firmware_statistics_pram {
543 u32 frrxfcser; /* frames with crc error */
544 u32 fraligner; /* frames with alignment error */
545 u32 inrangelenrxer; /* in range length error */
546 u32 outrangelenrxer; /* out of range length error */
547 u32 frtoolong; /* frame too long */
548 u32 runt; /* runt */
549 u32 verylongevent; /* very long event */
550 u32 symbolerror; /* symbol error */
551 u32 dropbsy; /* drop because of BD not ready */
552 u8 res0[0x8];
553 u32 mismatchdrop; /* drop because of MAC filtering (e.g. address
554 or type mismatch) */
555 u32 underpkts; /* total frames less than 64 octets */
556 u32 pkts256; /* total frames (including bad) between 256 and
557 511 octets */
558 u32 pkts512; /* total frames (including bad) between 512 and
559 1023 octets */
560 u32 pkts1024; /* total frames (including bad) between 1024
561 and 1518 octets */
562 u32 pktsjumbo; /* total frames (including bad) between 1024
563 and MAXLength octets */
564 u32 frlossinmacer; /* frames lost because of internal MAC error
565 that is not counted in any other counter */
566 u32 pausefr; /* pause frames */
567 u8 res1[0x4];
568 u32 removevlan; /* total frames that had their VLAN tag removed
569 */
570 u32 replacevlan; /* total frames that had their VLAN tag
571 replaced */
572 u32 insertvlan; /* total frames that had their VLAN tag
573 inserted */
574} __attribute__ ((packed));
575
576struct ucc_geth_rx_interrupt_coalescing_entry {
577 u32 interruptcoalescingmaxvalue; /* interrupt coalescing max
578 value */
579 u32 interruptcoalescingcounter; /* interrupt coalescing counter,
580 initialize to
581 interruptcoalescingmaxvalue */
582} __attribute__ ((packed));
583
584struct ucc_geth_rx_interrupt_coalescing_table {
585 struct ucc_geth_rx_interrupt_coalescing_entry coalescingentry[NUM_RX_QUEUES];
586 /**< interrupt coalescing entry */
587} __attribute__ ((packed));
588
589struct ucc_geth_rx_prefetched_bds {
590 struct qe_bd bd[NUM_BDS_IN_PREFETCHED_BDS]; /* prefetched bd */
591} __attribute__ ((packed));
592
593struct ucc_geth_rx_bd_queues_entry {
594 u32 bdbaseptr; /* BD base pointer */
595 u32 bdptr; /* BD pointer */
596 u32 externalbdbaseptr; /* external BD base pointer */
597 u32 externalbdptr; /* external BD pointer */
598} __attribute__ ((packed));
599
600struct ucc_geth_tx_global_pram {
601 u16 temoder;
602 u8 res0[0x38 - 0x02];
603 u32 sqptr; /* a base pointer to send queue memory region */
604 u32 schedulerbasepointer; /* a base pointer to scheduler memory
605 region */
606 u32 txrmonbaseptr; /* base pointer to Tx RMON statistics counter */
607 u32 tstate; /* tx internal state. High byte contains
608 function code */
609 u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
610 u32 vtagtable[0x8]; /* 8 4-byte VLAN tags */
611 u32 tqptr; /* a base pointer to the Tx Queues Memory
612 Region */
613 u8 res2[0x80 - 0x74];
614} __attribute__ ((packed));
615
616/* structure representing Extended Filtering Global Parameters in PRAM */
617struct ucc_geth_exf_global_pram {
618 u32 l2pcdptr; /* individual address filter, high */
619 u8 res0[0x10 - 0x04];
620} __attribute__ ((packed));
621
622struct ucc_geth_rx_global_pram {
623 u32 remoder; /* ethernet mode reg. */
624 u32 rqptr; /* base pointer to the Rx Queues Memory Region*/
625 u32 res0[0x1];
626 u8 res1[0x20 - 0xC];
627 u16 typeorlen; /* cutoff point less than which, type/len field
628 is considered length */
629 u8 res2[0x1];
630 u8 rxgstpack; /* acknowledgement on GRACEFUL STOP RX command*/
631 u32 rxrmonbaseptr; /* base pointer to Rx RMON statistics counter */
632 u8 res3[0x30 - 0x28];
633 u32 intcoalescingptr; /* Interrupt coalescing table pointer */
634 u8 res4[0x36 - 0x34];
635 u8 rstate; /* rx internal state. High byte contains
636 function code */
637 u8 res5[0x46 - 0x37];
638 u16 mrblr; /* max receive buffer length reg. */
639 u32 rbdqptr; /* base pointer to RxBD parameter table
640 description */
641 u16 mflr; /* max frame length reg. */
642 u16 minflr; /* min frame length reg. */
643 u16 maxd1; /* max dma1 length reg. */
644 u16 maxd2; /* max dma2 length reg. */
645 u32 ecamptr; /* external CAM address */
646 u32 l2qt; /* VLAN priority mapping table. */
647 u32 l3qt[0x8]; /* IP priority mapping table. */
648 u16 vlantype; /* vlan type */
649 u16 vlantci; /* default vlan tci */
650 u8 addressfiltering[64]; /* address filtering data structure */
651 u32 exfGlobalParam; /* base address for extended filtering global
652 parameters */
653 u8 res6[0x100 - 0xC4]; /* Initialize to zero */
654} __attribute__ ((packed));
655
656#define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01
657
658/* structure representing InitEnet command */
659struct ucc_geth_init_pram {
660 u8 resinit1;
661 u8 resinit2;
662 u8 resinit3;
663 u8 resinit4;
664 u16 resinit5;
665 u8 res1[0x1];
666 u8 largestexternallookupkeysize;
667 u32 rgftgfrxglobal;
668 u32 rxthread[ENET_INIT_PARAM_MAX_ENTRIES_RX]; /* rx threads */
669 u8 res2[0x38 - 0x30];
670 u32 txglobal; /* tx global */
671 u32 txthread[ENET_INIT_PARAM_MAX_ENTRIES_TX]; /* tx threads */
672 u8 res3[0x1];
673} __attribute__ ((packed));
674
675#define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)
676#define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)
677
678#define ENET_INIT_PARAM_RISC_MASK 0x0000003f
679#define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0
680#define ENET_INIT_PARAM_SNUM_MASK 0xff000000
681#define ENET_INIT_PARAM_SNUM_SHIFT 24
682
683#define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x06
684#define ENET_INIT_PARAM_MAGIC_RES_INIT2 0x30
685#define ENET_INIT_PARAM_MAGIC_RES_INIT3 0xff
686#define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x00
687#define ENET_INIT_PARAM_MAGIC_RES_INIT5 0x0400
688
689/* structure representing 82xx Address Filtering Enet Address in PRAM */
690struct ucc_geth_82xx_enet_address {
691 u8 res1[0x2];
692 u16 h; /* address (MSB) */
693 u16 m; /* address */
694 u16 l; /* address (LSB) */
695} __attribute__ ((packed));
696
697/* structure representing 82xx Address Filtering PRAM */
698struct ucc_geth_82xx_address_filtering_pram {
699 u32 iaddr_h; /* individual address filter, high */
700 u32 iaddr_l; /* individual address filter, low */
701 u32 gaddr_h; /* group address filter, high */
702 u32 gaddr_l; /* group address filter, low */
703 struct ucc_geth_82xx_enet_address __iomem taddr;
704 struct ucc_geth_82xx_enet_address __iomem paddr[NUM_OF_PADDRS];
705 u8 res0[0x40 - 0x38];
706} __attribute__ ((packed));
707
708/* GETH Tx firmware statistics structure, used when calling
709 UCC_GETH_GetStatistics. */
710struct ucc_geth_tx_firmware_statistics {
711 u32 sicoltx; /* single collision */
712 u32 mulcoltx; /* multiple collision */
713 u32 latecoltxfr; /* late collision */
714 u32 frabortduecol; /* frames aborted due to transmit collision */
715 u32 frlostinmactxer; /* frames lost due to internal MAC error
716 transmission that are not counted on any
717 other counter */
718 u32 carriersenseertx; /* carrier sense error */
719 u32 frtxok; /* frames transmitted OK */
720 u32 txfrexcessivedefer; /* frames with defferal time greater than
721 specified threshold */
722 u32 txpkts256; /* total packets (including bad) between 256
723 and 511 octets */
724 u32 txpkts512; /* total packets (including bad) between 512
725 and 1023 octets */
726 u32 txpkts1024; /* total packets (including bad) between 1024
727 and 1518 octets */
728 u32 txpktsjumbo; /* total packets (including bad) between 1024
729 and MAXLength octets */
730} __attribute__ ((packed));
731
732/* GETH Rx firmware statistics structure, used when calling
733 UCC_GETH_GetStatistics. */
734struct ucc_geth_rx_firmware_statistics {
735 u32 frrxfcser; /* frames with crc error */
736 u32 fraligner; /* frames with alignment error */
737 u32 inrangelenrxer; /* in range length error */
738 u32 outrangelenrxer; /* out of range length error */
739 u32 frtoolong; /* frame too long */
740 u32 runt; /* runt */
741 u32 verylongevent; /* very long event */
742 u32 symbolerror; /* symbol error */
743 u32 dropbsy; /* drop because of BD not ready */
744 u8 res0[0x8];
745 u32 mismatchdrop; /* drop because of MAC filtering (e.g. address
746 or type mismatch) */
747 u32 underpkts; /* total frames less than 64 octets */
748 u32 pkts256; /* total frames (including bad) between 256 and
749 511 octets */
750 u32 pkts512; /* total frames (including bad) between 512 and
751 1023 octets */
752 u32 pkts1024; /* total frames (including bad) between 1024
753 and 1518 octets */
754 u32 pktsjumbo; /* total frames (including bad) between 1024
755 and MAXLength octets */
756 u32 frlossinmacer; /* frames lost because of internal MAC error
757 that is not counted in any other counter */
758 u32 pausefr; /* pause frames */
759 u8 res1[0x4];
760 u32 removevlan; /* total frames that had their VLAN tag removed
761 */
762 u32 replacevlan; /* total frames that had their VLAN tag
763 replaced */
764 u32 insertvlan; /* total frames that had their VLAN tag
765 inserted */
766} __attribute__ ((packed));
767
768/* GETH hardware statistics structure, used when calling
769 UCC_GETH_GetStatistics. */
770struct ucc_geth_hardware_statistics {
771 u32 tx64; /* Total number of frames (including bad
772 frames) transmitted that were exactly of the
773 minimal length (64 for un tagged, 68 for
774 tagged, or with length exactly equal to the
775 parameter MINLength */
776 u32 tx127; /* Total number of frames (including bad
777 frames) transmitted that were between
778 MINLength (Including FCS length==4) and 127
779 octets */
780 u32 tx255; /* Total number of frames (including bad
781 frames) transmitted that were between 128
782 (Including FCS length==4) and 255 octets */
783 u32 rx64; /* Total number of frames received including
784 bad frames that were exactly of the mninimal
785 length (64 bytes) */
786 u32 rx127; /* Total number of frames (including bad
787 frames) received that were between MINLength
788 (Including FCS length==4) and 127 octets */
789 u32 rx255; /* Total number of frames (including bad
790 frames) received that were between 128
791 (Including FCS length==4) and 255 octets */
792 u32 txok; /* Total number of octets residing in frames
793 that where involved in succesfull
794 transmission */
795 u16 txcf; /* Total number of PAUSE control frames
796 transmitted by this MAC */
797 u32 tmca; /* Total number of frames that were transmitted
798 succesfully with the group address bit set
799 that are not broadcast frames */
800 u32 tbca; /* Total number of frames transmitted
801 succesfully that had destination address
802 field equal to the broadcast address */
803 u32 rxfok; /* Total number of frames received OK */
804 u32 rxbok; /* Total number of octets received OK */
805 u32 rbyt; /* Total number of octets received including
806 octets in bad frames. Must be implemented in
807 HW because it includes octets in frames that
808 never even reach the UCC */
809 u32 rmca; /* Total number of frames that were received
810 succesfully with the group address bit set
811 that are not broadcast frames */
812 u32 rbca; /* Total number of frames received succesfully
813 that had destination address equal to the
814 broadcast address */
815} __attribute__ ((packed));
816
817/* UCC GETH Tx errors returned via TxConf callback */
818#define TX_ERRORS_DEF 0x0200
819#define TX_ERRORS_EXDEF 0x0100
820#define TX_ERRORS_LC 0x0080
821#define TX_ERRORS_RL 0x0040
822#define TX_ERRORS_RC_MASK 0x003C
823#define TX_ERRORS_RC_SHIFT 2
824#define TX_ERRORS_UN 0x0002
825#define TX_ERRORS_CSL 0x0001
826
827/* UCC GETH Rx errors returned via RxStore callback */
828#define RX_ERRORS_CMR 0x0200
829#define RX_ERRORS_M 0x0100
830#define RX_ERRORS_BC 0x0080
831#define RX_ERRORS_MC 0x0040
832
833/* Transmit BD. These are in addition to values defined in uccf. */
834#define T_VID 0x003c0000 /* insert VLAN id index mask. */
835#define T_DEF (((u32) TX_ERRORS_DEF ) << 16)
836#define T_EXDEF (((u32) TX_ERRORS_EXDEF ) << 16)
837#define T_LC (((u32) TX_ERRORS_LC ) << 16)
838#define T_RL (((u32) TX_ERRORS_RL ) << 16)
839#define T_RC_MASK (((u32) TX_ERRORS_RC_MASK ) << 16)
840#define T_UN (((u32) TX_ERRORS_UN ) << 16)
841#define T_CSL (((u32) TX_ERRORS_CSL ) << 16)
842#define T_ERRORS_REPORT (T_DEF | T_EXDEF | T_LC | T_RL | T_RC_MASK \
843 | T_UN | T_CSL) /* transmit errors to report */
844
845/* Receive BD. These are in addition to values defined in uccf. */
846#define R_LG 0x00200000 /* Frame length violation. */
847#define R_NO 0x00100000 /* Non-octet aligned frame. */
848#define R_SH 0x00080000 /* Short frame. */
849#define R_CR 0x00040000 /* CRC error. */
850#define R_OV 0x00020000 /* Overrun. */
851#define R_IPCH 0x00010000 /* IP checksum check failed. */
852#define R_CMR (((u32) RX_ERRORS_CMR ) << 16)
853#define R_M (((u32) RX_ERRORS_M ) << 16)
854#define R_BC (((u32) RX_ERRORS_BC ) << 16)
855#define R_MC (((u32) RX_ERRORS_MC ) << 16)
856#define R_ERRORS_REPORT (R_CMR | R_M | R_BC | R_MC) /* receive errors to
857 report */
858#define R_ERRORS_FATAL (R_LG | R_NO | R_SH | R_CR | \
859 R_OV | R_IPCH) /* receive errors to discard */
860
861/* Alignments */
862#define UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT 256
863#define UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT 128
864#define UCC_GETH_THREAD_RX_PRAM_ALIGNMENT 128
865#define UCC_GETH_THREAD_TX_PRAM_ALIGNMENT 64
866#define UCC_GETH_THREAD_DATA_ALIGNMENT 256 /* spec gives values
867 based on num of
868 threads, but always
869 using the maximum is
870 easier */
871#define UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32
872#define UCC_GETH_SCHEDULER_ALIGNMENT 4 /* This is a guess */
873#define UCC_GETH_TX_STATISTICS_ALIGNMENT 4 /* This is a guess */
874#define UCC_GETH_RX_STATISTICS_ALIGNMENT 4 /* This is a guess */
875#define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT 64
876#define UCC_GETH_RX_BD_QUEUES_ALIGNMENT 8 /* This is a guess */
877#define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT 128 /* This is a guess */
878#define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4 /* This
879 is a
880 guess
881 */
882#define UCC_GETH_RX_BD_RING_ALIGNMENT 32
883#define UCC_GETH_TX_BD_RING_ALIGNMENT 32
884#define UCC_GETH_MRBLR_ALIGNMENT 128
885#define UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT 4
886#define UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32
887#define UCC_GETH_RX_DATA_BUF_ALIGNMENT 64
888
889#define UCC_GETH_TAD_EF 0x80
890#define UCC_GETH_TAD_V 0x40
891#define UCC_GETH_TAD_REJ 0x20
892#define UCC_GETH_TAD_VTAG_OP_RIGHT_SHIFT 2
893#define UCC_GETH_TAD_VTAG_OP_SHIFT 6
894#define UCC_GETH_TAD_V_NON_VTAG_OP 0x20
895#define UCC_GETH_TAD_RQOS_SHIFT 0
896#define UCC_GETH_TAD_V_PRIORITY_SHIFT 5
897#define UCC_GETH_TAD_CFI 0x10
898
899#define UCC_GETH_VLAN_PRIORITY_MAX 8
900#define UCC_GETH_IP_PRIORITY_MAX 64
901#define UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX 8
902#define UCC_GETH_RX_BD_RING_SIZE_MIN 8
903#define UCC_GETH_TX_BD_RING_SIZE_MIN 2
904#define UCC_GETH_BD_RING_SIZE_MAX 0xffff
905
906#define UCC_GETH_SIZE_OF_BD QE_SIZEOF_BD
907
908/* Driver definitions */
909#define TX_BD_RING_LEN 0x10
910#define RX_BD_RING_LEN 0x10
911#define UCC_GETH_DEV_WEIGHT TX_BD_RING_LEN
912
913#define TX_RING_MOD_MASK(size) (size-1)
914#define RX_RING_MOD_MASK(size) (size-1)
915
916#define ENET_NUM_OCTETS_PER_ADDRESS 6
917#define ENET_GROUP_ADDR 0x01 /* Group address mask
918 for ethernet
919 addresses */
920
921#define TX_TIMEOUT (1*HZ)
922#define SKB_ALLOC_TIMEOUT 100000
923#define PHY_INIT_TIMEOUT 100000
924#define PHY_CHANGE_TIME 2
925
926/* Fast Ethernet (10/100 Mbps) */
927#define UCC_GETH_URFS_INIT 512 /* Rx virtual FIFO size
928 */
929#define UCC_GETH_URFET_INIT 256 /* 1/2 urfs */
930#define UCC_GETH_URFSET_INIT 384 /* 3/4 urfs */
931#define UCC_GETH_UTFS_INIT 512 /* Tx virtual FIFO size
932 */
933#define UCC_GETH_UTFET_INIT 256 /* 1/2 utfs */
934#define UCC_GETH_UTFTT_INIT 128
935/* Gigabit Ethernet (1000 Mbps) */
936#define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ /* Rx virtual
937 FIFO size */
938#define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/ /* 1/2 urfs */
939#define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/ /* 3/4 urfs */
940#define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/ /* Tx virtual
941 FIFO size */
942#define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/ /* 1/2 utfs */
943#define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/ /* */
944
945#define UCC_GETH_REMODER_INIT 0 /* bits that must be
946 set */
947#define UCC_GETH_TEMODER_INIT 0xC000 /* bits that must */
948#define UCC_GETH_UPSMR_INIT (UPSMR_RES1) /* Start value
949 for this
950 register */
951#define UCC_GETH_MACCFG1_INIT 0
952#define UCC_GETH_MACCFG2_INIT (MACCFG2_RESERVED_1)
953
954/* Ethernet Address Type. */
955enum enet_addr_type {
956 ENET_ADDR_TYPE_INDIVIDUAL,
957 ENET_ADDR_TYPE_GROUP,
958 ENET_ADDR_TYPE_BROADCAST
959};
960
961/* UCC GETH 82xx Ethernet Address Recognition Location */
962enum ucc_geth_enet_address_recognition_location {
963 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,/* station
964 address */
965 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_FIRST, /* additional
966 station
967 address
968 paddr1 */
969 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR2, /* additional
970 station
971 address
972 paddr2 */
973 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR3, /* additional
974 station
975 address
976 paddr3 */
977 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_LAST, /* additional
978 station
979 address
980 paddr4 */
981 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH, /* group hash */
982 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH /* individual
983 hash */
984};
985
986/* UCC GETH vlan operation tagged */
987enum ucc_geth_vlan_operation_tagged {
988 UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0, /* Tagged - nop */
989 UCC_GETH_VLAN_OPERATION_TAGGED_REPLACE_VID_PORTION_OF_Q_TAG
990 = 0x1, /* Tagged - replace vid portion of q tag */
991 UCC_GETH_VLAN_OPERATION_TAGGED_IF_VID0_REPLACE_VID_WITH_DEFAULT_VALUE
992 = 0x2, /* Tagged - if vid0 replace vid with default value */
993 UCC_GETH_VLAN_OPERATION_TAGGED_EXTRACT_Q_TAG_FROM_FRAME
994 = 0x3 /* Tagged - extract q tag from frame */
995};
996
997/* UCC GETH vlan operation non-tagged */
998enum ucc_geth_vlan_operation_non_tagged {
999 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0, /* Non tagged - nop */
1000 UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1 /* Non tagged -
1001 q tag insert
1002 */
1003};
1004
1005/* UCC GETH Rx Quality of Service Mode */
1006enum ucc_geth_qos_mode {
1007 UCC_GETH_QOS_MODE_DEFAULT = 0x0, /* default queue */
1008 UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L2_CRITERIA = 0x1, /* queue
1009 determined
1010 by L2
1011 criteria */
1012 UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L3_CRITERIA = 0x2 /* queue
1013 determined
1014 by L3
1015 criteria */
1016};
1017
1018/* UCC GETH Statistics Gathering Mode - These are bit flags, 'or' them together
1019 for combined functionality */
1020enum ucc_geth_statistics_gathering_mode {
1021 UCC_GETH_STATISTICS_GATHERING_MODE_NONE = 0x00000000, /* No
1022 statistics
1023 gathering */
1024 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE = 0x00000001,/* Enable
1025 hardware
1026 statistics
1027 gathering
1028 */
1029 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX = 0x00000004,/*Enable
1030 firmware
1031 tx
1032 statistics
1033 gathering
1034 */
1035 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX = 0x00000008/* Enable
1036 firmware
1037 rx
1038 statistics
1039 gathering
1040 */
1041};
1042
1043/* UCC GETH Pad and CRC Mode - Note, Padding without CRC is not possible */
1044enum ucc_geth_maccfg2_pad_and_crc_mode {
1045 UCC_GETH_PAD_AND_CRC_MODE_NONE
1046 = MACCFG2_PAD_AND_CRC_MODE_NONE, /* Neither Padding
1047 short frames
1048 nor CRC */
1049 UCC_GETH_PAD_AND_CRC_MODE_CRC_ONLY
1050 = MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY, /* Append
1051 CRC only */
1052 UCC_GETH_PAD_AND_CRC_MODE_PAD_AND_CRC =
1053 MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC
1054};
1055
1056/* UCC GETH upsmr Flow Control Mode */
1057enum ucc_geth_flow_control_mode {
1058 UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE = 0x00000000, /* No automatic
1059 flow control
1060 */
1061 UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_PAUSE_WHEN_EMERGENCY
1062 = 0x00004000 /* Send pause frame when RxFIFO reaches its
1063 emergency threshold */
1064};
1065
1066/* UCC GETH number of threads */
1067enum ucc_geth_num_of_threads {
1068 UCC_GETH_NUM_OF_THREADS_1 = 0x1, /* 1 */
1069 UCC_GETH_NUM_OF_THREADS_2 = 0x2, /* 2 */
1070 UCC_GETH_NUM_OF_THREADS_4 = 0x0, /* 4 */
1071 UCC_GETH_NUM_OF_THREADS_6 = 0x3, /* 6 */
1072 UCC_GETH_NUM_OF_THREADS_8 = 0x4 /* 8 */
1073};
1074
1075/* UCC GETH number of station addresses */
1076enum ucc_geth_num_of_station_addresses {
1077 UCC_GETH_NUM_OF_STATION_ADDRESSES_1, /* 1 */
1078 UCC_GETH_NUM_OF_STATION_ADDRESSES_5 /* 5 */
1079};
1080
1081/* UCC GETH 82xx Ethernet Address Container */
1082struct enet_addr_container {
1083 u8 address[ENET_NUM_OCTETS_PER_ADDRESS]; /* ethernet address */
1084 enum ucc_geth_enet_address_recognition_location location; /* location in
1085 82xx address
1086 recognition
1087 hardware */
1088 struct list_head node;
1089};
1090
1091#define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, struct enet_addr_container, node)
1092
1093/* UCC GETH Termination Action Descriptor (TAD) structure. */
1094struct ucc_geth_tad_params {
1095 int rx_non_dynamic_extended_features_mode;
1096 int reject_frame;
1097 enum ucc_geth_vlan_operation_tagged vtag_op;
1098 enum ucc_geth_vlan_operation_non_tagged vnontag_op;
1099 enum ucc_geth_qos_mode rqos;
1100 u8 vpri;
1101 u16 vid;
1102};
1103
1104/* GETH protocol initialization structure */
1105struct ucc_geth_info {
1106 struct ucc_fast_info uf_info;
1107 u8 numQueuesTx;
1108 u8 numQueuesRx;
1109 int ipCheckSumCheck;
1110 int ipCheckSumGenerate;
1111 int rxExtendedFiltering;
1112 u32 extendedFilteringChainPointer;
1113 u16 typeorlen;
1114 int dynamicMaxFrameLength;
1115 int dynamicMinFrameLength;
1116 u8 nonBackToBackIfgPart1;
1117 u8 nonBackToBackIfgPart2;
1118 u8 miminumInterFrameGapEnforcement;
1119 u8 backToBackInterFrameGap;
1120 int ipAddressAlignment;
1121 int lengthCheckRx;
1122 u32 mblinterval;
1123 u16 nortsrbytetime;
1124 u8 fracsiz;
1125 u8 strictpriorityq;
1126 u8 txasap;
1127 u8 extrabw;
1128 int miiPreambleSupress;
1129 u8 altBebTruncation;
1130 int altBeb;
1131 int backPressureNoBackoff;
1132 int noBackoff;
1133 int excessDefer;
1134 u8 maxRetransmission;
1135 u8 collisionWindow;
1136 int pro;
1137 int cap;
1138 int rsh;
1139 int rlpb;
1140 int cam;
1141 int bro;
1142 int ecm;
1143 int receiveFlowControl;
1144 int transmitFlowControl;
1145 u8 maxGroupAddrInHash;
1146 u8 maxIndAddrInHash;
1147 u8 prel;
1148 u16 maxFrameLength;
1149 u16 minFrameLength;
1150 u16 maxD1Length;
1151 u16 maxD2Length;
1152 u16 vlantype;
1153 u16 vlantci;
1154 u32 ecamptr;
1155 u32 eventRegMask;
1156 u16 pausePeriod;
1157 u16 extensionField;
1158 u8 phy_address;
1159 char mdio_bus[MII_BUS_ID_SIZE];
1160 u8 weightfactor[NUM_TX_QUEUES];
1161 u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES];
1162 u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX];
1163 u8 l3qt[UCC_GETH_IP_PRIORITY_MAX];
1164 u32 vtagtable[UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX];
1165 u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
1166 u16 bdRingLenTx[NUM_TX_QUEUES];
1167 u16 bdRingLenRx[NUM_RX_QUEUES];
1168 enum ucc_geth_num_of_station_addresses numStationAddresses;
1169 enum qe_fltr_largest_external_tbl_lookup_key_size
1170 largestexternallookupkeysize;
1171 enum ucc_geth_statistics_gathering_mode statisticsMode;
1172 enum ucc_geth_vlan_operation_tagged vlanOperationTagged;
1173 enum ucc_geth_vlan_operation_non_tagged vlanOperationNonTagged;
1174 enum ucc_geth_qos_mode rxQoSMode;
1175 enum ucc_geth_flow_control_mode aufc;
1176 enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc;
1177 enum ucc_geth_num_of_threads numThreadsTx;
1178 enum ucc_geth_num_of_threads numThreadsRx;
1179 enum qe_risc_allocation riscTx;
1180 enum qe_risc_allocation riscRx;
1181};
1182
1183/* structure representing UCC GETH */
1184struct ucc_geth_private {
1185 struct ucc_geth_info *ug_info;
1186 struct ucc_fast_private *uccf;
1187 struct net_device *dev;
1188 struct napi_struct napi;
1189 struct ucc_geth __iomem *ug_regs;
1190 struct ucc_geth_init_pram *p_init_enet_param_shadow;
1191 struct ucc_geth_exf_global_pram __iomem *p_exf_glbl_param;
1192 u32 exf_glbl_param_offset;
1193 struct ucc_geth_rx_global_pram __iomem *p_rx_glbl_pram;
1194 u32 rx_glbl_pram_offset;
1195 struct ucc_geth_tx_global_pram __iomem *p_tx_glbl_pram;
1196 u32 tx_glbl_pram_offset;
1197 struct ucc_geth_send_queue_mem_region __iomem *p_send_q_mem_reg;
1198 u32 send_q_mem_reg_offset;
1199 struct ucc_geth_thread_data_tx __iomem *p_thread_data_tx;
1200 u32 thread_dat_tx_offset;
1201 struct ucc_geth_thread_data_rx __iomem *p_thread_data_rx;
1202 u32 thread_dat_rx_offset;
1203 struct ucc_geth_scheduler __iomem *p_scheduler;
1204 u32 scheduler_offset;
1205 struct ucc_geth_tx_firmware_statistics_pram __iomem *p_tx_fw_statistics_pram;
1206 u32 tx_fw_statistics_pram_offset;
1207 struct ucc_geth_rx_firmware_statistics_pram __iomem *p_rx_fw_statistics_pram;
1208 u32 rx_fw_statistics_pram_offset;
1209 struct ucc_geth_rx_interrupt_coalescing_table __iomem *p_rx_irq_coalescing_tbl;
1210 u32 rx_irq_coalescing_tbl_offset;
1211 struct ucc_geth_rx_bd_queues_entry __iomem *p_rx_bd_qs_tbl;
1212 u32 rx_bd_qs_tbl_offset;
1213 u8 __iomem *p_tx_bd_ring[NUM_TX_QUEUES];
1214 u32 tx_bd_ring_offset[NUM_TX_QUEUES];
1215 u8 __iomem *p_rx_bd_ring[NUM_RX_QUEUES];
1216 u32 rx_bd_ring_offset[NUM_RX_QUEUES];
1217 u8 __iomem *confBd[NUM_TX_QUEUES];
1218 u8 __iomem *txBd[NUM_TX_QUEUES];
1219 u8 __iomem *rxBd[NUM_RX_QUEUES];
1220 int badFrame[NUM_RX_QUEUES];
1221 u16 cpucount[NUM_TX_QUEUES];
1222 u16 __iomem *p_cpucount[NUM_TX_QUEUES];
1223 int indAddrRegUsed[NUM_OF_PADDRS];
1224 u8 paddr[NUM_OF_PADDRS][ENET_NUM_OCTETS_PER_ADDRESS]; /* ethernet address */
1225 u8 numGroupAddrInHash;
1226 u8 numIndAddrInHash;
1227 u8 numIndAddrInReg;
1228 int rx_extended_features;
1229 int rx_non_dynamic_extended_features;
1230 struct list_head conf_skbs;
1231 struct list_head group_hash_q;
1232 struct list_head ind_hash_q;
1233 u32 saved_uccm;
1234 spinlock_t lock;
1235 /* pointers to arrays of skbuffs for tx and rx */
1236 struct sk_buff **tx_skbuff[NUM_TX_QUEUES];
1237 struct sk_buff **rx_skbuff[NUM_RX_QUEUES];
1238 /* indices pointing to the next free sbk in skb arrays */
1239 u16 skb_curtx[NUM_TX_QUEUES];
1240 u16 skb_currx[NUM_RX_QUEUES];
1241 /* index of the first skb which hasn't been transmitted yet. */
1242 u16 skb_dirtytx[NUM_TX_QUEUES];
1243
1244 struct ugeth_mii_info *mii_info;
1245 struct phy_device *phydev;
1246 phy_interface_t phy_interface;
1247 int max_speed;
1248 uint32_t msg_enable;
1249 int oldspeed;
1250 int oldduplex;
1251 int oldlink;
1252};
1253
1254void uec_set_ethtool_ops(struct net_device *netdev);
1255int init_flow_control_params(u32 automatic_flow_control_mode,
1256 int rx_flow_control_enable, int tx_flow_control_enable,
1257 u16 pause_period, u16 extension_field,
1258 u32 __iomem *upsmr_register, u32 __iomem *uempr_register,
1259 u32 __iomem *maccfg1_register);
1260
1261
1262#endif /* __UCC_GETH_H__ */