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Linux kernel mirror (for testing)
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linux
1/* linux/include/asm-arm/arch-msm/dma.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#ifndef __ASM_ARCH_MSM_DMA_H
17
18#include <linux/list.h>
19#include <asm/arch/msm_iomap.h>
20
21struct msm_dmov_cmd {
22 struct list_head list;
23 unsigned int cmdptr;
24 void (*complete_func)(struct msm_dmov_cmd *cmd, unsigned int result);
25/* void (*user_result_func)(struct msm_dmov_cmd *cmd); */
26};
27
28void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
29void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd);
30int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr);
31/* int msm_dmov_exec_cmd_etc(unsigned id, unsigned int cmdptr, int timeout, int interruptible); */
32
33
34
35#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
36#define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2))
37#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2))
38#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2))
39
40/* only security domain 3 is available to the ARM11
41 * SD0 -> mARM trusted, SD1 -> mARM nontrusted, SD2 -> aDSP, SD3 -> aARM
42 */
43
44#define DMOV_CMD_PTR(ch) DMOV_SD3(0x000, ch)
45#define DMOV_CMD_LIST (0 << 29) /* does not work */
46#define DMOV_CMD_PTR_LIST (1 << 29) /* works */
47#define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */
48#define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */
49#define DMOV_CMD_ADDR(addr) ((addr) >> 3)
50
51#define DMOV_RSLT(ch) DMOV_SD3(0x040, ch)
52#define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */
53#define DMOV_RSLT_ERROR (1 << 3)
54#define DMOV_RSLT_FLUSH (1 << 2)
55#define DMOV_RSLT_DONE (1 << 1) /* top pointer done */
56#define DMOV_RSLT_USER (1 << 0) /* command with FR force result */
57
58#define DMOV_FLUSH0(ch) DMOV_SD3(0x080, ch)
59#define DMOV_FLUSH1(ch) DMOV_SD3(0x0C0, ch)
60#define DMOV_FLUSH2(ch) DMOV_SD3(0x100, ch)
61#define DMOV_FLUSH3(ch) DMOV_SD3(0x140, ch)
62#define DMOV_FLUSH4(ch) DMOV_SD3(0x180, ch)
63#define DMOV_FLUSH5(ch) DMOV_SD3(0x1C0, ch)
64
65#define DMOV_STATUS(ch) DMOV_SD3(0x200, ch)
66#define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29))
67#define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3)
68#define DMOV_STATUS_RSLT_VALID (1 << 1)
69#define DMOV_STATUS_CMD_PTR_RDY (1 << 0)
70
71#define DMOV_ISR DMOV_SD3(0x380, 0)
72
73#define DMOV_CONFIG(ch) DMOV_SD3(0x300, ch)
74#define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2)
75#define DMOV_CONFIG_FORCE_FLUSH_RSLT (1 << 1)
76#define DMOV_CONFIG_IRQ_EN (1 << 0)
77
78/* channel assignments */
79
80#define DMOV_NAND_CHAN 7
81#define DMOV_NAND_CRCI_CMD 5
82#define DMOV_NAND_CRCI_DATA 4
83
84#define DMOV_SDC1_CHAN 8
85#define DMOV_SDC1_CRCI 6
86
87#define DMOV_SDC2_CHAN 8
88#define DMOV_SDC2_CRCI 7
89
90#define DMOV_TSIF_CHAN 10
91#define DMOV_TSIF_CRCI 10
92
93#define DMOV_USB_CHAN 11
94
95/* no client rate control ifc (eg, ram) */
96#define DMOV_NONE_CRCI 0
97
98
99/* If the CMD_PTR register has CMD_PTR_LIST selected, the data mover
100 * is going to walk a list of 32bit pointers as described below. Each
101 * pointer points to a *array* of dmov_s, etc structs. The last pointer
102 * in the list is marked with CMD_PTR_LP. The last struct in each array
103 * is marked with CMD_LC (see below).
104 */
105#define CMD_PTR_ADDR(addr) ((addr) >> 3)
106#define CMD_PTR_LP (1 << 31) /* last pointer */
107#define CMD_PTR_PT (3 << 29) /* ? */
108
109/* Single Item Mode */
110typedef struct {
111 unsigned cmd;
112 unsigned src;
113 unsigned dst;
114 unsigned len;
115} dmov_s;
116
117/* Scatter/Gather Mode */
118typedef struct {
119 unsigned cmd;
120 unsigned src_dscr;
121 unsigned dst_dscr;
122 unsigned _reserved;
123} dmov_sg;
124
125/* bits for the cmd field of the above structures */
126
127#define CMD_LC (1 << 31) /* last command */
128#define CMD_FR (1 << 22) /* force result -- does not work? */
129#define CMD_OCU (1 << 21) /* other channel unblock */
130#define CMD_OCB (1 << 20) /* other channel block */
131#define CMD_TCB (1 << 19) /* ? */
132#define CMD_DAH (1 << 18) /* destination address hold -- does not work?*/
133#define CMD_SAH (1 << 17) /* source address hold -- does not work? */
134
135#define CMD_MODE_SINGLE (0 << 0) /* dmov_s structure used */
136#define CMD_MODE_SG (1 << 0) /* untested */
137#define CMD_MODE_IND_SG (2 << 0) /* untested */
138#define CMD_MODE_BOX (3 << 0) /* untested */
139
140#define CMD_DST_SWAP_BYTES (1 << 14) /* exchange each byte n with byte n+1 */
141#define CMD_DST_SWAP_SHORTS (1 << 15) /* exchange each short n with short n+1 */
142#define CMD_DST_SWAP_WORDS (1 << 16) /* exchange each word n with word n+1 */
143
144#define CMD_SRC_SWAP_BYTES (1 << 11) /* exchange each byte n with byte n+1 */
145#define CMD_SRC_SWAP_SHORTS (1 << 12) /* exchange each short n with short n+1 */
146#define CMD_SRC_SWAP_WORDS (1 << 13) /* exchange each word n with word n+1 */
147
148#define CMD_DST_CRCI(n) (((n) & 15) << 7)
149#define CMD_SRC_CRCI(n) (((n) & 15) << 3)
150
151#endif