Linux kernel mirror (for testing)
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1#ifndef __ASM_SH_SYSTEM_H
2#define __ASM_SH_SYSTEM_H
3
4/*
5 * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
6 * Copyright (C) 2002 Paul Mundt
7 */
8
9#include <linux/irqflags.h>
10#include <linux/compiler.h>
11#include <linux/linkage.h>
12#include <asm/types.h>
13#include <asm/ptrace.h>
14
15#define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
16
17#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
18#define __icbi() \
19{ \
20 unsigned long __addr; \
21 __addr = 0xa8000000; \
22 __asm__ __volatile__( \
23 "icbi %0\n\t" \
24 : /* no output */ \
25 : "m" (__m(__addr))); \
26}
27#endif
28
29/*
30 * A brief note on ctrl_barrier(), the control register write barrier.
31 *
32 * Legacy SH cores typically require a sequence of 8 nops after
33 * modification of a control register in order for the changes to take
34 * effect. On newer cores (like the sh4a and sh5) this is accomplished
35 * with icbi.
36 *
37 * Also note that on sh4a in the icbi case we can forego a synco for the
38 * write barrier, as it's not necessary for control registers.
39 *
40 * Historically we have only done this type of barrier for the MMUCR, but
41 * it's also necessary for the CCR, so we make it generic here instead.
42 */
43#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
44#define mb() __asm__ __volatile__ ("synco": : :"memory")
45#define rmb() mb()
46#define wmb() __asm__ __volatile__ ("synco": : :"memory")
47#define ctrl_barrier() __icbi()
48#define read_barrier_depends() do { } while(0)
49#else
50#define mb() __asm__ __volatile__ ("": : :"memory")
51#define rmb() mb()
52#define wmb() __asm__ __volatile__ ("": : :"memory")
53#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
54#define read_barrier_depends() do { } while(0)
55#endif
56
57#ifdef CONFIG_SMP
58#define smp_mb() mb()
59#define smp_rmb() rmb()
60#define smp_wmb() wmb()
61#define smp_read_barrier_depends() read_barrier_depends()
62#else
63#define smp_mb() barrier()
64#define smp_rmb() barrier()
65#define smp_wmb() barrier()
66#define smp_read_barrier_depends() do { } while(0)
67#endif
68
69#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
70
71#ifdef CONFIG_GUSA_RB
72#include <asm/cmpxchg-grb.h>
73#else
74#include <asm/cmpxchg-irq.h>
75#endif
76
77extern void __xchg_called_with_bad_pointer(void);
78
79#define __xchg(ptr, x, size) \
80({ \
81 unsigned long __xchg__res; \
82 volatile void *__xchg_ptr = (ptr); \
83 switch (size) { \
84 case 4: \
85 __xchg__res = xchg_u32(__xchg_ptr, x); \
86 break; \
87 case 1: \
88 __xchg__res = xchg_u8(__xchg_ptr, x); \
89 break; \
90 default: \
91 __xchg_called_with_bad_pointer(); \
92 __xchg__res = x; \
93 break; \
94 } \
95 \
96 __xchg__res; \
97})
98
99#define xchg(ptr,x) \
100 ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
101
102/* This function doesn't exist, so you'll get a linker error
103 * if something tries to do an invalid cmpxchg(). */
104extern void __cmpxchg_called_with_bad_pointer(void);
105
106#define __HAVE_ARCH_CMPXCHG 1
107
108static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
109 unsigned long new, int size)
110{
111 switch (size) {
112 case 4:
113 return __cmpxchg_u32(ptr, old, new);
114 }
115 __cmpxchg_called_with_bad_pointer();
116 return old;
117}
118
119#define cmpxchg(ptr,o,n) \
120 ({ \
121 __typeof__(*(ptr)) _o_ = (o); \
122 __typeof__(*(ptr)) _n_ = (n); \
123 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
124 (unsigned long)_n_, sizeof(*(ptr))); \
125 })
126
127extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
128
129extern void *set_exception_table_vec(unsigned int vec, void *handler);
130
131static inline void *set_exception_table_evt(unsigned int evt, void *handler)
132{
133 return set_exception_table_vec(evt >> 5, handler);
134}
135
136/*
137 * SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
138 */
139#ifdef CONFIG_CPU_SH2A
140extern unsigned int instruction_size(unsigned int insn);
141#elif defined(CONFIG_SUPERH32)
142#define instruction_size(insn) (2)
143#else
144#define instruction_size(insn) (4)
145#endif
146
147extern unsigned long cached_to_uncached;
148
149extern struct dentry *sh_debugfs_root;
150
151/* XXX
152 * disable hlt during certain critical i/o operations
153 */
154#define HAVE_DISABLE_HLT
155void disable_hlt(void);
156void enable_hlt(void);
157
158void default_idle(void);
159void per_cpu_trap_init(void);
160
161asmlinkage void break_point_trap(void);
162
163#ifdef CONFIG_SUPERH32
164#define BUILD_TRAP_HANDLER(name) \
165asmlinkage void name##_trap_handler(unsigned long r4, unsigned long r5, \
166 unsigned long r6, unsigned long r7, \
167 struct pt_regs __regs)
168
169#define TRAP_HANDLER_DECL \
170 struct pt_regs *regs = RELOC_HIDE(&__regs, 0); \
171 unsigned int vec = regs->tra; \
172 (void)vec;
173#else
174#define BUILD_TRAP_HANDLER(name) \
175asmlinkage void name##_trap_handler(unsigned int vec, struct pt_regs *regs)
176#define TRAP_HANDLER_DECL
177#endif
178
179BUILD_TRAP_HANDLER(address_error);
180BUILD_TRAP_HANDLER(debug);
181BUILD_TRAP_HANDLER(bug);
182BUILD_TRAP_HANDLER(fpu_error);
183BUILD_TRAP_HANDLER(fpu_state_restore);
184
185#define arch_align_stack(x) (x)
186
187struct mem_access {
188 unsigned long (*from)(void *dst, const void *src, unsigned long cnt);
189 unsigned long (*to)(void *dst, const void *src, unsigned long cnt);
190};
191
192#ifdef CONFIG_SUPERH32
193# include "system_32.h"
194#else
195# include "system_64.h"
196#endif
197
198#endif