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1#ifndef __CPM_H 2#define __CPM_H 3 4#include <linux/compiler.h> 5#include <linux/types.h> 6 7/* Opcodes common to CPM1 and CPM2 8*/ 9#define CPM_CR_INIT_TRX ((ushort)0x0000) 10#define CPM_CR_INIT_RX ((ushort)0x0001) 11#define CPM_CR_INIT_TX ((ushort)0x0002) 12#define CPM_CR_HUNT_MODE ((ushort)0x0003) 13#define CPM_CR_STOP_TX ((ushort)0x0004) 14#define CPM_CR_GRA_STOP_TX ((ushort)0x0005) 15#define CPM_CR_RESTART_TX ((ushort)0x0006) 16#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007) 17#define CPM_CR_SET_GADDR ((ushort)0x0008) 18#define CPM_CR_SET_TIMER ((ushort)0x0008) 19#define CPM_CR_STOP_IDMA ((ushort)0x000b) 20 21/* Buffer descriptors used by many of the CPM protocols. */ 22typedef struct cpm_buf_desc { 23 ushort cbd_sc; /* Status and Control */ 24 ushort cbd_datlen; /* Data length in buffer */ 25 uint cbd_bufaddr; /* Buffer address in host memory */ 26} cbd_t; 27 28/* Buffer descriptor control/status used by serial 29 */ 30 31#define BD_SC_EMPTY (0x8000) /* Receive is empty */ 32#define BD_SC_READY (0x8000) /* Transmit is ready */ 33#define BD_SC_WRAP (0x2000) /* Last buffer descriptor */ 34#define BD_SC_INTRPT (0x1000) /* Interrupt on change */ 35#define BD_SC_LAST (0x0800) /* Last buffer in frame */ 36#define BD_SC_TC (0x0400) /* Transmit CRC */ 37#define BD_SC_CM (0x0200) /* Continous mode */ 38#define BD_SC_ID (0x0100) /* Rec'd too many idles */ 39#define BD_SC_P (0x0100) /* xmt preamble */ 40#define BD_SC_BR (0x0020) /* Break received */ 41#define BD_SC_FR (0x0010) /* Framing error */ 42#define BD_SC_PR (0x0008) /* Parity error */ 43#define BD_SC_NAK (0x0004) /* NAK - did not respond */ 44#define BD_SC_OV (0x0002) /* Overrun */ 45#define BD_SC_UN (0x0002) /* Underrun */ 46#define BD_SC_CD (0x0001) /* */ 47#define BD_SC_CL (0x0001) /* Collision */ 48 49/* Buffer descriptor control/status used by Ethernet receive. 50 * Common to SCC and FCC. 51 */ 52#define BD_ENET_RX_EMPTY (0x8000) 53#define BD_ENET_RX_WRAP (0x2000) 54#define BD_ENET_RX_INTR (0x1000) 55#define BD_ENET_RX_LAST (0x0800) 56#define BD_ENET_RX_FIRST (0x0400) 57#define BD_ENET_RX_MISS (0x0100) 58#define BD_ENET_RX_BC (0x0080) /* FCC Only */ 59#define BD_ENET_RX_MC (0x0040) /* FCC Only */ 60#define BD_ENET_RX_LG (0x0020) 61#define BD_ENET_RX_NO (0x0010) 62#define BD_ENET_RX_SH (0x0008) 63#define BD_ENET_RX_CR (0x0004) 64#define BD_ENET_RX_OV (0x0002) 65#define BD_ENET_RX_CL (0x0001) 66#define BD_ENET_RX_STATS (0x01ff) /* All status bits */ 67 68/* Buffer descriptor control/status used by Ethernet transmit. 69 * Common to SCC and FCC. 70 */ 71#define BD_ENET_TX_READY (0x8000) 72#define BD_ENET_TX_PAD (0x4000) 73#define BD_ENET_TX_WRAP (0x2000) 74#define BD_ENET_TX_INTR (0x1000) 75#define BD_ENET_TX_LAST (0x0800) 76#define BD_ENET_TX_TC (0x0400) 77#define BD_ENET_TX_DEF (0x0200) 78#define BD_ENET_TX_HB (0x0100) 79#define BD_ENET_TX_LC (0x0080) 80#define BD_ENET_TX_RL (0x0040) 81#define BD_ENET_TX_RCMASK (0x003c) 82#define BD_ENET_TX_UN (0x0002) 83#define BD_ENET_TX_CSL (0x0001) 84#define BD_ENET_TX_STATS (0x03ff) /* All status bits */ 85 86/* Buffer descriptor control/status used by Transparent mode SCC. 87 */ 88#define BD_SCC_TX_LAST (0x0800) 89 90/* Buffer descriptor control/status used by I2C. 91 */ 92#define BD_I2C_START (0x0400) 93 94int cpm_muram_init(void); 95unsigned long cpm_muram_alloc(unsigned long size, unsigned long align); 96int cpm_muram_free(unsigned long offset); 97unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size); 98void __iomem *cpm_muram_addr(unsigned long offset); 99dma_addr_t cpm_muram_dma(void __iomem *addr); 100int cpm_command(u32 command, u8 opcode); 101 102#endif