Linux kernel mirror (for testing)
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linux
1/*
2 * arch/powerpc/sysdev/qe_lib/ucc.c
3 *
4 * QE UCC API Set - UCC specific routines implementations.
5 *
6 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
7 *
8 * Authors: Shlomi Gridish <gridish@freescale.com>
9 * Li Yang <leoli@freescale.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/errno.h>
19#include <linux/slab.h>
20#include <linux/stddef.h>
21#include <linux/module.h>
22
23#include <asm/irq.h>
24#include <asm/io.h>
25#include <asm/immap_qe.h>
26#include <asm/qe.h>
27#include <asm/ucc.h>
28
29static DEFINE_SPINLOCK(ucc_lock);
30
31int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
32{
33 unsigned long flags;
34
35 if (ucc_num > UCC_MAX_NUM - 1)
36 return -EINVAL;
37
38 spin_lock_irqsave(&ucc_lock, flags);
39 clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
40 ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
41 spin_unlock_irqrestore(&ucc_lock, flags);
42
43 return 0;
44}
45EXPORT_SYMBOL(ucc_set_qe_mux_mii_mng);
46
47/* Configure the UCC to either Slow or Fast.
48 *
49 * A given UCC can be figured to support either "slow" devices (e.g. UART)
50 * or "fast" devices (e.g. Ethernet).
51 *
52 * 'ucc_num' is the UCC number, from 0 - 7.
53 *
54 * This function also sets the UCC_GUEMR_SET_RESERVED3 bit because that bit
55 * must always be set to 1.
56 */
57int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed)
58{
59 u8 __iomem *guemr;
60
61 /* The GUEMR register is at the same location for both slow and fast
62 devices, so we just use uccX.slow.guemr. */
63 switch (ucc_num) {
64 case 0: guemr = &qe_immr->ucc1.slow.guemr;
65 break;
66 case 1: guemr = &qe_immr->ucc2.slow.guemr;
67 break;
68 case 2: guemr = &qe_immr->ucc3.slow.guemr;
69 break;
70 case 3: guemr = &qe_immr->ucc4.slow.guemr;
71 break;
72 case 4: guemr = &qe_immr->ucc5.slow.guemr;
73 break;
74 case 5: guemr = &qe_immr->ucc6.slow.guemr;
75 break;
76 case 6: guemr = &qe_immr->ucc7.slow.guemr;
77 break;
78 case 7: guemr = &qe_immr->ucc8.slow.guemr;
79 break;
80 default:
81 return -EINVAL;
82 }
83
84 clrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,
85 UCC_GUEMR_SET_RESERVED3 | speed);
86
87 return 0;
88}
89
90static void get_cmxucr_reg(unsigned int ucc_num, __be32 **cmxucr,
91 unsigned int *reg_num, unsigned int *shift)
92{
93 unsigned int cmx = ((ucc_num & 1) << 1) + (ucc_num > 3);
94
95 *reg_num = cmx + 1;
96 *cmxucr = &qe_immr->qmx.cmxucr[cmx];
97 *shift = 16 - 8 * (ucc_num & 2);
98}
99
100int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask)
101{
102 __be32 *cmxucr;
103 unsigned int reg_num;
104 unsigned int shift;
105
106 /* check if the UCC number is in range. */
107 if (ucc_num > UCC_MAX_NUM - 1)
108 return -EINVAL;
109
110 get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift);
111
112 if (set)
113 setbits32(cmxucr, mask << shift);
114 else
115 clrbits32(cmxucr, mask << shift);
116
117 return 0;
118}
119
120int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
121 enum comm_dir mode)
122{
123 __be32 *cmxucr;
124 unsigned int reg_num;
125 unsigned int shift;
126 u32 clock_bits = 0;
127
128 /* check if the UCC number is in range. */
129 if (ucc_num > UCC_MAX_NUM - 1)
130 return -EINVAL;
131
132 /* The communications direction must be RX or TX */
133 if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX)))
134 return -EINVAL;
135
136 get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift);
137
138 switch (reg_num) {
139 case 1:
140 switch (clock) {
141 case QE_BRG1: clock_bits = 1; break;
142 case QE_BRG2: clock_bits = 2; break;
143 case QE_BRG7: clock_bits = 3; break;
144 case QE_BRG8: clock_bits = 4; break;
145 case QE_CLK9: clock_bits = 5; break;
146 case QE_CLK10: clock_bits = 6; break;
147 case QE_CLK11: clock_bits = 7; break;
148 case QE_CLK12: clock_bits = 8; break;
149 case QE_CLK15: clock_bits = 9; break;
150 case QE_CLK16: clock_bits = 10; break;
151 default: break;
152 }
153 break;
154 case 2:
155 switch (clock) {
156 case QE_BRG5: clock_bits = 1; break;
157 case QE_BRG6: clock_bits = 2; break;
158 case QE_BRG7: clock_bits = 3; break;
159 case QE_BRG8: clock_bits = 4; break;
160 case QE_CLK13: clock_bits = 5; break;
161 case QE_CLK14: clock_bits = 6; break;
162 case QE_CLK19: clock_bits = 7; break;
163 case QE_CLK20: clock_bits = 8; break;
164 case QE_CLK15: clock_bits = 9; break;
165 case QE_CLK16: clock_bits = 10; break;
166 default: break;
167 }
168 break;
169 case 3:
170 switch (clock) {
171 case QE_BRG9: clock_bits = 1; break;
172 case QE_BRG10: clock_bits = 2; break;
173 case QE_BRG15: clock_bits = 3; break;
174 case QE_BRG16: clock_bits = 4; break;
175 case QE_CLK3: clock_bits = 5; break;
176 case QE_CLK4: clock_bits = 6; break;
177 case QE_CLK17: clock_bits = 7; break;
178 case QE_CLK18: clock_bits = 8; break;
179 case QE_CLK7: clock_bits = 9; break;
180 case QE_CLK8: clock_bits = 10; break;
181 case QE_CLK16: clock_bits = 11; break;
182 default: break;
183 }
184 break;
185 case 4:
186 switch (clock) {
187 case QE_BRG13: clock_bits = 1; break;
188 case QE_BRG14: clock_bits = 2; break;
189 case QE_BRG15: clock_bits = 3; break;
190 case QE_BRG16: clock_bits = 4; break;
191 case QE_CLK5: clock_bits = 5; break;
192 case QE_CLK6: clock_bits = 6; break;
193 case QE_CLK21: clock_bits = 7; break;
194 case QE_CLK22: clock_bits = 8; break;
195 case QE_CLK7: clock_bits = 9; break;
196 case QE_CLK8: clock_bits = 10; break;
197 case QE_CLK16: clock_bits = 11; break;
198 default: break;
199 }
200 break;
201 default: break;
202 }
203
204 /* Check for invalid combination of clock and UCC number */
205 if (!clock_bits)
206 return -ENOENT;
207
208 if (mode == COMM_DIR_RX)
209 shift += 4;
210
211 clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
212 clock_bits << shift);
213
214 return 0;
215}