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1/*
2 * include/asm-ppc/mpc52xx_psc.h
3 *
4 * Definitions of consts/structs to drive the Freescale MPC52xx OnChip
5 * PSCs. Theses are shared between multiple drivers since a PSC can be
6 * UART, AC97, IR, I2S, ... So this header is in asm-ppc.
7 *
8 *
9 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
10 *
11 * Based/Extracted from some header of the 2.4 originally written by
12 * Dale Farnsworth <dfarnsworth@mvista.com>
13 *
14 * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
15 * Copyright (C) 2003 MontaVista, Software, Inc.
16 *
17 * This file is licensed under the terms of the GNU General Public License
18 * version 2. This program is licensed "as is" without any warranty of any
19 * kind, whether express or implied.
20 */
21
22#ifndef __ASM_MPC52xx_PSC_H__
23#define __ASM_MPC52xx_PSC_H__
24
25#include <asm/types.h>
26
27/* Max number of PSCs */
28#define MPC52xx_PSC_MAXNUM 6
29
30/* Programmable Serial Controller (PSC) status register bits */
31#define MPC52xx_PSC_SR_UNEX_RX 0x0001
32#define MPC52xx_PSC_SR_DATA_VAL 0x0002
33#define MPC52xx_PSC_SR_DATA_OVR 0x0004
34#define MPC52xx_PSC_SR_CMDSEND 0x0008
35#define MPC52xx_PSC_SR_CDE 0x0080
36#define MPC52xx_PSC_SR_RXRDY 0x0100
37#define MPC52xx_PSC_SR_RXFULL 0x0200
38#define MPC52xx_PSC_SR_TXRDY 0x0400
39#define MPC52xx_PSC_SR_TXEMP 0x0800
40#define MPC52xx_PSC_SR_OE 0x1000
41#define MPC52xx_PSC_SR_PE 0x2000
42#define MPC52xx_PSC_SR_FE 0x4000
43#define MPC52xx_PSC_SR_RB 0x8000
44
45/* PSC Command values */
46#define MPC52xx_PSC_RX_ENABLE 0x0001
47#define MPC52xx_PSC_RX_DISABLE 0x0002
48#define MPC52xx_PSC_TX_ENABLE 0x0004
49#define MPC52xx_PSC_TX_DISABLE 0x0008
50#define MPC52xx_PSC_SEL_MODE_REG_1 0x0010
51#define MPC52xx_PSC_RST_RX 0x0020
52#define MPC52xx_PSC_RST_TX 0x0030
53#define MPC52xx_PSC_RST_ERR_STAT 0x0040
54#define MPC52xx_PSC_RST_BRK_CHG_INT 0x0050
55#define MPC52xx_PSC_START_BRK 0x0060
56#define MPC52xx_PSC_STOP_BRK 0x0070
57
58/* PSC TxRx FIFO status bits */
59#define MPC52xx_PSC_RXTX_FIFO_ERR 0x0040
60#define MPC52xx_PSC_RXTX_FIFO_UF 0x0020
61#define MPC52xx_PSC_RXTX_FIFO_OF 0x0010
62#define MPC52xx_PSC_RXTX_FIFO_FR 0x0008
63#define MPC52xx_PSC_RXTX_FIFO_FULL 0x0004
64#define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002
65#define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001
66
67/* PSC interrupt mask bits */
68#define MPC52xx_PSC_IMR_TXRDY 0x0100
69#define MPC52xx_PSC_IMR_RXRDY 0x0200
70#define MPC52xx_PSC_IMR_DB 0x0400
71#define MPC52xx_PSC_IMR_IPC 0x8000
72
73/* PSC input port change bit */
74#define MPC52xx_PSC_CTS 0x01
75#define MPC52xx_PSC_DCD 0x02
76#define MPC52xx_PSC_D_CTS 0x10
77#define MPC52xx_PSC_D_DCD 0x20
78
79/* PSC mode fields */
80#define MPC52xx_PSC_MODE_5_BITS 0x00
81#define MPC52xx_PSC_MODE_6_BITS 0x01
82#define MPC52xx_PSC_MODE_7_BITS 0x02
83#define MPC52xx_PSC_MODE_8_BITS 0x03
84#define MPC52xx_PSC_MODE_BITS_MASK 0x03
85#define MPC52xx_PSC_MODE_PAREVEN 0x00
86#define MPC52xx_PSC_MODE_PARODD 0x04
87#define MPC52xx_PSC_MODE_PARFORCE 0x08
88#define MPC52xx_PSC_MODE_PARNONE 0x10
89#define MPC52xx_PSC_MODE_ERR 0x20
90#define MPC52xx_PSC_MODE_FFULL 0x40
91#define MPC52xx_PSC_MODE_RXRTS 0x80
92
93#define MPC52xx_PSC_MODE_ONE_STOP_5_BITS 0x00
94#define MPC52xx_PSC_MODE_ONE_STOP 0x07
95#define MPC52xx_PSC_MODE_TWO_STOP 0x0f
96
97#define MPC52xx_PSC_RFNUM_MASK 0x01ff
98
99
100/* Structure of the hardware registers */
101struct mpc52xx_psc {
102 u8 mode; /* PSC + 0x00 */
103 u8 reserved0[3];
104 union { /* PSC + 0x04 */
105 u16 status;
106 u16 clock_select;
107 } sr_csr;
108#define mpc52xx_psc_status sr_csr.status
109#define mpc52xx_psc_clock_select sr_csr.clock_select
110 u16 reserved1;
111 u8 command; /* PSC + 0x08 */
112 u8 reserved2[3];
113 union { /* PSC + 0x0c */
114 u8 buffer_8;
115 u16 buffer_16;
116 u32 buffer_32;
117 } buffer;
118#define mpc52xx_psc_buffer_8 buffer.buffer_8
119#define mpc52xx_psc_buffer_16 buffer.buffer_16
120#define mpc52xx_psc_buffer_32 buffer.buffer_32
121 union { /* PSC + 0x10 */
122 u8 ipcr;
123 u8 acr;
124 } ipcr_acr;
125#define mpc52xx_psc_ipcr ipcr_acr.ipcr
126#define mpc52xx_psc_acr ipcr_acr.acr
127 u8 reserved3[3];
128 union { /* PSC + 0x14 */
129 u16 isr;
130 u16 imr;
131 } isr_imr;
132#define mpc52xx_psc_isr isr_imr.isr
133#define mpc52xx_psc_imr isr_imr.imr
134 u16 reserved4;
135 u8 ctur; /* PSC + 0x18 */
136 u8 reserved5[3];
137 u8 ctlr; /* PSC + 0x1c */
138 u8 reserved6[3];
139 u32 ccr; /* PSC + 0x20 */
140 u32 ac97_slots; /* PSC + 0x24 */
141 u32 ac97_cmd; /* PSC + 0x28 */
142 u32 ac97_data; /* PSC + 0x2c */
143 u8 ivr; /* PSC + 0x30 */
144 u8 reserved8[3];
145 u8 ip; /* PSC + 0x34 */
146 u8 reserved9[3];
147 u8 op1; /* PSC + 0x38 */
148 u8 reserved10[3];
149 u8 op0; /* PSC + 0x3c */
150 u8 reserved11[3];
151 u32 sicr; /* PSC + 0x40 */
152 u8 ircr1; /* PSC + 0x44 */
153 u8 reserved13[3];
154 u8 ircr2; /* PSC + 0x44 */
155 u8 reserved14[3];
156 u8 irsdr; /* PSC + 0x4c */
157 u8 reserved15[3];
158 u8 irmdr; /* PSC + 0x50 */
159 u8 reserved16[3];
160 u8 irfdr; /* PSC + 0x54 */
161 u8 reserved17[3];
162};
163
164struct mpc52xx_psc_fifo {
165 u16 rfnum; /* PSC + 0x58 */
166 u16 reserved18;
167 u16 tfnum; /* PSC + 0x5c */
168 u16 reserved19;
169 u32 rfdata; /* PSC + 0x60 */
170 u16 rfstat; /* PSC + 0x64 */
171 u16 reserved20;
172 u8 rfcntl; /* PSC + 0x68 */
173 u8 reserved21[5];
174 u16 rfalarm; /* PSC + 0x6e */
175 u16 reserved22;
176 u16 rfrptr; /* PSC + 0x72 */
177 u16 reserved23;
178 u16 rfwptr; /* PSC + 0x76 */
179 u16 reserved24;
180 u16 rflrfptr; /* PSC + 0x7a */
181 u16 reserved25;
182 u16 rflwfptr; /* PSC + 0x7e */
183 u32 tfdata; /* PSC + 0x80 */
184 u16 tfstat; /* PSC + 0x84 */
185 u16 reserved26;
186 u8 tfcntl; /* PSC + 0x88 */
187 u8 reserved27[5];
188 u16 tfalarm; /* PSC + 0x8e */
189 u16 reserved28;
190 u16 tfrptr; /* PSC + 0x92 */
191 u16 reserved29;
192 u16 tfwptr; /* PSC + 0x96 */
193 u16 reserved30;
194 u16 tflrfptr; /* PSC + 0x9a */
195 u16 reserved31;
196 u16 tflwfptr; /* PSC + 0x9e */
197};
198
199
200#endif /* __ASM_MPC52xx_PSC_H__ */