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1/* 2 * 3c359.c (c) 2000 Mike Phillips (mikep@linuxtr.net) All Rights Reserved 3 * 4 * Linux driver for 3Com 3c359 Tokenlink Velocity XL PCI NIC 5 * 6 * Base Driver Olympic: 7 * Written 1999 Peter De Schrijver & Mike Phillips 8 * 9 * This software may be used and distributed according to the terms 10 * of the GNU General Public License, incorporated herein by reference. 11 * 12 * 7/17/00 - Clean up, version number 0.9.0. Ready to release to the world. 13 * 14 * 2/16/01 - Port up to kernel 2.4.2 ready for submission into the kernel. 15 * 3/05/01 - Last clean up stuff before submission. 16 * 2/15/01 - Finally, update to new pci api. 17 * 18 * To Do: 19 */ 20 21/* 22 * Technical Card Details 23 * 24 * All access to data is done with 16/8 bit transfers. The transfer 25 * method really sucks. You can only read or write one location at a time. 26 * 27 * Also, the microcode for the card must be uploaded if the card does not have 28 * the flashrom on board. This is a 28K bloat in the driver when compiled 29 * as a module. 30 * 31 * Rx is very simple, status into a ring of descriptors, dma data transfer, 32 * interrupts to tell us when a packet is received. 33 * 34 * Tx is a little more interesting. Similar scenario, descriptor and dma data 35 * transfers, but we don't have to interrupt the card to tell it another packet 36 * is ready for transmission, we are just doing simple memory writes, not io or mmio 37 * writes. The card can be set up to simply poll on the next 38 * descriptor pointer and when this value is non-zero will automatically download 39 * the next packet. The card then interrupts us when the packet is done. 40 * 41 */ 42 43#define XL_DEBUG 0 44 45#include <linux/module.h> 46#include <linux/kernel.h> 47#include <linux/errno.h> 48#include <linux/timer.h> 49#include <linux/in.h> 50#include <linux/ioport.h> 51#include <linux/string.h> 52#include <linux/proc_fs.h> 53#include <linux/ptrace.h> 54#include <linux/skbuff.h> 55#include <linux/interrupt.h> 56#include <linux/delay.h> 57#include <linux/netdevice.h> 58#include <linux/trdevice.h> 59#include <linux/stddef.h> 60#include <linux/init.h> 61#include <linux/pci.h> 62#include <linux/spinlock.h> 63#include <linux/bitops.h> 64 65#include <net/checksum.h> 66 67#include <asm/io.h> 68#include <asm/system.h> 69 70#include "3c359.h" 71 72static char version[] __devinitdata = 73"3c359.c v1.2.0 2/17/01 - Mike Phillips (mikep@linuxtr.net)" ; 74 75MODULE_AUTHOR("Mike Phillips <mikep@linuxtr.net>") ; 76MODULE_DESCRIPTION("3Com 3C359 Velocity XL Token Ring Adapter Driver \n") ; 77 78/* Module paramters */ 79 80/* Ring Speed 0,4,16 81 * 0 = Autosense 82 * 4,16 = Selected speed only, no autosense 83 * This allows the card to be the first on the ring 84 * and become the active monitor. 85 * 86 * WARNING: Some hubs will allow you to insert 87 * at the wrong speed. 88 * 89 * The adapter will _not_ fail to open if there are no 90 * active monitors on the ring, it will simply open up in 91 * its last known ringspeed if no ringspeed is specified. 92 */ 93 94static int ringspeed[XL_MAX_ADAPTERS] = {0,} ; 95 96module_param_array(ringspeed, int, NULL, 0); 97MODULE_PARM_DESC(ringspeed,"3c359: Ringspeed selection - 4,16 or 0") ; 98 99/* Packet buffer size */ 100 101static int pkt_buf_sz[XL_MAX_ADAPTERS] = {0,} ; 102 103module_param_array(pkt_buf_sz, int, NULL, 0) ; 104MODULE_PARM_DESC(pkt_buf_sz,"3c359: Initial buffer size") ; 105/* Message Level */ 106 107static int message_level[XL_MAX_ADAPTERS] = {0,} ; 108 109module_param_array(message_level, int, NULL, 0) ; 110MODULE_PARM_DESC(message_level, "3c359: Level of reported messages \n") ; 111/* 112 * This is a real nasty way of doing this, but otherwise you 113 * will be stuck with 1555 lines of hex #'s in the code. 114 */ 115 116#include "3c359_microcode.h" 117 118static struct pci_device_id xl_pci_tbl[] = 119{ 120 {PCI_VENDOR_ID_3COM,PCI_DEVICE_ID_3COM_3C359, PCI_ANY_ID, PCI_ANY_ID, }, 121 { } /* terminate list */ 122}; 123MODULE_DEVICE_TABLE(pci,xl_pci_tbl) ; 124 125static int xl_init(struct net_device *dev); 126static int xl_open(struct net_device *dev); 127static int xl_open_hw(struct net_device *dev) ; 128static int xl_hw_reset(struct net_device *dev); 129static int xl_xmit(struct sk_buff *skb, struct net_device *dev); 130static void xl_dn_comp(struct net_device *dev); 131static int xl_close(struct net_device *dev); 132static void xl_set_rx_mode(struct net_device *dev); 133static irqreturn_t xl_interrupt(int irq, void *dev_id); 134static struct net_device_stats * xl_get_stats(struct net_device *dev); 135static int xl_set_mac_address(struct net_device *dev, void *addr) ; 136static void xl_arb_cmd(struct net_device *dev); 137static void xl_asb_cmd(struct net_device *dev) ; 138static void xl_srb_cmd(struct net_device *dev, int srb_cmd) ; 139static void xl_wait_misr_flags(struct net_device *dev) ; 140static int xl_change_mtu(struct net_device *dev, int mtu); 141static void xl_srb_bh(struct net_device *dev) ; 142static void xl_asb_bh(struct net_device *dev) ; 143static void xl_reset(struct net_device *dev) ; 144static void xl_freemem(struct net_device *dev) ; 145 146 147/* EEProm Access Functions */ 148static u16 xl_ee_read(struct net_device *dev, int ee_addr) ; 149static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value) ; 150 151/* Debugging functions */ 152#if XL_DEBUG 153static void print_tx_state(struct net_device *dev) ; 154static void print_rx_state(struct net_device *dev) ; 155 156static void print_tx_state(struct net_device *dev) 157{ 158 159 struct xl_private *xl_priv = netdev_priv(dev); 160 struct xl_tx_desc *txd ; 161 u8 __iomem *xl_mmio = xl_priv->xl_mmio ; 162 int i ; 163 164 printk("tx_ring_head: %d, tx_ring_tail: %d, free_ent: %d \n",xl_priv->tx_ring_head, 165 xl_priv->tx_ring_tail, xl_priv->free_ring_entries) ; 166 printk("Ring , Address , FSH , DnNextPtr, Buffer, Buffer_Len \n"); 167 for (i = 0; i < 16; i++) { 168 txd = &(xl_priv->xl_tx_ring[i]) ; 169 printk("%d, %08lx, %08x, %08x, %08x, %08x \n", i, virt_to_bus(txd), 170 txd->framestartheader, txd->dnnextptr, txd->buffer, txd->buffer_length ) ; 171 } 172 173 printk("DNLISTPTR = %04x \n", readl(xl_mmio + MMIO_DNLISTPTR) ); 174 175 printk("DmaCtl = %04x \n", readl(xl_mmio + MMIO_DMA_CTRL) ); 176 printk("Queue status = %0x \n",netif_running(dev) ) ; 177} 178 179static void print_rx_state(struct net_device *dev) 180{ 181 182 struct xl_private *xl_priv = netdev_priv(dev); 183 struct xl_rx_desc *rxd ; 184 u8 __iomem *xl_mmio = xl_priv->xl_mmio ; 185 int i ; 186 187 printk("rx_ring_tail: %d \n", xl_priv->rx_ring_tail) ; 188 printk("Ring , Address , FrameState , UPNextPtr, FragAddr, Frag_Len \n"); 189 for (i = 0; i < 16; i++) { 190 /* rxd = (struct xl_rx_desc *)xl_priv->rx_ring_dma_addr + (i * sizeof(struct xl_rx_desc)) ; */ 191 rxd = &(xl_priv->xl_rx_ring[i]) ; 192 printk("%d, %08lx, %08x, %08x, %08x, %08x \n", i, virt_to_bus(rxd), 193 rxd->framestatus, rxd->upnextptr, rxd->upfragaddr, rxd->upfraglen ) ; 194 } 195 196 printk("UPLISTPTR = %04x \n", readl(xl_mmio + MMIO_UPLISTPTR) ); 197 198 printk("DmaCtl = %04x \n", readl(xl_mmio + MMIO_DMA_CTRL) ); 199 printk("Queue status = %0x \n",netif_running(dev) ) ; 200} 201#endif 202 203/* 204 * Read values from the on-board EEProm. This looks very strange 205 * but you have to wait for the EEProm to get/set the value before 206 * passing/getting the next value from the nic. As with all requests 207 * on this nic it has to be done in two stages, a) tell the nic which 208 * memory address you want to access and b) pass/get the value from the nic. 209 * With the EEProm, you have to wait before and inbetween access a) and b). 210 * As this is only read at initialization time and the wait period is very 211 * small we shouldn't have to worry about scheduling issues. 212 */ 213 214static u16 xl_ee_read(struct net_device *dev, int ee_addr) 215{ 216 struct xl_private *xl_priv = netdev_priv(dev); 217 u8 __iomem *xl_mmio = xl_priv->xl_mmio ; 218 219 /* Wait for EEProm to not be busy */ 220 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 221 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ; 222 223 /* Tell EEProm what we want to do and where */ 224 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 225 writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ; 226 227 /* Wait for EEProm to not be busy */ 228 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 229 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ; 230 231 /* Tell EEProm what we want to do and where */ 232 writel(IO_WORD_WRITE | EECONTROL , xl_mmio + MMIO_MAC_ACCESS_CMD) ; 233 writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ; 234 235 /* Finally read the value from the EEProm */ 236 writel(IO_WORD_READ | EEDATA , xl_mmio + MMIO_MAC_ACCESS_CMD) ; 237 return readw(xl_mmio + MMIO_MACDATA) ; 238} 239 240/* 241 * Write values to the onboard eeprom. As with eeprom read you need to 242 * set which location to write, wait, value to write, wait, with the 243 * added twist of having to enable eeprom writes as well. 244 */ 245 246static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value) 247{ 248 struct xl_private *xl_priv = netdev_priv(dev); 249 u8 __iomem *xl_mmio = xl_priv->xl_mmio ; 250 251 /* Wait for EEProm to not be busy */ 252 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 253 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ; 254 255 /* Enable write/erase */ 256 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 257 writew(EE_ENABLE_WRITE, xl_mmio + MMIO_MACDATA) ; 258 259 /* Wait for EEProm to not be busy */ 260 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 261 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ; 262 263 /* Put the value we want to write into EEDATA */ 264 writel(IO_WORD_WRITE | EEDATA, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 265 writew(ee_value, xl_mmio + MMIO_MACDATA) ; 266 267 /* Tell EEProm to write eevalue into ee_addr */ 268 writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 269 writew(EEWRITE + ee_addr, xl_mmio + MMIO_MACDATA) ; 270 271 /* Wait for EEProm to not be busy, to ensure write gets done */ 272 writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 273 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ; 274 275 return ; 276} 277 278static int __devinit xl_probe(struct pci_dev *pdev, 279 const struct pci_device_id *ent) 280{ 281 struct net_device *dev ; 282 struct xl_private *xl_priv ; 283 static int card_no = -1 ; 284 int i ; 285 286 card_no++ ; 287 288 if (pci_enable_device(pdev)) { 289 return -ENODEV ; 290 } 291 292 pci_set_master(pdev); 293 294 if ((i = pci_request_regions(pdev,"3c359"))) { 295 return i ; 296 } ; 297 298 /* 299 * Allowing init_trdev to allocate the dev->priv structure will align xl_private 300 * on a 32 bytes boundary which we need for the rx/tx descriptors 301 */ 302 303 dev = alloc_trdev(sizeof(struct xl_private)) ; 304 if (!dev) { 305 pci_release_regions(pdev) ; 306 return -ENOMEM ; 307 } 308 xl_priv = netdev_priv(dev); 309 310#if XL_DEBUG 311 printk("pci_device: %p, dev:%p, dev->priv: %p, ba[0]: %10x, ba[1]:%10x\n", 312 pdev, dev, netdev_priv(dev), (unsigned int)pdev->resource[0].start, (unsigned int)pdev->resource[1].start); 313#endif 314 315 dev->irq=pdev->irq; 316 dev->base_addr=pci_resource_start(pdev,0) ; 317 xl_priv->xl_card_name = pci_name(pdev); 318 xl_priv->xl_mmio=ioremap(pci_resource_start(pdev,1), XL_IO_SPACE); 319 xl_priv->pdev = pdev ; 320 321 if ((pkt_buf_sz[card_no] < 100) || (pkt_buf_sz[card_no] > 18000) ) 322 xl_priv->pkt_buf_sz = PKT_BUF_SZ ; 323 else 324 xl_priv->pkt_buf_sz = pkt_buf_sz[card_no] ; 325 326 dev->mtu = xl_priv->pkt_buf_sz - TR_HLEN ; 327 xl_priv->xl_ring_speed = ringspeed[card_no] ; 328 xl_priv->xl_message_level = message_level[card_no] ; 329 xl_priv->xl_functional_addr[0] = xl_priv->xl_functional_addr[1] = xl_priv->xl_functional_addr[2] = xl_priv->xl_functional_addr[3] = 0 ; 330 xl_priv->xl_copy_all_options = 0 ; 331 332 if((i = xl_init(dev))) { 333 iounmap(xl_priv->xl_mmio) ; 334 free_netdev(dev) ; 335 pci_release_regions(pdev) ; 336 return i ; 337 } 338 339 dev->open=&xl_open; 340 dev->hard_start_xmit=&xl_xmit; 341 dev->change_mtu=&xl_change_mtu; 342 dev->stop=&xl_close; 343 dev->do_ioctl=NULL; 344 dev->set_multicast_list=&xl_set_rx_mode; 345 dev->get_stats=&xl_get_stats ; 346 dev->set_mac_address=&xl_set_mac_address ; 347 SET_NETDEV_DEV(dev, &pdev->dev); 348 349 pci_set_drvdata(pdev,dev) ; 350 if ((i = register_netdev(dev))) { 351 printk(KERN_ERR "3C359, register netdev failed\n") ; 352 pci_set_drvdata(pdev,NULL) ; 353 iounmap(xl_priv->xl_mmio) ; 354 free_netdev(dev) ; 355 pci_release_regions(pdev) ; 356 return i ; 357 } 358 359 printk(KERN_INFO "3C359: %s registered as: %s\n",xl_priv->xl_card_name,dev->name) ; 360 361 return 0; 362} 363 364 365static int __devinit xl_init(struct net_device *dev) 366{ 367 struct xl_private *xl_priv = netdev_priv(dev); 368 369 printk(KERN_INFO "%s \n", version); 370 printk(KERN_INFO "%s: I/O at %hx, MMIO at %p, using irq %d\n", 371 xl_priv->xl_card_name, (unsigned int)dev->base_addr ,xl_priv->xl_mmio, dev->irq); 372 373 spin_lock_init(&xl_priv->xl_lock) ; 374 375 return xl_hw_reset(dev) ; 376 377} 378 379 380/* 381 * Hardware reset. This needs to be a separate entity as we need to reset the card 382 * when we change the EEProm settings. 383 */ 384 385static int xl_hw_reset(struct net_device *dev) 386{ 387 struct xl_private *xl_priv = netdev_priv(dev); 388 u8 __iomem *xl_mmio = xl_priv->xl_mmio ; 389 unsigned long t ; 390 u16 i ; 391 u16 result_16 ; 392 u8 result_8 ; 393 u16 start ; 394 int j ; 395 396 /* 397 * Reset the card. If the card has got the microcode on board, we have 398 * missed the initialization interrupt, so we must always do this. 399 */ 400 401 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ; 402 403 /* 404 * Must wait for cmdInProgress bit (12) to clear before continuing with 405 * card configuration. 406 */ 407 408 t=jiffies; 409 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { 410 schedule(); 411 if(jiffies-t > 40*HZ) { 412 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL card not responding to global reset.\n", dev->name); 413 return -ENODEV; 414 } 415 } 416 417 /* 418 * Enable pmbar by setting bit in CPAttention 419 */ 420 421 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 422 result_8 = readb(xl_mmio + MMIO_MACDATA) ; 423 result_8 = result_8 | CPA_PMBARVIS ; 424 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 425 writeb(result_8, xl_mmio + MMIO_MACDATA) ; 426 427 /* 428 * Read cpHold bit in pmbar, if cleared we have got Flashrom on board. 429 * If not, we need to upload the microcode to the card 430 */ 431 432 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD); 433 434#if XL_DEBUG 435 printk(KERN_INFO "Read from PMBAR = %04x \n", readw(xl_mmio + MMIO_MACDATA)) ; 436#endif 437 438 if ( readw( (xl_mmio + MMIO_MACDATA)) & PMB_CPHOLD ) { 439 440 /* Set PmBar, privateMemoryBase bits (8:2) to 0 */ 441 442 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD); 443 result_16 = readw(xl_mmio + MMIO_MACDATA) ; 444 result_16 = result_16 & ~((0x7F) << 2) ; 445 writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 446 writew(result_16,xl_mmio + MMIO_MACDATA) ; 447 448 /* Set CPAttention, memWrEn bit */ 449 450 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 451 result_8 = readb(xl_mmio + MMIO_MACDATA) ; 452 result_8 = result_8 | CPA_MEMWREN ; 453 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 454 writeb(result_8, xl_mmio + MMIO_MACDATA) ; 455 456 /* 457 * Now to write the microcode into the shared ram 458 * The microcode must finish at position 0xFFFF, so we must subtract 459 * to get the start position for the code 460 */ 461 462 start = (0xFFFF - (mc_size) + 1 ) ; /* Looks strange but ensures compiler only uses 16 bit unsigned int for this */ 463 464 printk(KERN_INFO "3C359: Uploading Microcode: "); 465 466 for (i = start, j = 0; j < mc_size; i++, j++) { 467 writel(MEM_BYTE_WRITE | 0XD0000 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 468 writeb(microcode[j],xl_mmio + MMIO_MACDATA) ; 469 if (j % 1024 == 0) 470 printk("."); 471 } 472 printk("\n") ; 473 474 for (i=0;i < 16; i++) { 475 writel( (MEM_BYTE_WRITE | 0xDFFF0) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 476 writeb(microcode[mc_size - 16 + i], xl_mmio + MMIO_MACDATA) ; 477 } 478 479 /* 480 * Have to write the start address of the upload to FFF4, but 481 * the address must be >> 4. You do not want to know how long 482 * it took me to discover this. 483 */ 484 485 writel(MEM_WORD_WRITE | 0xDFFF4, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 486 writew(start >> 4, xl_mmio + MMIO_MACDATA); 487 488 /* Clear the CPAttention, memWrEn Bit */ 489 490 writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 491 result_8 = readb(xl_mmio + MMIO_MACDATA) ; 492 result_8 = result_8 & ~CPA_MEMWREN ; 493 writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 494 writeb(result_8, xl_mmio + MMIO_MACDATA) ; 495 496 /* Clear the cpHold bit in pmbar */ 497 498 writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD); 499 result_16 = readw(xl_mmio + MMIO_MACDATA) ; 500 result_16 = result_16 & ~PMB_CPHOLD ; 501 writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 502 writew(result_16,xl_mmio + MMIO_MACDATA) ; 503 504 505 } /* If microcode upload required */ 506 507 /* 508 * The card should now go though a self test procedure and get itself ready 509 * to be opened, we must wait for an srb response with the initialization 510 * information. 511 */ 512 513#if XL_DEBUG 514 printk(KERN_INFO "%s: Microcode uploaded, must wait for the self test to complete\n", dev->name); 515#endif 516 517 writew(SETINDENABLE | 0xFFF, xl_mmio + MMIO_COMMAND) ; 518 519 t=jiffies; 520 while ( !(readw(xl_mmio + MMIO_INTSTATUS_AUTO) & INTSTAT_SRB) ) { 521 schedule(); 522 if(jiffies-t > 15*HZ) { 523 printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n"); 524 return -ENODEV; 525 } 526 } 527 528 /* 529 * Write the RxBufArea with D000, RxEarlyThresh, TxStartThresh, 530 * DnPriReqThresh, read the tech docs if you want to know what 531 * values they need to be. 532 */ 533 534 writel(MMIO_WORD_WRITE | RXBUFAREA, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 535 writew(0xD000, xl_mmio + MMIO_MACDATA) ; 536 537 writel(MMIO_WORD_WRITE | RXEARLYTHRESH, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 538 writew(0X0020, xl_mmio + MMIO_MACDATA) ; 539 540 writew( SETTXSTARTTHRESH | 0x40 , xl_mmio + MMIO_COMMAND) ; 541 542 writeb(0x04, xl_mmio + MMIO_DNBURSTTHRESH) ; 543 writeb(0x04, xl_mmio + DNPRIREQTHRESH) ; 544 545 /* 546 * Read WRBR to provide the location of the srb block, have to use byte reads not word reads. 547 * Tech docs have this wrong !!!! 548 */ 549 550 writel(MMIO_BYTE_READ | WRBR, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 551 xl_priv->srb = readb(xl_mmio + MMIO_MACDATA) << 8 ; 552 writel( (MMIO_BYTE_READ | WRBR) + 1, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 553 xl_priv->srb = xl_priv->srb | readb(xl_mmio + MMIO_MACDATA) ; 554 555#if XL_DEBUG 556 writel(IO_WORD_READ | SWITCHSETTINGS, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 557 if ( readw(xl_mmio + MMIO_MACDATA) & 2) { 558 printk(KERN_INFO "Default ring speed 4 mbps \n") ; 559 } else { 560 printk(KERN_INFO "Default ring speed 16 mbps \n") ; 561 } 562 printk(KERN_INFO "%s: xl_priv->srb = %04x\n",xl_priv->xl_card_name, xl_priv->srb); 563#endif 564 565 return 0; 566} 567 568static int xl_open(struct net_device *dev) 569{ 570 struct xl_private *xl_priv=netdev_priv(dev); 571 u8 __iomem *xl_mmio = xl_priv->xl_mmio ; 572 u8 i ; 573 __le16 hwaddr[3] ; /* Should be u8[6] but we get word return values */ 574 int open_err ; 575 576 u16 switchsettings, switchsettings_eeprom ; 577 578 if(request_irq(dev->irq, &xl_interrupt, IRQF_SHARED , "3c359", dev)) { 579 return -EAGAIN; 580 } 581 582 /* 583 * Read the information from the EEPROM that we need. 584 */ 585 586 hwaddr[0] = cpu_to_le16(xl_ee_read(dev,0x10)); 587 hwaddr[1] = cpu_to_le16(xl_ee_read(dev,0x11)); 588 hwaddr[2] = cpu_to_le16(xl_ee_read(dev,0x12)); 589 590 /* Ring speed */ 591 592 switchsettings_eeprom = xl_ee_read(dev,0x08) ; 593 switchsettings = switchsettings_eeprom ; 594 595 if (xl_priv->xl_ring_speed != 0) { 596 if (xl_priv->xl_ring_speed == 4) 597 switchsettings = switchsettings | 0x02 ; 598 else 599 switchsettings = switchsettings & ~0x02 ; 600 } 601 602 /* Only write EEProm if there has been a change */ 603 if (switchsettings != switchsettings_eeprom) { 604 xl_ee_write(dev,0x08,switchsettings) ; 605 /* Hardware reset after changing EEProm */ 606 xl_hw_reset(dev) ; 607 } 608 609 memcpy(dev->dev_addr,hwaddr,dev->addr_len) ; 610 611 open_err = xl_open_hw(dev) ; 612 613 /* 614 * This really needs to be cleaned up with better error reporting. 615 */ 616 617 if (open_err != 0) { /* Something went wrong with the open command */ 618 if (open_err & 0x07) { /* Wrong speed, retry at different speed */ 619 printk(KERN_WARNING "%s: Open Error, retrying at different ringspeed \n", dev->name) ; 620 switchsettings = switchsettings ^ 2 ; 621 xl_ee_write(dev,0x08,switchsettings) ; 622 xl_hw_reset(dev) ; 623 open_err = xl_open_hw(dev) ; 624 if (open_err != 0) { 625 printk(KERN_WARNING "%s: Open error returned a second time, we're bombing out now\n", dev->name); 626 free_irq(dev->irq,dev) ; 627 return -ENODEV ; 628 } 629 } else { 630 printk(KERN_WARNING "%s: Open Error = %04x\n", dev->name, open_err) ; 631 free_irq(dev->irq,dev) ; 632 return -ENODEV ; 633 } 634 } 635 636 /* 637 * Now to set up the Rx and Tx buffer structures 638 */ 639 /* These MUST be on 8 byte boundaries */ 640 xl_priv->xl_tx_ring = kzalloc((sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE) + 7, GFP_DMA | GFP_KERNEL); 641 if (xl_priv->xl_tx_ring == NULL) { 642 printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers.\n", 643 dev->name); 644 free_irq(dev->irq,dev); 645 return -ENOMEM; 646 } 647 xl_priv->xl_rx_ring = kzalloc((sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE) +7, GFP_DMA | GFP_KERNEL); 648 if (xl_priv->xl_tx_ring == NULL) { 649 printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers.\n", 650 dev->name); 651 free_irq(dev->irq,dev); 652 kfree(xl_priv->xl_tx_ring); 653 return -ENOMEM; 654 } 655 656 /* Setup Rx Ring */ 657 for (i=0 ; i < XL_RX_RING_SIZE ; i++) { 658 struct sk_buff *skb ; 659 660 skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ; 661 if (skb==NULL) 662 break ; 663 664 skb->dev = dev ; 665 xl_priv->xl_rx_ring[i].upfragaddr = cpu_to_le32(pci_map_single(xl_priv->pdev, skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE)); 666 xl_priv->xl_rx_ring[i].upfraglen = cpu_to_le32(xl_priv->pkt_buf_sz) | RXUPLASTFRAG; 667 xl_priv->rx_ring_skb[i] = skb ; 668 } 669 670 if (i==0) { 671 printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers. Adapter disabled \n",dev->name) ; 672 free_irq(dev->irq,dev) ; 673 return -EIO ; 674 } 675 676 xl_priv->rx_ring_no = i ; 677 xl_priv->rx_ring_tail = 0 ; 678 xl_priv->rx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_rx_ring, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_TODEVICE) ; 679 for (i=0;i<(xl_priv->rx_ring_no-1);i++) { 680 xl_priv->xl_rx_ring[i].upnextptr = cpu_to_le32(xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * (i+1))); 681 } 682 xl_priv->xl_rx_ring[i].upnextptr = 0 ; 683 684 writel(xl_priv->rx_ring_dma_addr, xl_mmio + MMIO_UPLISTPTR) ; 685 686 /* Setup Tx Ring */ 687 688 xl_priv->tx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_tx_ring, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE,PCI_DMA_TODEVICE) ; 689 690 xl_priv->tx_ring_head = 1 ; 691 xl_priv->tx_ring_tail = 255 ; /* Special marker for first packet */ 692 xl_priv->free_ring_entries = XL_TX_RING_SIZE ; 693 694 /* 695 * Setup the first dummy DPD entry for polling to start working. 696 */ 697 698 xl_priv->xl_tx_ring[0].framestartheader = TXDPDEMPTY; 699 xl_priv->xl_tx_ring[0].buffer = 0 ; 700 xl_priv->xl_tx_ring[0].buffer_length = 0 ; 701 xl_priv->xl_tx_ring[0].dnnextptr = 0 ; 702 703 writel(xl_priv->tx_ring_dma_addr, xl_mmio + MMIO_DNLISTPTR) ; 704 writel(DNUNSTALL, xl_mmio + MMIO_COMMAND) ; 705 writel(UPUNSTALL, xl_mmio + MMIO_COMMAND) ; 706 writel(DNENABLE, xl_mmio + MMIO_COMMAND) ; 707 writeb(0x40, xl_mmio + MMIO_DNPOLL) ; 708 709 /* 710 * Enable interrupts on the card 711 */ 712 713 writel(SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ; 714 writel(SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ; 715 716 netif_start_queue(dev) ; 717 return 0; 718 719} 720 721static int xl_open_hw(struct net_device *dev) 722{ 723 struct xl_private *xl_priv=netdev_priv(dev); 724 u8 __iomem *xl_mmio = xl_priv->xl_mmio ; 725 u16 vsoff ; 726 char ver_str[33]; 727 int open_err ; 728 int i ; 729 unsigned long t ; 730 731 /* 732 * Okay, let's build up the Open.NIC srb command 733 * 734 */ 735 736 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 737 writeb(OPEN_NIC, xl_mmio + MMIO_MACDATA) ; 738 739 /* 740 * Use this as a test byte, if it comes back with the same value, the command didn't work 741 */ 742 743 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb)+ 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 744 writeb(0xff,xl_mmio + MMIO_MACDATA) ; 745 746 /* Open options */ 747 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 748 writeb(0x00, xl_mmio + MMIO_MACDATA) ; 749 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 9, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 750 writeb(0x00, xl_mmio + MMIO_MACDATA) ; 751 752 /* 753 * Node address, be careful here, the docs say you can just put zeros here and it will use 754 * the hardware address, it doesn't, you must include the node address in the open command. 755 */ 756 757 if (xl_priv->xl_laa[0]) { /* If using a LAA address */ 758 for (i=10;i<16;i++) { 759 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 760 writeb(xl_priv->xl_laa[i-10],xl_mmio + MMIO_MACDATA) ; 761 } 762 memcpy(dev->dev_addr,xl_priv->xl_laa,dev->addr_len) ; 763 } else { /* Regular hardware address */ 764 for (i=10;i<16;i++) { 765 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 766 writeb(dev->dev_addr[i-10], xl_mmio + MMIO_MACDATA) ; 767 } 768 } 769 770 /* Default everything else to 0 */ 771 for (i = 16; i < 34; i++) { 772 writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 773 writeb(0x00,xl_mmio + MMIO_MACDATA) ; 774 } 775 776 /* 777 * Set the csrb bit in the MISR register 778 */ 779 780 xl_wait_misr_flags(dev) ; 781 writel(MEM_BYTE_WRITE | MF_CSRB, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 782 writeb(0xFF, xl_mmio + MMIO_MACDATA) ; 783 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 784 writeb(MISR_CSRB , xl_mmio + MMIO_MACDATA) ; 785 786 /* 787 * Now wait for the command to run 788 */ 789 790 t=jiffies; 791 while (! (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) { 792 schedule(); 793 if(jiffies-t > 40*HZ) { 794 printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n"); 795 break ; 796 } 797 } 798 799 /* 800 * Let's interpret the open response 801 */ 802 803 writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb)+2, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 804 if (readb(xl_mmio + MMIO_MACDATA)!=0) { 805 open_err = readb(xl_mmio + MMIO_MACDATA) << 8 ; 806 writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb) + 7, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 807 open_err |= readb(xl_mmio + MMIO_MACDATA) ; 808 return open_err ; 809 } else { 810 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 811 xl_priv->asb = swab16(readw(xl_mmio + MMIO_MACDATA)) ; 812 printk(KERN_INFO "%s: Adapter Opened Details: ",dev->name) ; 813 printk("ASB: %04x",xl_priv->asb ) ; 814 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 10, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 815 printk(", SRB: %04x",swab16(readw(xl_mmio + MMIO_MACDATA)) ) ; 816 817 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 12, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 818 xl_priv->arb = swab16(readw(xl_mmio + MMIO_MACDATA)) ; 819 printk(", ARB: %04x \n",xl_priv->arb ) ; 820 writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 14, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 821 vsoff = swab16(readw(xl_mmio + MMIO_MACDATA)) ; 822 823 /* 824 * Interesting, sending the individual characters directly to printk was causing klogd to use 825 * use 100% of processor time, so we build up the string and print that instead. 826 */ 827 828 for (i=0;i<0x20;i++) { 829 writel( (MEM_BYTE_READ | 0xD0000 | vsoff) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 830 ver_str[i] = readb(xl_mmio + MMIO_MACDATA) ; 831 } 832 ver_str[i] = '\0' ; 833 printk(KERN_INFO "%s: Microcode version String: %s \n",dev->name,ver_str); 834 } 835 836 /* 837 * Issue the AckInterrupt 838 */ 839 writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; 840 841 return 0 ; 842} 843 844/* 845 * There are two ways of implementing rx on the 359 NIC, either 846 * interrupt driven or polling. We are going to uses interrupts, 847 * it is the easier way of doing things. 848 * 849 * The Rx works with a ring of Rx descriptors. At initialise time the ring 850 * entries point to the next entry except for the last entry in the ring 851 * which points to 0. The card is programmed with the location of the first 852 * available descriptor and keeps reading the next_ptr until next_ptr is set 853 * to 0. Hopefully with a ring size of 16 the card will never get to read a next_ptr 854 * of 0. As the Rx interrupt is received we copy the frame up to the protocol layers 855 * and then point the end of the ring to our current position and point our current 856 * position to 0, therefore making the current position the last position on the ring. 857 * The last position on the ring therefore loops continually loops around the rx ring. 858 * 859 * rx_ring_tail is the position on the ring to process next. (Think of a snake, the head 860 * expands as the card adds new packets and we go around eating the tail processing the 861 * packets.) 862 * 863 * Undoubtably it could be streamlined and improved upon, but at the moment it works 864 * and the fast path through the routine is fine. 865 * 866 * adv_rx_ring could be inlined to increase performance, but its called a *lot* of times 867 * in xl_rx so would increase the size of the function significantly. 868 */ 869 870static void adv_rx_ring(struct net_device *dev) /* Advance rx_ring, cut down on bloat in xl_rx */ 871{ 872 struct xl_private *xl_priv=netdev_priv(dev); 873 int n = xl_priv->rx_ring_tail; 874 int prev_ring_loc; 875 876 prev_ring_loc = (n + XL_RX_RING_SIZE - 1) & (XL_RX_RING_SIZE - 1); 877 xl_priv->xl_rx_ring[prev_ring_loc].upnextptr = cpu_to_le32(xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * n)); 878 xl_priv->xl_rx_ring[n].framestatus = 0; 879 xl_priv->xl_rx_ring[n].upnextptr = 0; 880 xl_priv->rx_ring_tail++; 881 xl_priv->rx_ring_tail &= (XL_RX_RING_SIZE-1); 882} 883 884static void xl_rx(struct net_device *dev) 885{ 886 struct xl_private *xl_priv=netdev_priv(dev); 887 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 888 struct sk_buff *skb, *skb2 ; 889 int frame_length = 0, copy_len = 0 ; 890 int temp_ring_loc ; 891 892 /* 893 * Receive the next frame, loop around the ring until all frames 894 * have been received. 895 */ 896 897 while (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & (RXUPDCOMPLETE | RXUPDFULL) ) { /* Descriptor to process */ 898 899 if (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & RXUPDFULL ) { /* UpdFull, Multiple Descriptors used for the frame */ 900 901 /* 902 * This is a pain, you need to go through all the descriptors until the last one 903 * for this frame to find the framelength 904 */ 905 906 temp_ring_loc = xl_priv->rx_ring_tail ; 907 908 while (xl_priv->xl_rx_ring[temp_ring_loc].framestatus & RXUPDFULL ) { 909 temp_ring_loc++ ; 910 temp_ring_loc &= (XL_RX_RING_SIZE-1) ; 911 } 912 913 frame_length = le32_to_cpu(xl_priv->xl_rx_ring[temp_ring_loc].framestatus) & 0x7FFF; 914 915 skb = dev_alloc_skb(frame_length) ; 916 917 if (skb==NULL) { /* No memory for frame, still need to roll forward the rx ring */ 918 printk(KERN_WARNING "%s: dev_alloc_skb failed - multi buffer !\n", dev->name) ; 919 while (xl_priv->rx_ring_tail != temp_ring_loc) 920 adv_rx_ring(dev) ; 921 922 adv_rx_ring(dev) ; /* One more time just for luck :) */ 923 xl_priv->xl_stats.rx_dropped++ ; 924 925 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ; 926 return ; 927 } 928 929 while (xl_priv->rx_ring_tail != temp_ring_loc) { 930 copy_len = le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen) & 0x7FFF; 931 frame_length -= copy_len ; 932 pci_dma_sync_single_for_cpu(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE); 933 skb_copy_from_linear_data(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail], 934 skb_put(skb, copy_len), 935 copy_len); 936 pci_dma_sync_single_for_device(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE); 937 adv_rx_ring(dev) ; 938 } 939 940 /* Now we have found the last fragment */ 941 pci_dma_sync_single_for_cpu(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE); 942 skb_copy_from_linear_data(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail], 943 skb_put(skb,copy_len), frame_length); 944/* memcpy(skb_put(skb,frame_length), bus_to_virt(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), frame_length) ; */ 945 pci_dma_sync_single_for_device(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE); 946 adv_rx_ring(dev) ; 947 skb->protocol = tr_type_trans(skb,dev) ; 948 netif_rx(skb) ; 949 950 } else { /* Single Descriptor Used, simply swap buffers over, fast path */ 951 952 frame_length = le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus) & 0x7FFF; 953 954 skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ; 955 956 if (skb==NULL) { /* Still need to fix the rx ring */ 957 printk(KERN_WARNING "%s: dev_alloc_skb failed in rx, single buffer \n",dev->name) ; 958 adv_rx_ring(dev) ; 959 xl_priv->xl_stats.rx_dropped++ ; 960 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ; 961 return ; 962 } 963 964 skb2 = xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] ; 965 pci_unmap_single(xl_priv->pdev, le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ; 966 skb_put(skb2, frame_length) ; 967 skb2->protocol = tr_type_trans(skb2,dev) ; 968 969 xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] = skb ; 970 xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr = cpu_to_le32(pci_map_single(xl_priv->pdev,skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE)); 971 xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen = cpu_to_le32(xl_priv->pkt_buf_sz) | RXUPLASTFRAG; 972 adv_rx_ring(dev) ; 973 xl_priv->xl_stats.rx_packets++ ; 974 xl_priv->xl_stats.rx_bytes += frame_length ; 975 976 netif_rx(skb2) ; 977 } /* if multiple buffers */ 978 dev->last_rx = jiffies ; 979 } /* while packet to do */ 980 981 /* Clear the updComplete interrupt */ 982 writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ; 983 return ; 984} 985 986/* 987 * This is ruthless, it doesn't care what state the card is in it will 988 * completely reset the adapter. 989 */ 990 991static void xl_reset(struct net_device *dev) 992{ 993 struct xl_private *xl_priv=netdev_priv(dev); 994 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 995 unsigned long t; 996 997 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ; 998 999 /* 1000 * Must wait for cmdInProgress bit (12) to clear before continuing with 1001 * card configuration. 1002 */ 1003 1004 t=jiffies; 1005 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { 1006 if(jiffies-t > 40*HZ) { 1007 printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n"); 1008 break ; 1009 } 1010 } 1011 1012} 1013 1014static void xl_freemem(struct net_device *dev) 1015{ 1016 struct xl_private *xl_priv=netdev_priv(dev); 1017 int i ; 1018 1019 for (i=0;i<XL_RX_RING_SIZE;i++) { 1020 dev_kfree_skb_irq(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail]) ; 1021 pci_unmap_single(xl_priv->pdev,le32_to_cpu(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr),xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE); 1022 xl_priv->rx_ring_tail++ ; 1023 xl_priv->rx_ring_tail &= XL_RX_RING_SIZE-1; 1024 } 1025 1026 /* unmap ring */ 1027 pci_unmap_single(xl_priv->pdev,xl_priv->rx_ring_dma_addr, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_FROMDEVICE) ; 1028 1029 pci_unmap_single(xl_priv->pdev,xl_priv->tx_ring_dma_addr, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE, PCI_DMA_TODEVICE) ; 1030 1031 kfree(xl_priv->xl_rx_ring) ; 1032 kfree(xl_priv->xl_tx_ring) ; 1033 1034 return ; 1035} 1036 1037static irqreturn_t xl_interrupt(int irq, void *dev_id) 1038{ 1039 struct net_device *dev = (struct net_device *)dev_id; 1040 struct xl_private *xl_priv =netdev_priv(dev); 1041 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 1042 u16 intstatus, macstatus ; 1043 1044 intstatus = readw(xl_mmio + MMIO_INTSTATUS) ; 1045 1046 if (!(intstatus & 1)) /* We didn't generate the interrupt */ 1047 return IRQ_NONE; 1048 1049 spin_lock(&xl_priv->xl_lock) ; 1050 1051 /* 1052 * Process the interrupt 1053 */ 1054 /* 1055 * Something fishy going on here, we shouldn't get 0001 ints, not fatal though. 1056 */ 1057 if (intstatus == 0x0001) { 1058 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; 1059 printk(KERN_INFO "%s: 00001 int received \n",dev->name) ; 1060 } else { 1061 if (intstatus & (HOSTERRINT | SRBRINT | ARBCINT | UPCOMPINT | DNCOMPINT | HARDERRINT | (1<<8) | TXUNDERRUN | ASBFINT)) { 1062 1063 /* 1064 * Host Error. 1065 * It may be possible to recover from this, but usually it means something 1066 * is seriously fubar, so we just close the adapter. 1067 */ 1068 1069 if (intstatus & HOSTERRINT) { 1070 printk(KERN_WARNING "%s: Host Error, performing global reset, intstatus = %04x \n",dev->name,intstatus) ; 1071 writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ; 1072 printk(KERN_WARNING "%s: Resetting hardware: \n", dev->name); 1073 netif_stop_queue(dev) ; 1074 xl_freemem(dev) ; 1075 free_irq(dev->irq,dev); 1076 xl_reset(dev) ; 1077 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; 1078 spin_unlock(&xl_priv->xl_lock) ; 1079 return IRQ_HANDLED; 1080 } /* Host Error */ 1081 1082 if (intstatus & SRBRINT ) { /* Srbc interrupt */ 1083 writel(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; 1084 if (xl_priv->srb_queued) 1085 xl_srb_bh(dev) ; 1086 } /* SRBR Interrupt */ 1087 1088 if (intstatus & TXUNDERRUN) { /* Issue DnReset command */ 1089 writel(DNRESET, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1090 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { /* Wait for command to run */ 1091 /* !!! FIX-ME !!!! 1092 Must put a timeout check here ! */ 1093 /* Empty Loop */ 1094 } 1095 printk(KERN_WARNING "%s: TX Underrun received \n",dev->name) ; 1096 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; 1097 } /* TxUnderRun */ 1098 1099 if (intstatus & ARBCINT ) { /* Arbc interrupt */ 1100 xl_arb_cmd(dev) ; 1101 } /* Arbc */ 1102 1103 if (intstatus & ASBFINT) { 1104 if (xl_priv->asb_queued == 1) { 1105 xl_asb_cmd(dev) ; 1106 } else if (xl_priv->asb_queued == 2) { 1107 xl_asb_bh(dev) ; 1108 } else { 1109 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ; 1110 } 1111 } /* Asbf */ 1112 1113 if (intstatus & UPCOMPINT ) /* UpComplete */ 1114 xl_rx(dev) ; 1115 1116 if (intstatus & DNCOMPINT ) /* DnComplete */ 1117 xl_dn_comp(dev) ; 1118 1119 if (intstatus & HARDERRINT ) { /* Hardware error */ 1120 writel(MMIO_WORD_READ | MACSTATUS, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1121 macstatus = readw(xl_mmio + MMIO_MACDATA) ; 1122 printk(KERN_WARNING "%s: MacStatusError, details: ", dev->name); 1123 if (macstatus & (1<<14)) 1124 printk(KERN_WARNING "tchk error: Unrecoverable error \n") ; 1125 if (macstatus & (1<<3)) 1126 printk(KERN_WARNING "eint error: Internal watchdog timer expired \n") ; 1127 if (macstatus & (1<<2)) 1128 printk(KERN_WARNING "aint error: Host tried to perform invalid operation \n") ; 1129 printk(KERN_WARNING "Instatus = %02x, macstatus = %02x\n",intstatus,macstatus) ; 1130 printk(KERN_WARNING "%s: Resetting hardware: \n", dev->name); 1131 netif_stop_queue(dev) ; 1132 xl_freemem(dev) ; 1133 free_irq(dev->irq,dev); 1134 unregister_netdev(dev) ; 1135 free_netdev(dev) ; 1136 xl_reset(dev) ; 1137 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; 1138 spin_unlock(&xl_priv->xl_lock) ; 1139 return IRQ_HANDLED; 1140 } 1141 } else { 1142 printk(KERN_WARNING "%s: Received Unknown interrupt : %04x \n", dev->name, intstatus) ; 1143 writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; 1144 } 1145 } 1146 1147 /* Turn interrupts back on */ 1148 1149 writel( SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ; 1150 writel( SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ; 1151 1152 spin_unlock(&xl_priv->xl_lock) ; 1153 return IRQ_HANDLED; 1154} 1155 1156/* 1157 * Tx - Polling configuration 1158 */ 1159 1160static int xl_xmit(struct sk_buff *skb, struct net_device *dev) 1161{ 1162 struct xl_private *xl_priv=netdev_priv(dev); 1163 struct xl_tx_desc *txd ; 1164 int tx_head, tx_tail, tx_prev ; 1165 unsigned long flags ; 1166 1167 spin_lock_irqsave(&xl_priv->xl_lock,flags) ; 1168 1169 netif_stop_queue(dev) ; 1170 1171 if (xl_priv->free_ring_entries > 1 ) { 1172 /* 1173 * Set up the descriptor for the packet 1174 */ 1175 tx_head = xl_priv->tx_ring_head ; 1176 tx_tail = xl_priv->tx_ring_tail ; 1177 1178 txd = &(xl_priv->xl_tx_ring[tx_head]) ; 1179 txd->dnnextptr = 0 ; 1180 txd->framestartheader = cpu_to_le32(skb->len) | TXDNINDICATE; 1181 txd->buffer = cpu_to_le32(pci_map_single(xl_priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE)); 1182 txd->buffer_length = cpu_to_le32(skb->len) | TXDNFRAGLAST; 1183 xl_priv->tx_ring_skb[tx_head] = skb ; 1184 xl_priv->xl_stats.tx_packets++ ; 1185 xl_priv->xl_stats.tx_bytes += skb->len ; 1186 1187 /* 1188 * Set the nextptr of the previous descriptor equal to this descriptor, add XL_TX_RING_SIZE -1 1189 * to ensure no negative numbers in unsigned locations. 1190 */ 1191 1192 tx_prev = (xl_priv->tx_ring_head + XL_TX_RING_SIZE - 1) & (XL_TX_RING_SIZE - 1) ; 1193 1194 xl_priv->tx_ring_head++ ; 1195 xl_priv->tx_ring_head &= (XL_TX_RING_SIZE - 1) ; 1196 xl_priv->free_ring_entries-- ; 1197 1198 xl_priv->xl_tx_ring[tx_prev].dnnextptr = cpu_to_le32(xl_priv->tx_ring_dma_addr + (sizeof (struct xl_tx_desc) * tx_head)); 1199 1200 /* Sneaky, by doing a read on DnListPtr we can force the card to poll on the DnNextPtr */ 1201 /* readl(xl_mmio + MMIO_DNLISTPTR) ; */ 1202 1203 netif_wake_queue(dev) ; 1204 1205 spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ; 1206 1207 return 0; 1208 } else { 1209 spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ; 1210 return 1; 1211 } 1212 1213} 1214 1215/* 1216 * The NIC has told us that a packet has been downloaded onto the card, we must 1217 * find out which packet it has done, clear the skb and information for the packet 1218 * then advance around the ring for all tranmitted packets 1219 */ 1220 1221static void xl_dn_comp(struct net_device *dev) 1222{ 1223 struct xl_private *xl_priv=netdev_priv(dev); 1224 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 1225 struct xl_tx_desc *txd ; 1226 1227 1228 if (xl_priv->tx_ring_tail == 255) {/* First time */ 1229 xl_priv->xl_tx_ring[0].framestartheader = 0 ; 1230 xl_priv->xl_tx_ring[0].dnnextptr = 0 ; 1231 xl_priv->tx_ring_tail = 1 ; 1232 } 1233 1234 while (xl_priv->xl_tx_ring[xl_priv->tx_ring_tail].framestartheader & TXDNCOMPLETE ) { 1235 txd = &(xl_priv->xl_tx_ring[xl_priv->tx_ring_tail]) ; 1236 pci_unmap_single(xl_priv->pdev, le32_to_cpu(txd->buffer), xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]->len, PCI_DMA_TODEVICE); 1237 txd->framestartheader = 0 ; 1238 txd->buffer = cpu_to_le32(0xdeadbeef); 1239 txd->buffer_length = 0 ; 1240 dev_kfree_skb_irq(xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]) ; 1241 xl_priv->tx_ring_tail++ ; 1242 xl_priv->tx_ring_tail &= (XL_TX_RING_SIZE - 1) ; 1243 xl_priv->free_ring_entries++ ; 1244 } 1245 1246 netif_wake_queue(dev) ; 1247 1248 writel(ACK_INTERRUPT | DNCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ; 1249} 1250 1251/* 1252 * Close the adapter properly. 1253 * This srb reply cannot be handled from interrupt context as we have 1254 * to free the interrupt from the driver. 1255 */ 1256 1257static int xl_close(struct net_device *dev) 1258{ 1259 struct xl_private *xl_priv = netdev_priv(dev); 1260 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 1261 unsigned long t ; 1262 1263 netif_stop_queue(dev) ; 1264 1265 /* 1266 * Close the adapter, need to stall the rx and tx queues. 1267 */ 1268 1269 writew(DNSTALL, xl_mmio + MMIO_COMMAND) ; 1270 t=jiffies; 1271 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { 1272 schedule(); 1273 if(jiffies-t > 10*HZ) { 1274 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNSTALL not responding.\n", dev->name); 1275 break ; 1276 } 1277 } 1278 writew(DNDISABLE, xl_mmio + MMIO_COMMAND) ; 1279 t=jiffies; 1280 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { 1281 schedule(); 1282 if(jiffies-t > 10*HZ) { 1283 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNDISABLE not responding.\n", dev->name); 1284 break ; 1285 } 1286 } 1287 writew(UPSTALL, xl_mmio + MMIO_COMMAND) ; 1288 t=jiffies; 1289 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { 1290 schedule(); 1291 if(jiffies-t > 10*HZ) { 1292 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPSTALL not responding.\n", dev->name); 1293 break ; 1294 } 1295 } 1296 1297 /* Turn off interrupts, we will still get the indication though 1298 * so we can trap it 1299 */ 1300 1301 writel(SETINTENABLE, xl_mmio + MMIO_COMMAND) ; 1302 1303 xl_srb_cmd(dev,CLOSE_NIC) ; 1304 1305 t=jiffies; 1306 while (!(readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) { 1307 schedule(); 1308 if(jiffies-t > 10*HZ) { 1309 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-CLOSENIC not responding.\n", dev->name); 1310 break ; 1311 } 1312 } 1313 /* Read the srb response from the adapter */ 1314 1315 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD); 1316 if (readb(xl_mmio + MMIO_MACDATA) != CLOSE_NIC) { 1317 printk(KERN_INFO "%s: CLOSE_NIC did not get a CLOSE_NIC response \n",dev->name) ; 1318 } else { 1319 writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1320 if (readb(xl_mmio + MMIO_MACDATA)==0) { 1321 printk(KERN_INFO "%s: Adapter has been closed \n",dev->name) ; 1322 writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; 1323 1324 xl_freemem(dev) ; 1325 free_irq(dev->irq,dev) ; 1326 } else { 1327 printk(KERN_INFO "%s: Close nic command returned error code %02x\n",dev->name, readb(xl_mmio + MMIO_MACDATA)) ; 1328 } 1329 } 1330 1331 /* Reset the upload and download logic */ 1332 1333 writew(UPRESET, xl_mmio + MMIO_COMMAND) ; 1334 t=jiffies; 1335 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { 1336 schedule(); 1337 if(jiffies-t > 10*HZ) { 1338 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPRESET not responding.\n", dev->name); 1339 break ; 1340 } 1341 } 1342 writew(DNRESET, xl_mmio + MMIO_COMMAND) ; 1343 t=jiffies; 1344 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { 1345 schedule(); 1346 if(jiffies-t > 10*HZ) { 1347 printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNRESET not responding.\n", dev->name); 1348 break ; 1349 } 1350 } 1351 xl_hw_reset(dev) ; 1352 return 0 ; 1353} 1354 1355static void xl_set_rx_mode(struct net_device *dev) 1356{ 1357 struct xl_private *xl_priv = netdev_priv(dev); 1358 struct dev_mc_list *dmi ; 1359 unsigned char dev_mc_address[4] ; 1360 u16 options ; 1361 int i ; 1362 1363 if (dev->flags & IFF_PROMISC) 1364 options = 0x0004 ; 1365 else 1366 options = 0x0000 ; 1367 1368 if (options ^ xl_priv->xl_copy_all_options) { /* Changed, must send command */ 1369 xl_priv->xl_copy_all_options = options ; 1370 xl_srb_cmd(dev, SET_RECEIVE_MODE) ; 1371 return ; 1372 } 1373 1374 dev_mc_address[0] = dev_mc_address[1] = dev_mc_address[2] = dev_mc_address[3] = 0 ; 1375 1376 for (i=0,dmi=dev->mc_list;i < dev->mc_count; i++,dmi = dmi->next) { 1377 dev_mc_address[0] |= dmi->dmi_addr[2] ; 1378 dev_mc_address[1] |= dmi->dmi_addr[3] ; 1379 dev_mc_address[2] |= dmi->dmi_addr[4] ; 1380 dev_mc_address[3] |= dmi->dmi_addr[5] ; 1381 } 1382 1383 if (memcmp(xl_priv->xl_functional_addr,dev_mc_address,4) != 0) { /* Options have changed, run the command */ 1384 memcpy(xl_priv->xl_functional_addr, dev_mc_address,4) ; 1385 xl_srb_cmd(dev, SET_FUNC_ADDRESS) ; 1386 } 1387 return ; 1388} 1389 1390 1391/* 1392 * We issued an srb command and now we must read 1393 * the response from the completed command. 1394 */ 1395 1396static void xl_srb_bh(struct net_device *dev) 1397{ 1398 struct xl_private *xl_priv = netdev_priv(dev); 1399 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 1400 u8 srb_cmd, ret_code ; 1401 int i ; 1402 1403 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1404 srb_cmd = readb(xl_mmio + MMIO_MACDATA) ; 1405 writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1406 ret_code = readb(xl_mmio + MMIO_MACDATA) ; 1407 1408 /* Ret_code is standard across all commands */ 1409 1410 switch (ret_code) { 1411 case 1: 1412 printk(KERN_INFO "%s: Command: %d - Invalid Command code\n",dev->name,srb_cmd) ; 1413 break ; 1414 case 4: 1415 printk(KERN_INFO "%s: Command: %d - Adapter is closed, must be open for this command \n",dev->name,srb_cmd) ; 1416 break ; 1417 1418 case 6: 1419 printk(KERN_INFO "%s: Command: %d - Options Invalid for command \n",dev->name,srb_cmd) ; 1420 break ; 1421 1422 case 0: /* Successful command execution */ 1423 switch (srb_cmd) { 1424 case READ_LOG: /* Returns 14 bytes of data from the NIC */ 1425 if(xl_priv->xl_message_level) 1426 printk(KERN_INFO "%s: READ.LOG 14 bytes of data ",dev->name) ; 1427 /* 1428 * We still have to read the log even if message_level = 0 and we don't want 1429 * to see it 1430 */ 1431 for (i=0;i<14;i++) { 1432 writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1433 if(xl_priv->xl_message_level) 1434 printk("%02x:",readb(xl_mmio + MMIO_MACDATA)) ; 1435 } 1436 printk("\n") ; 1437 break ; 1438 case SET_FUNC_ADDRESS: 1439 if(xl_priv->xl_message_level) 1440 printk(KERN_INFO "%s: Functional Address Set \n",dev->name) ; 1441 break ; 1442 case CLOSE_NIC: 1443 if(xl_priv->xl_message_level) 1444 printk(KERN_INFO "%s: Received CLOSE_NIC interrupt in interrupt handler \n",dev->name) ; 1445 break ; 1446 case SET_MULTICAST_MODE: 1447 if(xl_priv->xl_message_level) 1448 printk(KERN_INFO "%s: Multicast options successfully changed\n",dev->name) ; 1449 break ; 1450 case SET_RECEIVE_MODE: 1451 if(xl_priv->xl_message_level) { 1452 if (xl_priv->xl_copy_all_options == 0x0004) 1453 printk(KERN_INFO "%s: Entering promiscuous mode \n", dev->name) ; 1454 else 1455 printk(KERN_INFO "%s: Entering normal receive mode \n",dev->name) ; 1456 } 1457 break ; 1458 1459 } /* switch */ 1460 break ; 1461 } /* switch */ 1462 return ; 1463} 1464 1465static struct net_device_stats * xl_get_stats(struct net_device *dev) 1466{ 1467 struct xl_private *xl_priv = netdev_priv(dev); 1468 return (struct net_device_stats *) &xl_priv->xl_stats; 1469} 1470 1471static int xl_set_mac_address (struct net_device *dev, void *addr) 1472{ 1473 struct sockaddr *saddr = addr ; 1474 struct xl_private *xl_priv = netdev_priv(dev); 1475 1476 if (netif_running(dev)) { 1477 printk(KERN_WARNING "%s: Cannot set mac/laa address while card is open\n", dev->name) ; 1478 return -EIO ; 1479 } 1480 1481 memcpy(xl_priv->xl_laa, saddr->sa_data,dev->addr_len) ; 1482 1483 if (xl_priv->xl_message_level) { 1484 printk(KERN_INFO "%s: MAC/LAA Set to = %x.%x.%x.%x.%x.%x\n",dev->name, xl_priv->xl_laa[0], 1485 xl_priv->xl_laa[1], xl_priv->xl_laa[2], 1486 xl_priv->xl_laa[3], xl_priv->xl_laa[4], 1487 xl_priv->xl_laa[5]); 1488 } 1489 1490 return 0 ; 1491} 1492 1493static void xl_arb_cmd(struct net_device *dev) 1494{ 1495 struct xl_private *xl_priv = netdev_priv(dev); 1496 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 1497 u8 arb_cmd ; 1498 u16 lan_status, lan_status_diff ; 1499 1500 writel( ( MEM_BYTE_READ | 0xD0000 | xl_priv->arb), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1501 arb_cmd = readb(xl_mmio + MMIO_MACDATA) ; 1502 1503 if (arb_cmd == RING_STATUS_CHANGE) { /* Ring.Status.Change */ 1504 writel( ( (MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1505 1506 printk(KERN_INFO "%s: Ring Status Change: New Status = %04x\n", dev->name, swab16(readw(xl_mmio + MMIO_MACDATA) )) ; 1507 1508 lan_status = swab16(readw(xl_mmio + MMIO_MACDATA)); 1509 1510 /* Acknowledge interrupt, this tells nic we are done with the arb */ 1511 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; 1512 1513 lan_status_diff = xl_priv->xl_lan_status ^ lan_status ; 1514 1515 if (lan_status_diff & (LSC_LWF | LSC_ARW | LSC_FPE | LSC_RR) ) { 1516 if (lan_status_diff & LSC_LWF) 1517 printk(KERN_WARNING "%s: Short circuit detected on the lobe\n",dev->name); 1518 if (lan_status_diff & LSC_ARW) 1519 printk(KERN_WARNING "%s: Auto removal error\n",dev->name); 1520 if (lan_status_diff & LSC_FPE) 1521 printk(KERN_WARNING "%s: FDX Protocol Error\n",dev->name); 1522 if (lan_status_diff & LSC_RR) 1523 printk(KERN_WARNING "%s: Force remove MAC frame received\n",dev->name); 1524 1525 /* Adapter has been closed by the hardware */ 1526 1527 netif_stop_queue(dev); 1528 xl_freemem(dev) ; 1529 free_irq(dev->irq,dev); 1530 1531 printk(KERN_WARNING "%s: Adapter has been closed \n", dev->name) ; 1532 } /* If serious error */ 1533 1534 if (xl_priv->xl_message_level) { 1535 if (lan_status_diff & LSC_SIG_LOSS) 1536 printk(KERN_WARNING "%s: No receive signal detected \n", dev->name) ; 1537 if (lan_status_diff & LSC_HARD_ERR) 1538 printk(KERN_INFO "%s: Beaconing \n",dev->name); 1539 if (lan_status_diff & LSC_SOFT_ERR) 1540 printk(KERN_WARNING "%s: Adapter transmitted Soft Error Report Mac Frame \n",dev->name); 1541 if (lan_status_diff & LSC_TRAN_BCN) 1542 printk(KERN_INFO "%s: We are tranmitting the beacon, aaah\n",dev->name); 1543 if (lan_status_diff & LSC_SS) 1544 printk(KERN_INFO "%s: Single Station on the ring \n", dev->name); 1545 if (lan_status_diff & LSC_RING_REC) 1546 printk(KERN_INFO "%s: Ring recovery ongoing\n",dev->name); 1547 if (lan_status_diff & LSC_FDX_MODE) 1548 printk(KERN_INFO "%s: Operating in FDX mode\n",dev->name); 1549 } 1550 1551 if (lan_status_diff & LSC_CO) { 1552 if (xl_priv->xl_message_level) 1553 printk(KERN_INFO "%s: Counter Overflow \n", dev->name); 1554 /* Issue READ.LOG command */ 1555 xl_srb_cmd(dev, READ_LOG) ; 1556 } 1557 1558 /* There is no command in the tech docs to issue the read_sr_counters */ 1559 if (lan_status_diff & LSC_SR_CO) { 1560 if (xl_priv->xl_message_level) 1561 printk(KERN_INFO "%s: Source routing counters overflow\n", dev->name); 1562 } 1563 1564 xl_priv->xl_lan_status = lan_status ; 1565 1566 } /* Lan.change.status */ 1567 else if ( arb_cmd == RECEIVE_DATA) { /* Received.Data */ 1568#if XL_DEBUG 1569 printk(KERN_INFO "Received.Data \n") ; 1570#endif 1571 writel( ((MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1572 xl_priv->mac_buffer = swab16(readw(xl_mmio + MMIO_MACDATA)) ; 1573 1574 /* Now we are going to be really basic here and not do anything 1575 * with the data at all. The tech docs do not give me enough 1576 * information to calculate the buffers properly so we're 1577 * just going to tell the nic that we've dealt with the frame 1578 * anyway. 1579 */ 1580 1581 dev->last_rx = jiffies ; 1582 /* Acknowledge interrupt, this tells nic we are done with the arb */ 1583 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ; 1584 1585 /* Is the ASB free ? */ 1586 1587 xl_priv->asb_queued = 0 ; 1588 writel( ((MEM_BYTE_READ | 0xD0000 | xl_priv->asb) + 2), xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1589 if (readb(xl_mmio + MMIO_MACDATA) != 0xff) { 1590 xl_priv->asb_queued = 1 ; 1591 1592 xl_wait_misr_flags(dev) ; 1593 1594 writel(MEM_BYTE_WRITE | MF_ASBFR, xl_mmio + MMIO_MAC_ACCESS_CMD); 1595 writeb(0xff, xl_mmio + MMIO_MACDATA) ; 1596 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1597 writeb(MISR_ASBFR, xl_mmio + MMIO_MACDATA) ; 1598 return ; 1599 /* Drop out and wait for the bottom half to be run */ 1600 } 1601 1602 xl_asb_cmd(dev) ; 1603 1604 } else { 1605 printk(KERN_WARNING "%s: Received unknown arb (xl_priv) command: %02x \n",dev->name,arb_cmd) ; 1606 } 1607 1608 /* Acknowledge the arb interrupt */ 1609 1610 writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ; 1611 1612 return ; 1613} 1614 1615 1616/* 1617 * There is only one asb command, but we can get called from different 1618 * places. 1619 */ 1620 1621static void xl_asb_cmd(struct net_device *dev) 1622{ 1623 struct xl_private *xl_priv = netdev_priv(dev); 1624 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 1625 1626 if (xl_priv->asb_queued == 1) 1627 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ; 1628 1629 writel(MEM_BYTE_WRITE | 0xd0000 | xl_priv->asb, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1630 writeb(0x81, xl_mmio + MMIO_MACDATA) ; 1631 1632 writel(MEM_WORD_WRITE | 0xd0000 | xl_priv->asb | 6, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1633 writew(swab16(xl_priv->mac_buffer), xl_mmio + MMIO_MACDATA) ; 1634 1635 xl_wait_misr_flags(dev) ; 1636 1637 writel(MEM_BYTE_WRITE | MF_RASB, xl_mmio + MMIO_MAC_ACCESS_CMD); 1638 writeb(0xff, xl_mmio + MMIO_MACDATA) ; 1639 1640 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1641 writeb(MISR_RASB, xl_mmio + MMIO_MACDATA) ; 1642 1643 xl_priv->asb_queued = 2 ; 1644 1645 return ; 1646} 1647 1648/* 1649 * This will only get called if there was an error 1650 * from the asb cmd. 1651 */ 1652static void xl_asb_bh(struct net_device *dev) 1653{ 1654 struct xl_private *xl_priv = netdev_priv(dev); 1655 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 1656 u8 ret_code ; 1657 1658 writel(MMIO_BYTE_READ | 0xd0000 | xl_priv->asb | 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1659 ret_code = readb(xl_mmio + MMIO_MACDATA) ; 1660 switch (ret_code) { 1661 case 0x01: 1662 printk(KERN_INFO "%s: ASB Command, unrecognized command code \n",dev->name) ; 1663 break ; 1664 case 0x26: 1665 printk(KERN_INFO "%s: ASB Command, unexpected receive buffer \n", dev->name) ; 1666 break ; 1667 case 0x40: 1668 printk(KERN_INFO "%s: ASB Command, Invalid Station ID \n", dev->name) ; 1669 break ; 1670 } 1671 xl_priv->asb_queued = 0 ; 1672 writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ; 1673 return ; 1674} 1675 1676/* 1677 * Issue srb commands to the nic 1678 */ 1679 1680static void xl_srb_cmd(struct net_device *dev, int srb_cmd) 1681{ 1682 struct xl_private *xl_priv = netdev_priv(dev); 1683 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 1684 1685 switch (srb_cmd) { 1686 case READ_LOG: 1687 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1688 writeb(READ_LOG, xl_mmio + MMIO_MACDATA) ; 1689 break; 1690 1691 case CLOSE_NIC: 1692 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1693 writeb(CLOSE_NIC, xl_mmio + MMIO_MACDATA) ; 1694 break ; 1695 1696 case SET_RECEIVE_MODE: 1697 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1698 writeb(SET_RECEIVE_MODE, xl_mmio + MMIO_MACDATA) ; 1699 writel(MEM_WORD_WRITE | 0xD0000 | xl_priv->srb | 4, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1700 writew(xl_priv->xl_copy_all_options, xl_mmio + MMIO_MACDATA) ; 1701 break ; 1702 1703 case SET_FUNC_ADDRESS: 1704 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1705 writeb(SET_FUNC_ADDRESS, xl_mmio + MMIO_MACDATA) ; 1706 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 6 , xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1707 writeb(xl_priv->xl_functional_addr[0], xl_mmio + MMIO_MACDATA) ; 1708 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 7 , xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1709 writeb(xl_priv->xl_functional_addr[1], xl_mmio + MMIO_MACDATA) ; 1710 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 8 , xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1711 writeb(xl_priv->xl_functional_addr[2], xl_mmio + MMIO_MACDATA) ; 1712 writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 9 , xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1713 writeb(xl_priv->xl_functional_addr[3], xl_mmio + MMIO_MACDATA) ; 1714 break ; 1715 } /* switch */ 1716 1717 1718 xl_wait_misr_flags(dev) ; 1719 1720 /* Write 0xff to the CSRB flag */ 1721 writel(MEM_BYTE_WRITE | MF_CSRB , xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1722 writeb(0xFF, xl_mmio + MMIO_MACDATA) ; 1723 /* Set csrb bit in MISR register to process command */ 1724 writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1725 writeb(MISR_CSRB, xl_mmio + MMIO_MACDATA) ; 1726 xl_priv->srb_queued = 1 ; 1727 1728 return ; 1729} 1730 1731/* 1732 * This is nasty, to use the MISR command you have to wait for 6 memory locations 1733 * to be zero. This is the way the driver does on other OS'es so we should be ok with 1734 * the empty loop. 1735 */ 1736 1737static void xl_wait_misr_flags(struct net_device *dev) 1738{ 1739 struct xl_private *xl_priv = netdev_priv(dev); 1740 u8 __iomem * xl_mmio = xl_priv->xl_mmio ; 1741 1742 int i ; 1743 1744 writel(MMIO_BYTE_READ | MISR_RW, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1745 if (readb(xl_mmio + MMIO_MACDATA) != 0) { /* Misr not clear */ 1746 for (i=0; i<6; i++) { 1747 writel(MEM_BYTE_READ | 0xDFFE0 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1748 while (readb(xl_mmio + MMIO_MACDATA) != 0 ) {} ; /* Empty Loop */ 1749 } 1750 } 1751 1752 writel(MMIO_BYTE_WRITE | MISR_AND, xl_mmio + MMIO_MAC_ACCESS_CMD) ; 1753 writeb(0x80, xl_mmio + MMIO_MACDATA) ; 1754 1755 return ; 1756} 1757 1758/* 1759 * Change mtu size, this should work the same as olympic 1760 */ 1761 1762static int xl_change_mtu(struct net_device *dev, int mtu) 1763{ 1764 struct xl_private *xl_priv = netdev_priv(dev); 1765 u16 max_mtu ; 1766 1767 if (xl_priv->xl_ring_speed == 4) 1768 max_mtu = 4500 ; 1769 else 1770 max_mtu = 18000 ; 1771 1772 if (mtu > max_mtu) 1773 return -EINVAL ; 1774 if (mtu < 100) 1775 return -EINVAL ; 1776 1777 dev->mtu = mtu ; 1778 xl_priv->pkt_buf_sz = mtu + TR_HLEN ; 1779 1780 return 0 ; 1781} 1782 1783static void __devexit xl_remove_one (struct pci_dev *pdev) 1784{ 1785 struct net_device *dev = pci_get_drvdata(pdev); 1786 struct xl_private *xl_priv=netdev_priv(dev); 1787 1788 unregister_netdev(dev); 1789 iounmap(xl_priv->xl_mmio) ; 1790 pci_release_regions(pdev) ; 1791 pci_set_drvdata(pdev,NULL) ; 1792 free_netdev(dev); 1793 return ; 1794} 1795 1796static struct pci_driver xl_3c359_driver = { 1797 .name = "3c359", 1798 .id_table = xl_pci_tbl, 1799 .probe = xl_probe, 1800 .remove = __devexit_p(xl_remove_one), 1801}; 1802 1803static int __init xl_pci_init (void) 1804{ 1805 return pci_register_driver(&xl_3c359_driver); 1806} 1807 1808 1809static void __exit xl_pci_cleanup (void) 1810{ 1811 pci_unregister_driver (&xl_3c359_driver); 1812} 1813 1814module_init(xl_pci_init); 1815module_exit(xl_pci_cleanup); 1816 1817MODULE_LICENSE("GPL") ;