tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _E1000_82575_H_
29#define _E1000_82575_H_
30
31#define E1000_RAR_ENTRIES_82575 16
32
33/* SRRCTL bit definitions */
34#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
35#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
36#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
37#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
38
39#define E1000_MRQC_ENABLE_RSS_4Q 0x00000002
40#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
41#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
42#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
43
44#define E1000_EICR_TX_QUEUE ( \
45 E1000_EICR_TX_QUEUE0 | \
46 E1000_EICR_TX_QUEUE1 | \
47 E1000_EICR_TX_QUEUE2 | \
48 E1000_EICR_TX_QUEUE3)
49
50#define E1000_EICR_RX_QUEUE ( \
51 E1000_EICR_RX_QUEUE0 | \
52 E1000_EICR_RX_QUEUE1 | \
53 E1000_EICR_RX_QUEUE2 | \
54 E1000_EICR_RX_QUEUE3)
55
56#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
57#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
58
59/* Immediate Interrupt RX (A.K.A. Low Latency Interrupt) */
60
61/* Receive Descriptor - Advanced */
62union e1000_adv_rx_desc {
63 struct {
64 u64 pkt_addr; /* Packet buffer address */
65 u64 hdr_addr; /* Header buffer address */
66 } read;
67 struct {
68 struct {
69 struct {
70 u16 pkt_info; /* RSS type, Packet type */
71 u16 hdr_info; /* Split Header,
72 * header buffer length */
73 } lo_dword;
74 union {
75 u32 rss; /* RSS Hash */
76 struct {
77 u16 ip_id; /* IP id */
78 u16 csum; /* Packet Checksum */
79 } csum_ip;
80 } hi_dword;
81 } lower;
82 struct {
83 u32 status_error; /* ext status/error */
84 u16 length; /* Packet length */
85 u16 vlan; /* VLAN tag */
86 } upper;
87 } wb; /* writeback */
88};
89
90#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
91#define E1000_RXDADV_HDRBUFLEN_SHIFT 5
92
93/* RSS Hash results */
94
95/* RSS Packet Types as indicated in the receive descriptor */
96
97/* Transmit Descriptor - Advanced */
98union e1000_adv_tx_desc {
99 struct {
100 u64 buffer_addr; /* Address of descriptor's data buf */
101 u32 cmd_type_len;
102 u32 olinfo_status;
103 } read;
104 struct {
105 u64 rsvd; /* Reserved */
106 u32 nxtseq_seed;
107 u32 status;
108 } wb;
109};
110
111/* Adv Transmit Descriptor Config Masks */
112#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
113#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
114#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
115#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
116#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
117#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
118#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
119
120/* Context descriptors */
121struct e1000_adv_tx_context_desc {
122 u32 vlan_macip_lens;
123 u32 seqnum_seed;
124 u32 type_tucmd_mlhl;
125 u32 mss_l4len_idx;
126};
127
128#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
129#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
130#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
131/* IPSec Encrypt Enable for ESP */
132#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
133#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
134/* Adv ctxt IPSec SA IDX mask */
135/* Adv ctxt IPSec ESP len mask */
136
137/* Additional Transmit Descriptor Control definitions */
138#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
139/* Tx Queue Arbitration Priority 0=low, 1=high */
140
141/* Additional Receive Descriptor Control definitions */
142#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
143
144/* Direct Cache Access (DCA) definitions */
145
146
147
148#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* TX Desc writeback RO bit */
149
150#endif