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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * include/asm-xtensa/page.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version2 as
6 * published by the Free Software Foundation.
7 *
8 * Copyright (C) 2001 - 2007 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_PAGE_H
12#define _XTENSA_PAGE_H
13
14#include <asm/processor.h>
15#include <asm/types.h>
16#include <asm/cache.h>
17
18/*
19 * Fixed TLB translations in the processor.
20 */
21
22#define XCHAL_KSEG_CACHED_VADDR 0xd0000000
23#define XCHAL_KSEG_BYPASS_VADDR 0xd8000000
24#define XCHAL_KSEG_PADDR 0x00000000
25#define XCHAL_KSEG_SIZE 0x08000000
26
27/*
28 * PAGE_SHIFT determines the page size
29 * PAGE_ALIGN(x) aligns the pointer to the (next) page boundary
30 */
31
32#define PAGE_SHIFT 12
33#define PAGE_SIZE (__XTENSA_UL_CONST(1) << PAGE_SHIFT)
34#define PAGE_MASK (~(PAGE_SIZE-1))
35#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE - 1) & PAGE_MASK)
36
37#define PAGE_OFFSET XCHAL_KSEG_CACHED_VADDR
38#define MAX_MEM_PFN XCHAL_KSEG_SIZE
39#define PGTABLE_START 0x80000000
40
41/*
42 * Cache aliasing:
43 *
44 * If the cache size for one way is greater than the page size, we have to
45 * deal with cache aliasing. The cache index is wider than the page size:
46 *
47 * | |cache| cache index
48 * | pfn |off| virtual address
49 * |xxxx:X|zzz|
50 * | : | |
51 * | \ / | |
52 * |trans.| |
53 * | / \ | |
54 * |yyyy:Y|zzz| physical address
55 *
56 * When the page number is translated to the physical page address, the lowest
57 * bit(s) (X) that are part of the cache index are also translated (Y).
58 * If this translation changes bit(s) (X), the cache index is also afected,
59 * thus resulting in a different cache line than before.
60 * The kernel does not provide a mechanism to ensure that the page color
61 * (represented by this bit) remains the same when allocated or when pages
62 * are remapped. When user pages are mapped into kernel space, the color of
63 * the page might also change.
64 *
65 * We use the address space VMALLOC_END ... VMALLOC_END + DCACHE_WAY_SIZE * 2
66 * to temporarily map a patch so we can match the color.
67 */
68
69#if DCACHE_WAY_SIZE > PAGE_SIZE
70# define DCACHE_ALIAS_ORDER (DCACHE_WAY_SHIFT - PAGE_SHIFT)
71# define DCACHE_ALIAS_MASK (PAGE_MASK & (DCACHE_WAY_SIZE - 1))
72# define DCACHE_ALIAS(a) (((a) & DCACHE_ALIAS_MASK) >> PAGE_SHIFT)
73# define DCACHE_ALIAS_EQ(a,b) ((((a) ^ (b)) & DCACHE_ALIAS_MASK) == 0)
74#else
75# define DCACHE_ALIAS_ORDER 0
76#endif
77
78#if ICACHE_WAY_SIZE > PAGE_SIZE
79# define ICACHE_ALIAS_ORDER (ICACHE_WAY_SHIFT - PAGE_SHIFT)
80# define ICACHE_ALIAS_MASK (PAGE_MASK & (ICACHE_WAY_SIZE - 1))
81# define ICACHE_ALIAS(a) (((a) & ICACHE_ALIAS_MASK) >> PAGE_SHIFT)
82# define ICACHE_ALIAS_EQ(a,b) ((((a) ^ (b)) & ICACHE_ALIAS_MASK) == 0)
83#else
84# define ICACHE_ALIAS_ORDER 0
85#endif
86
87
88#ifdef __ASSEMBLY__
89
90#define __pgprot(x) (x)
91
92#else
93
94/*
95 * These are used to make use of C type-checking..
96 */
97
98typedef struct { unsigned long pte; } pte_t; /* page table entry */
99typedef struct { unsigned long pgd; } pgd_t; /* PGD table entry */
100typedef struct { unsigned long pgprot; } pgprot_t;
101typedef struct page *pgtable_t;
102
103#define pte_val(x) ((x).pte)
104#define pgd_val(x) ((x).pgd)
105#define pgprot_val(x) ((x).pgprot)
106
107#define __pte(x) ((pte_t) { (x) } )
108#define __pgd(x) ((pgd_t) { (x) } )
109#define __pgprot(x) ((pgprot_t) { (x) } )
110
111/*
112 * Pure 2^n version of get_order
113 * Use 'nsau' instructions if supported by the processor or the generic version.
114 */
115
116#if XCHAL_HAVE_NSA
117
118static inline __attribute_const__ int get_order(unsigned long size)
119{
120 int lz;
121 asm ("nsau %0, %1" : "=r" (lz) : "r" ((size - 1) >> PAGE_SHIFT));
122 return 32 - lz;
123}
124
125#else
126
127# include <asm-generic/page.h>
128
129#endif
130
131struct page;
132extern void clear_page(void *page);
133extern void copy_page(void *to, void *from);
134
135/*
136 * If we have cache aliasing and writeback caches, we might have to do
137 * some extra work
138 */
139
140#if DCACHE_WAY_SIZE > PAGE_SIZE
141extern void clear_user_page(void*, unsigned long, struct page*);
142extern void copy_user_page(void*, void*, unsigned long, struct page*);
143#else
144# define clear_user_page(page, vaddr, pg) clear_page(page)
145# define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
146#endif
147
148/*
149 * This handles the memory map. We handle pages at
150 * XCHAL_KSEG_CACHED_VADDR for kernels with 32 bit address space.
151 * These macros are for conversion of kernel address, not user
152 * addresses.
153 */
154
155#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
156#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
157#define pfn_valid(pfn) ((unsigned long)pfn < max_mapnr)
158#ifdef CONFIG_DISCONTIGMEM
159# error CONFIG_DISCONTIGMEM not supported
160#endif
161
162#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
163#define page_to_virt(page) __va(page_to_pfn(page) << PAGE_SHIFT)
164#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
165#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
166
167#define WANT_PAGE_VIRTUAL
168
169
170#endif /* __ASSEMBLY__ */
171
172#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
173 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
174
175#include <asm-generic/memory_model.h>
176#endif /* _XTENSA_PAGE_H */