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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
2 *
3 * linux/drivers/serial/sh-sci.h
4 *
5 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 1999, 2000 Niibe Yutaka
7 * Copyright (C) 2000 Greg Banks
8 * Copyright (C) 2002, 2003 Paul Mundt
9 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
12 * Removed SH7300 support (Jul 2007).
13 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Aug 2007).
14 */
15#include <linux/serial_core.h>
16#include <asm/io.h>
17
18#include <asm/gpio.h>
19
20#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
21#include <asm/regs306x.h>
22#endif
23#if defined(CONFIG_H8S2678)
24#include <asm/regs267x.h>
25#endif
26
27#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
28 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
29 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
30 defined(CONFIG_CPU_SUBTYPE_SH7709)
31# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
32# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
33# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
34# define SCI_AND_SCIF
35#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
36# define SCIF0 0xA4400000
37# define SCIF2 0xA4410000
38# define SCSMR_Ir 0xA44A0000
39# define IRDA_SCIF SCIF0
40# define SCPCR 0xA4000116
41# define SCPDR 0xA4000136
42
43/* Set the clock source,
44 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
45 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
46 */
47# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
48# define SCIF_ONLY
49#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
50# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
51# define SCIF_ONLY
52#define SCIF_ORER 0x0200 /* overrun error bit */
53#elif defined(CONFIG_SH_RTS7751R2D)
54# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
55# define SCIF_ORER 0x0001 /* overrun error bit */
56# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
57# define SCIF_ONLY
58#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
59 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
60 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
61 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
62 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
63 defined(CONFIG_CPU_SUBTYPE_SH7751R)
64# define SCSPTR1 0xffe0001c /* 8 bit SCI */
65# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
66# define SCIF_ORER 0x0001 /* overrun error bit */
67# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
68 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
69 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
70# define SCI_AND_SCIF
71#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
72# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
73# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
74# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
75# define SCIF_ORER 0x0001 /* overrun error bit */
76# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
77# define SCIF_ONLY
78#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
79# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
80# define SCIF_ORER 0x0001 /* overrun error bit */
81# define PACR 0xa4050100
82# define PBCR 0xa4050102
83# define SCSCR_INIT(port) 0x3B
84# define SCIF_ONLY
85#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
86# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
87# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
88# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
89# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
90# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
91# define SCIF_ONLY
92#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
93# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
94# define SCSPTR0 SCPDR0
95# define SCIF_ORER 0x0001 /* overrun error bit */
96# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
97# define SCIF_ONLY
98# define PORT_PSCR 0xA405011E
99#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
100# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
101# define SCIF_ORER 0x0001 /* overrun error bit */
102# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
103# define SCIF_ONLY
104#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
105# include <asm/hardware.h>
106# define SCIF_BASE_ADDR 0x01030000
107# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
108# define SCIF_PTR2_OFFS 0x0000020
109# define SCIF_LSR2_OFFS 0x0000024
110# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
111# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
112# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
113# define SCIF_ONLY
114#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
115# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
116# define SCI_ONLY
117# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
118#elif defined(CONFIG_H8S2678)
119# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
120# define SCI_ONLY
121# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
122#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
123# define SCSPTR0 0xff923020 /* 16 bit SCIF */
124# define SCSPTR1 0xff924020 /* 16 bit SCIF */
125# define SCSPTR2 0xff925020 /* 16 bit SCIF */
126# define SCIF_ORER 0x0001 /* overrun error bit */
127# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
128# define SCIF_ONLY
129#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
130# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
131# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
132# define SCIF_ORER 0x0001 /* Overrun error bit */
133# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
134# define SCIF_ONLY
135#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
136# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
137# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
138# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
139# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
140# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
141# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
142# define SCIF_OPER 0x0001 /* Overrun error bit */
143# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
144# define SCIF_ONLY
145#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
146# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
147# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
148# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
149# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
150# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
151# define SCIF_ONLY
152#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
153# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
154# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
155# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
156# define SCIF_ORER 0x0001 /* overrun error bit */
157# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
158# define SCIF_ONLY
159#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
160# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
161# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
162# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
163# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
164# define SCIF_ORER 0x0001 /* Overrun error bit */
165# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
166# define SCIF_ONLY
167#else
168# error CPU subtype not defined
169#endif
170
171/* SCSCR */
172#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
173#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
174#define SCI_CTRL_FLAGS_TE 0x20 /* all */
175#define SCI_CTRL_FLAGS_RE 0x10 /* all */
176#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
177 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
178 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
179 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
180 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
181 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
182 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
183 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
184 defined(CONFIG_CPU_SUBTYPE_SHX3)
185#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
186#else
187#define SCI_CTRL_FLAGS_REIE 0
188#endif
189/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
190/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
191/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
192/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
193
194/* SCxSR SCI */
195#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
196#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
197#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
198#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
199#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
200#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
201/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
202/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
203
204#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
205
206/* SCxSR SCIF */
207#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
208#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
209#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
210#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
211#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
212#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
213#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
214#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
215
216#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
217 defined(CONFIG_CPU_SUBTYPE_SH7720)
218#define SCIF_ORER 0x0200
219#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
220#define SCIF_RFDC_MASK 0x007f
221#define SCIF_TXROOM_MAX 64
222#else
223#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
224#define SCIF_RFDC_MASK 0x001f
225#define SCIF_TXROOM_MAX 16
226#endif
227
228#if defined(SCI_ONLY)
229# define SCxSR_TEND(port) SCI_TEND
230# define SCxSR_ERRORS(port) SCI_ERRORS
231# define SCxSR_RDxF(port) SCI_RDRF
232# define SCxSR_TDxE(port) SCI_TDRE
233# define SCxSR_ORER(port) SCI_ORER
234# define SCxSR_FER(port) SCI_FER
235# define SCxSR_PER(port) SCI_PER
236# define SCxSR_BRK(port) 0x00
237# define SCxSR_RDxF_CLEAR(port) 0xbc
238# define SCxSR_ERROR_CLEAR(port) 0xc4
239# define SCxSR_TDxE_CLEAR(port) 0x78
240# define SCxSR_BREAK_CLEAR(port) 0xc4
241#elif defined(SCIF_ONLY)
242# define SCxSR_TEND(port) SCIF_TEND
243# define SCxSR_ERRORS(port) SCIF_ERRORS
244# define SCxSR_RDxF(port) SCIF_RDF
245# define SCxSR_TDxE(port) SCIF_TDFE
246#if defined(CONFIG_CPU_SUBTYPE_SH7705)
247# define SCxSR_ORER(port) SCIF_ORER
248#else
249# define SCxSR_ORER(port) 0x0000
250#endif
251# define SCxSR_FER(port) SCIF_FER
252# define SCxSR_PER(port) SCIF_PER
253# define SCxSR_BRK(port) SCIF_BRK
254#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
255 defined(CONFIG_CPU_SUBTYPE_SH7720)
256# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
257# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
258# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
259# define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
260#else
261/* SH7705 can also use this, clearing is same between 7705 and 7709 */
262# define SCxSR_RDxF_CLEAR(port) 0x00fc
263# define SCxSR_ERROR_CLEAR(port) 0x0073
264# define SCxSR_TDxE_CLEAR(port) 0x00df
265# define SCxSR_BREAK_CLEAR(port) 0x00e3
266#endif
267#else
268# define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
269# define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
270# define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
271# define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
272# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
273# define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
274# define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
275# define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
276# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
277# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
278# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
279# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
280#endif
281
282/* SCFCR */
283#define SCFCR_RFRST 0x0002
284#define SCFCR_TFRST 0x0004
285#define SCFCR_TCRST 0x4000
286#define SCFCR_MCE 0x0008
287
288#define SCI_MAJOR 204
289#define SCI_MINOR_START 8
290
291/* Generic serial flags */
292#define SCI_RX_THROTTLE 0x0000001
293
294#define SCI_MAGIC 0xbabeface
295
296/*
297 * Events are used to schedule things to happen at timer-interrupt
298 * time, instead of at rs interrupt time.
299 */
300#define SCI_EVENT_WRITE_WAKEUP 0
301
302#define SCI_IN(size, offset) \
303 unsigned int addr = port->mapbase + (offset); \
304 if ((size) == 8) { \
305 return ctrl_inb(addr); \
306 } else { \
307 return ctrl_inw(addr); \
308 }
309#define SCI_OUT(size, offset, value) \
310 unsigned int addr = port->mapbase + (offset); \
311 if ((size) == 8) { \
312 ctrl_outb(value, addr); \
313 } else { \
314 ctrl_outw(value, addr); \
315 }
316
317#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
318 static inline unsigned int sci_##name##_in(struct uart_port *port) \
319 { \
320 if (port->type == PORT_SCI) { \
321 SCI_IN(sci_size, sci_offset) \
322 } else { \
323 SCI_IN(scif_size, scif_offset); \
324 } \
325 } \
326 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
327 { \
328 if (port->type == PORT_SCI) { \
329 SCI_OUT(sci_size, sci_offset, value) \
330 } else { \
331 SCI_OUT(scif_size, scif_offset, value); \
332 } \
333 }
334
335#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
336 static inline unsigned int sci_##name##_in(struct uart_port *port) \
337 { \
338 SCI_IN(scif_size, scif_offset); \
339 } \
340 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
341 { \
342 SCI_OUT(scif_size, scif_offset, value); \
343 }
344
345#define CPU_SCI_FNS(name, sci_offset, sci_size) \
346 static inline unsigned int sci_##name##_in(struct uart_port* port) \
347 { \
348 SCI_IN(sci_size, sci_offset); \
349 } \
350 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
351 { \
352 SCI_OUT(sci_size, sci_offset, value); \
353 }
354
355#ifdef CONFIG_CPU_SH3
356#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
357#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
358 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
359 h8_sci_offset, h8_sci_size) \
360 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
361#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
362 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
363#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
364 defined(CONFIG_CPU_SUBTYPE_SH7720)
365#define SCIF_FNS(name, scif_offset, scif_size) \
366 CPU_SCIF_FNS(name, scif_offset, scif_size)
367#else
368#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
369 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
370 h8_sci_offset, h8_sci_size) \
371 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
372#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
373 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
374#endif
375#elif defined(__H8300H__) || defined(__H8300S__)
376#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
377 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
378 h8_sci_offset, h8_sci_size) \
379 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
380#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
381#else
382#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
383 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
384 h8_sci_offset, h8_sci_size) \
385 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
386#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
387 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
388#endif
389
390#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
391 defined(CONFIG_CPU_SUBTYPE_SH7720)
392
393SCIF_FNS(SCSMR, 0x00, 16)
394SCIF_FNS(SCBRR, 0x04, 8)
395SCIF_FNS(SCSCR, 0x08, 16)
396SCIF_FNS(SCTDSR, 0x0c, 8)
397SCIF_FNS(SCFER, 0x10, 16)
398SCIF_FNS(SCxSR, 0x14, 16)
399SCIF_FNS(SCFCR, 0x18, 16)
400SCIF_FNS(SCFDR, 0x1c, 16)
401SCIF_FNS(SCxTDR, 0x20, 8)
402SCIF_FNS(SCxRDR, 0x24, 8)
403SCIF_FNS(SCLSR, 0x24, 16)
404#else
405/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
406/* name off sz off sz off sz off sz off sz*/
407SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
408SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
409SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
410SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
411SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
412SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
413SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
414#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
415 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
416 defined(CONFIG_CPU_SUBTYPE_SH7785)
417SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
418SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
419SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
420SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
421SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
422#else
423SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
424SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
425SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
426#endif
427#endif
428#define sci_in(port, reg) sci_##reg##_in(port)
429#define sci_out(port, reg, value) sci_##reg##_out(port, value)
430
431/* H8/300 series SCI pins assignment */
432#if defined(__H8300H__) || defined(__H8300S__)
433static const struct __attribute__((packed)) {
434 int port; /* GPIO port no */
435 unsigned short rx,tx; /* GPIO bit no */
436} h8300_sci_pins[] = {
437#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
438 { /* SCI0 */
439 .port = H8300_GPIO_P9,
440 .rx = H8300_GPIO_B2,
441 .tx = H8300_GPIO_B0,
442 },
443 { /* SCI1 */
444 .port = H8300_GPIO_P9,
445 .rx = H8300_GPIO_B3,
446 .tx = H8300_GPIO_B1,
447 },
448 { /* SCI2 */
449 .port = H8300_GPIO_PB,
450 .rx = H8300_GPIO_B7,
451 .tx = H8300_GPIO_B6,
452 }
453#elif defined(CONFIG_H8S2678)
454 { /* SCI0 */
455 .port = H8300_GPIO_P3,
456 .rx = H8300_GPIO_B2,
457 .tx = H8300_GPIO_B0,
458 },
459 { /* SCI1 */
460 .port = H8300_GPIO_P3,
461 .rx = H8300_GPIO_B3,
462 .tx = H8300_GPIO_B1,
463 },
464 { /* SCI2 */
465 .port = H8300_GPIO_P5,
466 .rx = H8300_GPIO_B1,
467 .tx = H8300_GPIO_B0,
468 }
469#endif
470};
471#endif
472
473#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
474 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
475 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
476 defined(CONFIG_CPU_SUBTYPE_SH7709)
477static inline int sci_rxd_in(struct uart_port *port)
478{
479 if (port->mapbase == 0xfffffe80)
480 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
481 if (port->mapbase == 0xa4000150)
482 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
483 if (port->mapbase == 0xa4000140)
484 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
485 return 1;
486}
487#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
488static inline int sci_rxd_in(struct uart_port *port)
489{
490 if (port->mapbase == SCIF0)
491 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
492 if (port->mapbase == SCIF2)
493 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
494 return 1;
495}
496#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
497static inline int sci_rxd_in(struct uart_port *port)
498{
499 return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
500}
501static inline void set_sh771x_scif_pfc(struct uart_port *port)
502{
503 if (port->mapbase == 0xA4400000){
504 ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
505 ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
506 return;
507 }
508 if (port->mapbase == 0xA4410000){
509 ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
510 return;
511 }
512}
513#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
514static inline int sci_rxd_in(struct uart_port *port)
515{
516 if (port->mapbase == 0xa4430000)
517 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
518 else if (port->mapbase == 0xa4438000)
519 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
520 return 1;
521}
522#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
523 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
524 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
525 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
526 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
527 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
528 defined(CONFIG_CPU_SUBTYPE_SH4_202)
529static inline int sci_rxd_in(struct uart_port *port)
530{
531#ifndef SCIF_ONLY
532 if (port->mapbase == 0xffe00000)
533 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
534#endif
535#ifndef SCI_ONLY
536 if (port->mapbase == 0xffe80000)
537 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
538#endif
539 return 1;
540}
541#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
542static inline int sci_rxd_in(struct uart_port *port)
543{
544 if (port->mapbase == 0xfe600000)
545 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
546 if (port->mapbase == 0xfe610000)
547 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
548 if (port->mapbase == 0xfe620000)
549 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
550 return 1;
551}
552#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
553static inline int sci_rxd_in(struct uart_port *port)
554{
555 if (port->mapbase == 0xffe00000)
556 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
557 if (port->mapbase == 0xffe10000)
558 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
559 if (port->mapbase == 0xffe20000)
560 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
561 if (port->mapbase == 0xffe30000)
562 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
563 return 1;
564}
565#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
566static inline int sci_rxd_in(struct uart_port *port)
567{
568 if (port->mapbase == 0xffe00000)
569 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
570 return 1;
571}
572#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
573static inline int sci_rxd_in(struct uart_port *port)
574{
575 return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
576}
577#elif defined(__H8300H__) || defined(__H8300S__)
578static inline int sci_rxd_in(struct uart_port *port)
579{
580 int ch = (port->mapbase - SMR0) >> 3;
581 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
582}
583#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
584static inline int sci_rxd_in(struct uart_port *port)
585{
586 if (port->mapbase == 0xff923000)
587 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
588 if (port->mapbase == 0xff924000)
589 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
590 if (port->mapbase == 0xff925000)
591 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
592 return 1;
593}
594#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
595static inline int sci_rxd_in(struct uart_port *port)
596{
597 if (port->mapbase == 0xffe00000)
598 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
599 if (port->mapbase == 0xffe10000)
600 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
601 return 1;
602}
603#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
604static inline int sci_rxd_in(struct uart_port *port)
605{
606 if (port->mapbase == 0xffea0000)
607 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
608 if (port->mapbase == 0xffeb0000)
609 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
610 if (port->mapbase == 0xffec0000)
611 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
612 if (port->mapbase == 0xffed0000)
613 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
614 if (port->mapbase == 0xffee0000)
615 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
616 if (port->mapbase == 0xffef0000)
617 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
618 return 1;
619}
620#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
621static inline int sci_rxd_in(struct uart_port *port)
622{
623 if (port->mapbase == 0xfffe8000)
624 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
625 if (port->mapbase == 0xfffe8800)
626 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
627 if (port->mapbase == 0xfffe9000)
628 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
629 if (port->mapbase == 0xfffe9800)
630 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
631 return 1;
632}
633#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
634static inline int sci_rxd_in(struct uart_port *port)
635{
636 if (port->mapbase == 0xf8400000)
637 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
638 if (port->mapbase == 0xf8410000)
639 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
640 if (port->mapbase == 0xf8420000)
641 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
642 return 1;
643}
644#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
645static inline int sci_rxd_in(struct uart_port *port)
646{
647 if (port->mapbase == 0xffc30000)
648 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
649 if (port->mapbase == 0xffc40000)
650 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
651 if (port->mapbase == 0xffc50000)
652 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
653 if (port->mapbase == 0xffc60000)
654 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
655 return 1;
656}
657#endif
658
659/*
660 * Values for the BitRate Register (SCBRR)
661 *
662 * The values are actually divisors for a frequency which can
663 * be internal to the SH3 (14.7456MHz) or derived from an external
664 * clock source. This driver assumes the internal clock is used;
665 * to support using an external clock source, config options or
666 * possibly command-line options would need to be added.
667 *
668 * Also, to support speeds below 2400 (why?) the lower 2 bits of
669 * the SCSMR register would also need to be set to non-zero values.
670 *
671 * -- Greg Banks 27Feb2000
672 *
673 * Answer: The SCBRR register is only eight bits, and the value in
674 * it gets larger with lower baud rates. At around 2400 (depending on
675 * the peripherial module clock) you run out of bits. However the
676 * lower two bits of SCSMR allow the module clock to be divided down,
677 * scaling the value which is needed in SCBRR.
678 *
679 * -- Stuart Menefy - 23 May 2000
680 *
681 * I meant, why would anyone bother with bitrates below 2400.
682 *
683 * -- Greg Banks - 7Jul2000
684 *
685 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
686 * tape reader as a console!
687 *
688 * -- Mitch Davis - 15 Jul 2000
689 */
690
691#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
692 defined(CONFIG_CPU_SUBTYPE_SH7785)
693#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
694#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
695 defined(CONFIG_CPU_SUBTYPE_SH7720)
696#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
697#elif defined(__H8300H__) || defined(__H8300S__)
698#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
699#elif defined(CONFIG_SUPERH64)
700#define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
701#else /* Generic SH */
702#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
703#endif