tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 */
6#ifndef __MIPSNET_H
7#define __MIPSNET_H
8
9/*
10 * Id of this Net device, as seen by the core.
11 */
12#define MIPS_NET_DEV_ID ((uint64_t) \
13 ((uint64_t) 'M' << 0)| \
14 ((uint64_t) 'I' << 8)| \
15 ((uint64_t) 'P' << 16)| \
16 ((uint64_t) 'S' << 24)| \
17 ((uint64_t) 'N' << 32)| \
18 ((uint64_t) 'E' << 40)| \
19 ((uint64_t) 'T' << 48)| \
20 ((uint64_t) '0' << 56))
21
22/*
23 * Net status/control block as seen by sw in the core.
24 * (Why not use bit fields? can't be bothered with cross-platform struct
25 * packing.)
26 */
27struct net_control_block {
28 /*
29 * dev info for probing
30 * reads as MIPSNET%d where %d is some form of version
31 */
32 uint64_t devId; /* 0x00 */
33
34 /*
35 * read only busy flag.
36 * Set and cleared by the Net Device to indicate that an rx or a tx
37 * is in progress.
38 */
39 uint32_t busy; /* 0x08 */
40
41 /*
42 * Set by the Net Device.
43 * The device will set it once data has been received.
44 * The value is the number of bytes that should be read from
45 * rxDataBuffer. The value will decrease till 0 until all the data
46 * from rxDataBuffer has been read.
47 */
48 uint32_t rxDataCount; /* 0x0c */
49#define MIPSNET_MAX_RXTX_DATACOUNT (1<<16)
50
51 /*
52 * Settable from the MIPS core, cleared by the Net Device. The core
53 * should set the number of bytes it wants to send, then it should
54 * write those bytes of data to txDataBuffer. The device will clear
55 * txDataCount has been processed (not necessarily sent).
56 */
57 uint32_t txDataCount; /* 0x10 */
58
59 /*
60 * Interrupt control
61 *
62 * Used to clear the interrupted generated by this dev.
63 * Write a 1 to clear the interrupt. (except bit31).
64 *
65 * Bit0 is set if it was a tx-done interrupt.
66 * Bit1 is set when new rx-data is available.
67 * Until this bit is cleared there will be no other RXs.
68 *
69 * Bit31 is used for testing, it clears after a read.
70 * Writing 1 to this bit will cause an interrupt to be generated.
71 * To clear the test interrupt, write 0 to this register.
72 */
73 uint32_t interruptControl; /*0x14 */
74#define MIPSNET_INTCTL_TXDONE ((uint32_t)(1 << 0))
75#define MIPSNET_INTCTL_RXDONE ((uint32_t)(1 << 1))
76#define MIPSNET_INTCTL_TESTBIT ((uint32_t)(1 << 31))
77#define MIPSNET_INTCTL_ALLSOURCES (MIPSNET_INTCTL_TXDONE | \
78 MIPSNET_INTCTL_RXDONE | \
79 MIPSNET_INTCTL_TESTBIT)
80
81 /*
82 * Readonly core-specific interrupt info for the device to signal the
83 * core. The meaning of the contents of this field might change.
84 *
85 * TODO: the whole memIntf interrupt scheme is messy: the device should
86 * have no control what so ever of what VPE/register set is being
87 * used. The MemIntf should only expose interrupt lines, and
88 * something in the config should be responsible for the
89 * line<->core/vpe bindings.
90 */
91 uint32_t interruptInfo; /* 0x18 */
92
93 /*
94 * This is where the received data is read out.
95 * There is more data to read until rxDataReady is 0.
96 * Only 1 byte at this regs offset is used.
97 */
98 uint32_t rxDataBuffer; /* 0x1c */
99
100 /*
101 * This is where the data to transmit is written. Data should be
102 * written for the amount specified in the txDataCount register. Only
103 * 1 byte at this regs offset is used.
104 */
105 uint32_t txDataBuffer; /* 0x20 */
106};
107
108#define MIPSNET_IO_EXTENT 0x40 /* being generous */
109
110#define field_offset(field) (offsetof(struct net_control_block, field))
111
112#endif /* __MIPSNET_H */