tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1
2/*
3 * Common code for mac80211 Prism54 drivers
4 *
5 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
6 * Copyright (c) 2007, Christian Lamparter <chunkeey@web.de>
7 *
8 * Based on the islsm (softmac prism54) driver, which is:
9 * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/init.h>
17#include <linux/firmware.h>
18#include <linux/etherdevice.h>
19
20#include <net/mac80211.h>
21
22#include "p54.h"
23#include "p54common.h"
24
25MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
26MODULE_DESCRIPTION("Softmac Prism54 common code");
27MODULE_LICENSE("GPL");
28MODULE_ALIAS("prism54common");
29
30void p54_parse_firmware(struct ieee80211_hw *dev, const struct firmware *fw)
31{
32 struct p54_common *priv = dev->priv;
33 struct bootrec_exp_if *exp_if;
34 struct bootrec *bootrec;
35 u32 *data = (u32 *)fw->data;
36 u32 *end_data = (u32 *)fw->data + (fw->size >> 2);
37 u8 *fw_version = NULL;
38 size_t len;
39 int i;
40
41 if (priv->rx_start)
42 return;
43
44 while (data < end_data && *data)
45 data++;
46
47 while (data < end_data && !*data)
48 data++;
49
50 bootrec = (struct bootrec *) data;
51
52 while (bootrec->data <= end_data &&
53 (bootrec->data + (len = le32_to_cpu(bootrec->len))) <= end_data) {
54 u32 code = le32_to_cpu(bootrec->code);
55 switch (code) {
56 case BR_CODE_COMPONENT_ID:
57 switch (be32_to_cpu(*bootrec->data)) {
58 case FW_FMAC:
59 printk(KERN_INFO "p54: FreeMAC firmware\n");
60 break;
61 case FW_LM20:
62 printk(KERN_INFO "p54: LM20 firmware\n");
63 break;
64 case FW_LM86:
65 printk(KERN_INFO "p54: LM86 firmware\n");
66 break;
67 case FW_LM87:
68 printk(KERN_INFO "p54: LM87 firmware - not supported yet!\n");
69 break;
70 default:
71 printk(KERN_INFO "p54: unknown firmware\n");
72 break;
73 }
74 break;
75 case BR_CODE_COMPONENT_VERSION:
76 /* 24 bytes should be enough for all firmwares */
77 if (strnlen((unsigned char*)bootrec->data, 24) < 24)
78 fw_version = (unsigned char*)bootrec->data;
79 break;
80 case BR_CODE_DESCR:
81 priv->rx_start = le32_to_cpu(bootrec->data[1]);
82 /* FIXME add sanity checking */
83 priv->rx_end = le32_to_cpu(bootrec->data[2]) - 0x3500;
84 break;
85 case BR_CODE_EXPOSED_IF:
86 exp_if = (struct bootrec_exp_if *) bootrec->data;
87 for (i = 0; i < (len * sizeof(*exp_if) / 4); i++)
88 if (exp_if[i].if_id == 0x1a)
89 priv->fw_var = le16_to_cpu(exp_if[i].variant);
90 break;
91 case BR_CODE_DEPENDENT_IF:
92 break;
93 case BR_CODE_END_OF_BRA:
94 case LEGACY_BR_CODE_END_OF_BRA:
95 end_data = NULL;
96 break;
97 default:
98 break;
99 }
100 bootrec = (struct bootrec *)&bootrec->data[len];
101 }
102
103 if (fw_version)
104 printk(KERN_INFO "p54: FW rev %s - Softmac protocol %x.%x\n",
105 fw_version, priv->fw_var >> 8, priv->fw_var & 0xff);
106
107 if (priv->fw_var >= 0x300) {
108 /* Firmware supports QoS, use it! */
109 priv->tx_stats.data[0].limit = 3;
110 priv->tx_stats.data[1].limit = 4;
111 priv->tx_stats.data[2].limit = 3;
112 priv->tx_stats.data[3].limit = 1;
113 dev->queues = 4;
114 }
115}
116EXPORT_SYMBOL_GPL(p54_parse_firmware);
117
118static int p54_convert_rev0_to_rev1(struct ieee80211_hw *dev,
119 struct pda_pa_curve_data *curve_data)
120{
121 struct p54_common *priv = dev->priv;
122 struct pda_pa_curve_data_sample_rev1 *rev1;
123 struct pda_pa_curve_data_sample_rev0 *rev0;
124 size_t cd_len = sizeof(*curve_data) +
125 (curve_data->points_per_channel*sizeof(*rev1) + 2) *
126 curve_data->channels;
127 unsigned int i, j;
128 void *source, *target;
129
130 priv->curve_data = kmalloc(cd_len, GFP_KERNEL);
131 if (!priv->curve_data)
132 return -ENOMEM;
133
134 memcpy(priv->curve_data, curve_data, sizeof(*curve_data));
135 source = curve_data->data;
136 target = priv->curve_data->data;
137 for (i = 0; i < curve_data->channels; i++) {
138 __le16 *freq = source;
139 source += sizeof(__le16);
140 *((__le16 *)target) = *freq;
141 target += sizeof(__le16);
142 for (j = 0; j < curve_data->points_per_channel; j++) {
143 rev1 = target;
144 rev0 = source;
145
146 rev1->rf_power = rev0->rf_power;
147 rev1->pa_detector = rev0->pa_detector;
148 rev1->data_64qam = rev0->pcv;
149 /* "invent" the points for the other modulations */
150#define SUB(x,y) (u8)((x) - (y)) > (x) ? 0 : (x) - (y)
151 rev1->data_16qam = SUB(rev0->pcv, 12);
152 rev1->data_qpsk = SUB(rev1->data_16qam, 12);
153 rev1->data_bpsk = SUB(rev1->data_qpsk, 12);
154 rev1->data_barker= SUB(rev1->data_bpsk, 14);
155#undef SUB
156 target += sizeof(*rev1);
157 source += sizeof(*rev0);
158 }
159 }
160
161 return 0;
162}
163
164int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len)
165{
166 struct p54_common *priv = dev->priv;
167 struct eeprom_pda_wrap *wrap = NULL;
168 struct pda_entry *entry;
169 int i = 0;
170 unsigned int data_len, entry_len;
171 void *tmp;
172 int err;
173
174 wrap = (struct eeprom_pda_wrap *) eeprom;
175 entry = (void *)wrap->data + wrap->len;
176 i += 2;
177 i += le16_to_cpu(entry->len)*2;
178 while (i < len) {
179 entry_len = le16_to_cpu(entry->len);
180 data_len = ((entry_len - 1) << 1);
181 switch (le16_to_cpu(entry->code)) {
182 case PDR_MAC_ADDRESS:
183 SET_IEEE80211_PERM_ADDR(dev, entry->data);
184 break;
185 case PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS:
186 if (data_len < 2) {
187 err = -EINVAL;
188 goto err;
189 }
190
191 if (2 + entry->data[1]*sizeof(*priv->output_limit) > data_len) {
192 err = -EINVAL;
193 goto err;
194 }
195
196 priv->output_limit = kmalloc(entry->data[1] *
197 sizeof(*priv->output_limit), GFP_KERNEL);
198
199 if (!priv->output_limit) {
200 err = -ENOMEM;
201 goto err;
202 }
203
204 memcpy(priv->output_limit, &entry->data[2],
205 entry->data[1]*sizeof(*priv->output_limit));
206 priv->output_limit_len = entry->data[1];
207 break;
208 case PDR_PRISM_PA_CAL_CURVE_DATA:
209 if (data_len < sizeof(struct pda_pa_curve_data)) {
210 err = -EINVAL;
211 goto err;
212 }
213
214 if (((struct pda_pa_curve_data *)entry->data)->cal_method_rev) {
215 priv->curve_data = kmalloc(data_len, GFP_KERNEL);
216 if (!priv->curve_data) {
217 err = -ENOMEM;
218 goto err;
219 }
220
221 memcpy(priv->curve_data, entry->data, data_len);
222 } else {
223 err = p54_convert_rev0_to_rev1(dev, (struct pda_pa_curve_data *)entry->data);
224 if (err)
225 goto err;
226 }
227
228 break;
229 case PDR_PRISM_ZIF_TX_IQ_CALIBRATION:
230 priv->iq_autocal = kmalloc(data_len, GFP_KERNEL);
231 if (!priv->iq_autocal) {
232 err = -ENOMEM;
233 goto err;
234 }
235
236 memcpy(priv->iq_autocal, entry->data, data_len);
237 priv->iq_autocal_len = data_len / sizeof(struct pda_iq_autocal_entry);
238 break;
239 case PDR_INTERFACE_LIST:
240 tmp = entry->data;
241 while ((u8 *)tmp < entry->data + data_len) {
242 struct bootrec_exp_if *exp_if = tmp;
243 if (le16_to_cpu(exp_if->if_id) == 0xF)
244 priv->rxhw = exp_if->variant & cpu_to_le16(0x07);
245 tmp += sizeof(struct bootrec_exp_if);
246 }
247 break;
248 case PDR_HARDWARE_PLATFORM_COMPONENT_ID:
249 priv->version = *(u8 *)(entry->data + 1);
250 break;
251 case PDR_END:
252 i = len;
253 break;
254 }
255
256 entry = (void *)entry + (entry_len + 1)*2;
257 i += 2;
258 i += entry_len*2;
259 }
260
261 if (!priv->iq_autocal || !priv->output_limit || !priv->curve_data) {
262 printk(KERN_ERR "p54: not all required entries found in eeprom!\n");
263 err = -EINVAL;
264 goto err;
265 }
266
267 return 0;
268
269 err:
270 if (priv->iq_autocal) {
271 kfree(priv->iq_autocal);
272 priv->iq_autocal = NULL;
273 }
274
275 if (priv->output_limit) {
276 kfree(priv->output_limit);
277 priv->output_limit = NULL;
278 }
279
280 if (priv->curve_data) {
281 kfree(priv->curve_data);
282 priv->curve_data = NULL;
283 }
284
285 printk(KERN_ERR "p54: eeprom parse failed!\n");
286 return err;
287}
288EXPORT_SYMBOL_GPL(p54_parse_eeprom);
289
290void p54_fill_eeprom_readback(struct p54_control_hdr *hdr)
291{
292 struct p54_eeprom_lm86 *eeprom_hdr;
293
294 hdr->magic1 = cpu_to_le16(0x8000);
295 hdr->len = cpu_to_le16(sizeof(*eeprom_hdr) + 0x2000);
296 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_EEPROM_READBACK);
297 hdr->retry1 = hdr->retry2 = 0;
298 eeprom_hdr = (struct p54_eeprom_lm86 *) hdr->data;
299 eeprom_hdr->offset = 0x0;
300 eeprom_hdr->len = cpu_to_le16(0x2000);
301}
302EXPORT_SYMBOL_GPL(p54_fill_eeprom_readback);
303
304static void p54_rx_data(struct ieee80211_hw *dev, struct sk_buff *skb)
305{
306 struct p54_rx_hdr *hdr = (struct p54_rx_hdr *) skb->data;
307 struct ieee80211_rx_status rx_status = {0};
308 u16 freq = le16_to_cpu(hdr->freq);
309
310 rx_status.ssi = hdr->rssi;
311 rx_status.rate = hdr->rate & 0x1f; /* report short preambles & CCK too */
312 rx_status.channel = freq == 2484 ? 14 : (freq - 2407)/5;
313 rx_status.freq = freq;
314 rx_status.phymode = MODE_IEEE80211G;
315 rx_status.antenna = hdr->antenna;
316 rx_status.mactime = le64_to_cpu(hdr->timestamp);
317
318 skb_pull(skb, sizeof(*hdr));
319 skb_trim(skb, le16_to_cpu(hdr->len));
320
321 ieee80211_rx_irqsafe(dev, skb, &rx_status);
322}
323
324static void inline p54_wake_free_queues(struct ieee80211_hw *dev)
325{
326 struct p54_common *priv = dev->priv;
327 int i;
328
329 /* ieee80211_start_queues is great if all queues are really empty.
330 * But, what if some are full? */
331
332 for (i = 0; i < dev->queues; i++)
333 if (priv->tx_stats.data[i].len < priv->tx_stats.data[i].limit)
334 ieee80211_wake_queue(dev, i);
335}
336
337static void p54_rx_frame_sent(struct ieee80211_hw *dev, struct sk_buff *skb)
338{
339 struct p54_common *priv = dev->priv;
340 struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data;
341 struct p54_frame_sent_hdr *payload = (struct p54_frame_sent_hdr *) hdr->data;
342 struct sk_buff *entry = (struct sk_buff *) priv->tx_queue.next;
343 u32 addr = le32_to_cpu(hdr->req_id) - 0x70;
344 struct memrecord *range = NULL;
345 u32 freed = 0;
346 u32 last_addr = priv->rx_start;
347
348 while (entry != (struct sk_buff *)&priv->tx_queue) {
349 range = (struct memrecord *)&entry->cb;
350 if (range->start_addr == addr) {
351 struct ieee80211_tx_status status = {{0}};
352 struct p54_control_hdr *entry_hdr;
353 struct p54_tx_control_allocdata *entry_data;
354 int pad = 0;
355
356 if (entry->next != (struct sk_buff *)&priv->tx_queue)
357 freed = ((struct memrecord *)&entry->next->cb)->start_addr - last_addr;
358 else
359 freed = priv->rx_end - last_addr;
360
361 last_addr = range->end_addr;
362 __skb_unlink(entry, &priv->tx_queue);
363 if (!range->control) {
364 kfree_skb(entry);
365 break;
366 }
367 memcpy(&status.control, range->control,
368 sizeof(status.control));
369 kfree(range->control);
370 priv->tx_stats.data[status.control.queue].len--;
371
372 entry_hdr = (struct p54_control_hdr *) entry->data;
373 entry_data = (struct p54_tx_control_allocdata *) entry_hdr->data;
374 if ((entry_hdr->magic1 & cpu_to_le16(0x4000)) != 0)
375 pad = entry_data->align[0];
376
377 if (!status.control.flags & IEEE80211_TXCTL_NO_ACK) {
378 if (!(payload->status & 0x01))
379 status.flags |= IEEE80211_TX_STATUS_ACK;
380 else
381 status.excessive_retries = 1;
382 }
383 status.retry_count = payload->retries - 1;
384 status.ack_signal = le16_to_cpu(payload->ack_rssi);
385 skb_pull(entry, sizeof(*hdr) + pad + sizeof(*entry_data));
386 ieee80211_tx_status_irqsafe(dev, entry, &status);
387 break;
388 } else
389 last_addr = range->end_addr;
390 entry = entry->next;
391 }
392
393 if (freed >= IEEE80211_MAX_RTS_THRESHOLD + 0x170 +
394 sizeof(struct p54_control_hdr))
395 p54_wake_free_queues(dev);
396}
397
398static void p54_rx_control(struct ieee80211_hw *dev, struct sk_buff *skb)
399{
400 struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data;
401
402 switch (le16_to_cpu(hdr->type)) {
403 case P54_CONTROL_TYPE_TXDONE:
404 p54_rx_frame_sent(dev, skb);
405 break;
406 case P54_CONTROL_TYPE_BBP:
407 break;
408 default:
409 printk(KERN_DEBUG "%s: not handling 0x%02x type control frame\n",
410 wiphy_name(dev->wiphy), le16_to_cpu(hdr->type));
411 break;
412 }
413}
414
415/* returns zero if skb can be reused */
416int p54_rx(struct ieee80211_hw *dev, struct sk_buff *skb)
417{
418 u8 type = le16_to_cpu(*((__le16 *)skb->data)) >> 8;
419 switch (type) {
420 case 0x00:
421 case 0x01:
422 p54_rx_data(dev, skb);
423 return -1;
424 case 0x4d:
425 /* TODO: do something better... but then again, I've never seen this happen */
426 printk(KERN_ERR "%s: Received fault. Probably need to restart hardware now..\n",
427 wiphy_name(dev->wiphy));
428 break;
429 case 0x80:
430 p54_rx_control(dev, skb);
431 break;
432 default:
433 printk(KERN_ERR "%s: unknown frame RXed (0x%02x)\n",
434 wiphy_name(dev->wiphy), type);
435 break;
436 }
437 return 0;
438}
439EXPORT_SYMBOL_GPL(p54_rx);
440
441/*
442 * So, the firmware is somewhat stupid and doesn't know what places in its
443 * memory incoming data should go to. By poking around in the firmware, we
444 * can find some unused memory to upload our packets to. However, data that we
445 * want the card to TX needs to stay intact until the card has told us that
446 * it is done with it. This function finds empty places we can upload to and
447 * marks allocated areas as reserved if necessary. p54_rx_frame_sent frees
448 * allocated areas.
449 */
450static void p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb,
451 struct p54_control_hdr *data, u32 len,
452 struct ieee80211_tx_control *control)
453{
454 struct p54_common *priv = dev->priv;
455 struct sk_buff *entry = priv->tx_queue.next;
456 struct sk_buff *target_skb = NULL;
457 struct memrecord *range;
458 u32 last_addr = priv->rx_start;
459 u32 largest_hole = 0;
460 u32 target_addr = priv->rx_start;
461 unsigned long flags;
462 unsigned int left;
463 len = (len + 0x170 + 3) & ~0x3; /* 0x70 headroom, 0x100 tailroom */
464
465 spin_lock_irqsave(&priv->tx_queue.lock, flags);
466 left = skb_queue_len(&priv->tx_queue);
467 while (left--) {
468 u32 hole_size;
469 range = (struct memrecord *)&entry->cb;
470 hole_size = range->start_addr - last_addr;
471 if (!target_skb && hole_size >= len) {
472 target_skb = entry->prev;
473 hole_size -= len;
474 target_addr = last_addr;
475 }
476 largest_hole = max(largest_hole, hole_size);
477 last_addr = range->end_addr;
478 entry = entry->next;
479 }
480 if (!target_skb && priv->rx_end - last_addr >= len) {
481 target_skb = priv->tx_queue.prev;
482 largest_hole = max(largest_hole, priv->rx_end - last_addr - len);
483 if (!skb_queue_empty(&priv->tx_queue)) {
484 range = (struct memrecord *)&target_skb->cb;
485 target_addr = range->end_addr;
486 }
487 } else
488 largest_hole = max(largest_hole, priv->rx_end - last_addr);
489
490 if (skb) {
491 range = (struct memrecord *)&skb->cb;
492 range->start_addr = target_addr;
493 range->end_addr = target_addr + len;
494 range->control = control;
495 __skb_queue_after(&priv->tx_queue, target_skb, skb);
496 if (largest_hole < IEEE80211_MAX_RTS_THRESHOLD + 0x170 +
497 sizeof(struct p54_control_hdr))
498 ieee80211_stop_queues(dev);
499 }
500 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
501
502 data->req_id = cpu_to_le32(target_addr + 0x70);
503}
504
505static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
506 struct ieee80211_tx_control *control)
507{
508 struct ieee80211_tx_queue_stats_data *current_queue;
509 struct p54_common *priv = dev->priv;
510 struct p54_control_hdr *hdr;
511 struct p54_tx_control_allocdata *txhdr;
512 struct ieee80211_tx_control *control_copy;
513 size_t padding, len;
514 u8 rate;
515
516 current_queue = &priv->tx_stats.data[control->queue];
517 if (unlikely(current_queue->len > current_queue->limit))
518 return NETDEV_TX_BUSY;
519 current_queue->len++;
520 current_queue->count++;
521 if (current_queue->len == current_queue->limit)
522 ieee80211_stop_queue(dev, control->queue);
523
524 padding = (unsigned long)(skb->data - (sizeof(*hdr) + sizeof(*txhdr))) & 3;
525 len = skb->len;
526
527 control_copy = kmalloc(sizeof(*control), GFP_ATOMIC);
528 if (control_copy)
529 memcpy(control_copy, control, sizeof(*control));
530
531 txhdr = (struct p54_tx_control_allocdata *)
532 skb_push(skb, sizeof(*txhdr) + padding);
533 hdr = (struct p54_control_hdr *) skb_push(skb, sizeof(*hdr));
534
535 if (padding)
536 hdr->magic1 = cpu_to_le16(0x4010);
537 else
538 hdr->magic1 = cpu_to_le16(0x0010);
539 hdr->len = cpu_to_le16(len);
540 hdr->type = (control->flags & IEEE80211_TXCTL_NO_ACK) ? 0 : cpu_to_le16(1);
541 hdr->retry1 = hdr->retry2 = control->retry_limit;
542 p54_assign_address(dev, skb, hdr, skb->len, control_copy);
543
544 memset(txhdr->wep_key, 0x0, 16);
545 txhdr->padding = 0;
546 txhdr->padding2 = 0;
547
548 /* TODO: add support for alternate retry TX rates */
549 rate = control->tx_rate;
550 if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS)
551 rate |= 0x40;
552 else if (control->flags & IEEE80211_TXCTL_USE_CTS_PROTECT)
553 rate |= 0x20;
554 memset(txhdr->rateset, rate, 8);
555 txhdr->wep_key_present = 0;
556 txhdr->wep_key_len = 0;
557 txhdr->frame_type = cpu_to_le32(control->queue + 4);
558 txhdr->magic4 = 0;
559 txhdr->antenna = (control->antenna_sel_tx == 0) ?
560 2 : control->antenna_sel_tx - 1;
561 txhdr->output_power = 0x7f; // HW Maximum
562 txhdr->magic5 = (control->flags & IEEE80211_TXCTL_NO_ACK) ?
563 0 : ((rate > 0x3) ? cpu_to_le32(0x33) : cpu_to_le32(0x23));
564 if (padding)
565 txhdr->align[0] = padding;
566
567 priv->tx(dev, hdr, skb->len, 0);
568 return 0;
569}
570
571static int p54_set_filter(struct ieee80211_hw *dev, u16 filter_type,
572 const u8 *dst, const u8 *src, u8 antenna,
573 u32 magic3, u32 magic8, u32 magic9)
574{
575 struct p54_common *priv = dev->priv;
576 struct p54_control_hdr *hdr;
577 struct p54_tx_control_filter *filter;
578
579 hdr = kzalloc(sizeof(*hdr) + sizeof(*filter) +
580 priv->tx_hdr_len, GFP_ATOMIC);
581 if (!hdr)
582 return -ENOMEM;
583
584 hdr = (void *)hdr + priv->tx_hdr_len;
585
586 filter = (struct p54_tx_control_filter *) hdr->data;
587 hdr->magic1 = cpu_to_le16(0x8001);
588 hdr->len = cpu_to_le16(sizeof(*filter));
589 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*filter), NULL);
590 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_FILTER_SET);
591
592 filter->filter_type = cpu_to_le16(filter_type);
593 memcpy(filter->dst, dst, ETH_ALEN);
594 if (!src)
595 memset(filter->src, ~0, ETH_ALEN);
596 else
597 memcpy(filter->src, src, ETH_ALEN);
598 filter->antenna = antenna;
599 filter->magic3 = cpu_to_le32(magic3);
600 filter->rx_addr = cpu_to_le32(priv->rx_end);
601 filter->max_rx = cpu_to_le16(0x0620); /* FIXME: for usb ver 1.. maybe */
602 filter->rxhw = priv->rxhw;
603 filter->magic8 = cpu_to_le16(magic8);
604 filter->magic9 = cpu_to_le16(magic9);
605
606 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*filter), 1);
607 return 0;
608}
609
610static int p54_set_freq(struct ieee80211_hw *dev, __le16 freq)
611{
612 struct p54_common *priv = dev->priv;
613 struct p54_control_hdr *hdr;
614 struct p54_tx_control_channel *chan;
615 unsigned int i;
616 size_t payload_len = sizeof(*chan) + sizeof(u32)*2 +
617 sizeof(*chan->curve_data) *
618 priv->curve_data->points_per_channel;
619 void *entry;
620
621 hdr = kzalloc(sizeof(*hdr) + payload_len +
622 priv->tx_hdr_len, GFP_KERNEL);
623 if (!hdr)
624 return -ENOMEM;
625
626 hdr = (void *)hdr + priv->tx_hdr_len;
627
628 chan = (struct p54_tx_control_channel *) hdr->data;
629
630 hdr->magic1 = cpu_to_le16(0x8001);
631 hdr->len = cpu_to_le16(sizeof(*chan));
632 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_CHANNEL_CHANGE);
633 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + payload_len, NULL);
634
635 chan->magic1 = cpu_to_le16(0x1);
636 chan->magic2 = cpu_to_le16(0x0);
637
638 for (i = 0; i < priv->iq_autocal_len; i++) {
639 if (priv->iq_autocal[i].freq != freq)
640 continue;
641
642 memcpy(&chan->iq_autocal, &priv->iq_autocal[i],
643 sizeof(*priv->iq_autocal));
644 break;
645 }
646 if (i == priv->iq_autocal_len)
647 goto err;
648
649 for (i = 0; i < priv->output_limit_len; i++) {
650 if (priv->output_limit[i].freq != freq)
651 continue;
652
653 chan->val_barker = 0x38;
654 chan->val_bpsk = priv->output_limit[i].val_bpsk;
655 chan->val_qpsk = priv->output_limit[i].val_qpsk;
656 chan->val_16qam = priv->output_limit[i].val_16qam;
657 chan->val_64qam = priv->output_limit[i].val_64qam;
658 break;
659 }
660 if (i == priv->output_limit_len)
661 goto err;
662
663 chan->pa_points_per_curve = priv->curve_data->points_per_channel;
664
665 entry = priv->curve_data->data;
666 for (i = 0; i < priv->curve_data->channels; i++) {
667 if (*((__le16 *)entry) != freq) {
668 entry += sizeof(__le16);
669 entry += sizeof(struct pda_pa_curve_data_sample_rev1) *
670 chan->pa_points_per_curve;
671 continue;
672 }
673
674 entry += sizeof(__le16);
675 memcpy(chan->curve_data, entry, sizeof(*chan->curve_data) *
676 chan->pa_points_per_curve);
677 break;
678 }
679
680 memcpy(hdr->data + payload_len - 4, &chan->val_bpsk, 4);
681
682 priv->tx(dev, hdr, sizeof(*hdr) + payload_len, 1);
683 return 0;
684
685 err:
686 printk(KERN_ERR "%s: frequency change failed\n", wiphy_name(dev->wiphy));
687 kfree(hdr);
688 return -EINVAL;
689}
690
691static int p54_set_leds(struct ieee80211_hw *dev, int mode, int link, int act)
692{
693 struct p54_common *priv = dev->priv;
694 struct p54_control_hdr *hdr;
695 struct p54_tx_control_led *led;
696
697 hdr = kzalloc(sizeof(*hdr) + sizeof(*led) +
698 priv->tx_hdr_len, GFP_KERNEL);
699 if (!hdr)
700 return -ENOMEM;
701
702 hdr = (void *)hdr + priv->tx_hdr_len;
703 hdr->magic1 = cpu_to_le16(0x8001);
704 hdr->len = cpu_to_le16(sizeof(*led));
705 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_LED);
706 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*led), NULL);
707
708 led = (struct p54_tx_control_led *) hdr->data;
709 led->mode = cpu_to_le16(mode);
710 led->led_permanent = cpu_to_le16(link);
711 led->led_temporary = cpu_to_le16(act);
712 led->duration = cpu_to_le16(1000);
713
714 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*led), 1);
715
716 return 0;
717}
718
719#define P54_SET_QUEUE(queue, ai_fs, cw_min, cw_max, burst) \
720do { \
721 queue.aifs = cpu_to_le16(ai_fs); \
722 queue.cwmin = cpu_to_le16(cw_min); \
723 queue.cwmax = cpu_to_le16(cw_max); \
724 queue.txop = (burst == 0) ? \
725 0 : cpu_to_le16((burst * 100) / 32 + 1); \
726} while(0)
727
728static void p54_init_vdcf(struct ieee80211_hw *dev)
729{
730 struct p54_common *priv = dev->priv;
731 struct p54_control_hdr *hdr;
732 struct p54_tx_control_vdcf *vdcf;
733
734 /* all USB V1 adapters need a extra headroom */
735 hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len;
736 hdr->magic1 = cpu_to_le16(0x8001);
737 hdr->len = cpu_to_le16(sizeof(*vdcf));
738 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_DCFINIT);
739 hdr->req_id = cpu_to_le32(priv->rx_start);
740
741 vdcf = (struct p54_tx_control_vdcf *) hdr->data;
742
743 P54_SET_QUEUE(vdcf->queue[0], 0x0002, 0x0003, 0x0007, 0x000f);
744 P54_SET_QUEUE(vdcf->queue[1], 0x0002, 0x0007, 0x000f, 0x001e);
745 P54_SET_QUEUE(vdcf->queue[2], 0x0002, 0x000f, 0x03ff, 0x0014);
746 P54_SET_QUEUE(vdcf->queue[3], 0x0007, 0x000f, 0x03ff, 0x0000);
747}
748
749static void p54_set_vdcf(struct ieee80211_hw *dev)
750{
751 struct p54_common *priv = dev->priv;
752 struct p54_control_hdr *hdr;
753 struct p54_tx_control_vdcf *vdcf;
754
755 hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len;
756
757 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*vdcf), NULL);
758
759 vdcf = (struct p54_tx_control_vdcf *) hdr->data;
760
761 if (dev->conf.flags & IEEE80211_CONF_SHORT_SLOT_TIME) {
762 vdcf->slottime = 9;
763 vdcf->magic1 = 0x00;
764 vdcf->magic2 = 0x10;
765 } else {
766 vdcf->slottime = 20;
767 vdcf->magic1 = 0x0a;
768 vdcf->magic2 = 0x06;
769 }
770
771 /* (see prism54/isl_oid.h for further details) */
772 vdcf->frameburst = cpu_to_le16(0);
773
774 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*vdcf), 0);
775}
776
777static int p54_start(struct ieee80211_hw *dev)
778{
779 struct p54_common *priv = dev->priv;
780 int err;
781
782 err = priv->open(dev);
783 if (!err)
784 priv->mode = IEEE80211_IF_TYPE_MNTR;
785
786 return err;
787}
788
789static void p54_stop(struct ieee80211_hw *dev)
790{
791 struct p54_common *priv = dev->priv;
792 struct sk_buff *skb;
793 while ((skb = skb_dequeue(&priv->tx_queue))) {
794 struct memrecord *range = (struct memrecord *)&skb->cb;
795 if (range->control)
796 kfree(range->control);
797 kfree_skb(skb);
798 }
799 priv->stop(dev);
800 priv->mode = IEEE80211_IF_TYPE_INVALID;
801}
802
803static int p54_add_interface(struct ieee80211_hw *dev,
804 struct ieee80211_if_init_conf *conf)
805{
806 struct p54_common *priv = dev->priv;
807
808 if (priv->mode != IEEE80211_IF_TYPE_MNTR)
809 return -EOPNOTSUPP;
810
811 switch (conf->type) {
812 case IEEE80211_IF_TYPE_STA:
813 priv->mode = conf->type;
814 break;
815 default:
816 return -EOPNOTSUPP;
817 }
818
819 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
820
821 p54_set_filter(dev, 0, priv->mac_addr, NULL, 0, 1, 0, 0xF642);
822 p54_set_filter(dev, 0, priv->mac_addr, NULL, 1, 0, 0, 0xF642);
823
824 switch (conf->type) {
825 case IEEE80211_IF_TYPE_STA:
826 p54_set_filter(dev, 1, priv->mac_addr, NULL, 0, 0x15F, 0x1F4, 0);
827 break;
828 default:
829 BUG(); /* impossible */
830 break;
831 }
832
833 p54_set_leds(dev, 1, 0, 0);
834
835 return 0;
836}
837
838static void p54_remove_interface(struct ieee80211_hw *dev,
839 struct ieee80211_if_init_conf *conf)
840{
841 struct p54_common *priv = dev->priv;
842 priv->mode = IEEE80211_IF_TYPE_MNTR;
843 memset(priv->mac_addr, 0, ETH_ALEN);
844 p54_set_filter(dev, 0, priv->mac_addr, NULL, 2, 0, 0, 0);
845}
846
847static int p54_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
848{
849 int ret;
850
851 ret = p54_set_freq(dev, cpu_to_le16(conf->freq));
852 p54_set_vdcf(dev);
853 return ret;
854}
855
856static int p54_config_interface(struct ieee80211_hw *dev, int if_id,
857 struct ieee80211_if_conf *conf)
858{
859 struct p54_common *priv = dev->priv;
860
861 p54_set_filter(dev, 0, priv->mac_addr, conf->bssid, 0, 1, 0, 0xF642);
862 p54_set_filter(dev, 0, priv->mac_addr, conf->bssid, 2, 0, 0, 0);
863 p54_set_leds(dev, 1, !is_multicast_ether_addr(conf->bssid), 0);
864 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
865 return 0;
866}
867
868static void p54_configure_filter(struct ieee80211_hw *dev,
869 unsigned int changed_flags,
870 unsigned int *total_flags,
871 int mc_count, struct dev_mc_list *mclist)
872{
873 struct p54_common *priv = dev->priv;
874
875 *total_flags &= FIF_BCN_PRBRESP_PROMISC;
876
877 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
878 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
879 p54_set_filter(dev, 0, priv->mac_addr,
880 NULL, 2, 0, 0, 0);
881 else
882 p54_set_filter(dev, 0, priv->mac_addr,
883 priv->bssid, 2, 0, 0, 0);
884 }
885}
886
887static int p54_conf_tx(struct ieee80211_hw *dev, int queue,
888 const struct ieee80211_tx_queue_params *params)
889{
890 struct p54_common *priv = dev->priv;
891 struct p54_tx_control_vdcf *vdcf;
892
893 vdcf = (struct p54_tx_control_vdcf *)(((struct p54_control_hdr *)
894 ((void *)priv->cached_vdcf + priv->tx_hdr_len))->data);
895
896 if ((params) && !((queue < 0) || (queue > 4))) {
897 P54_SET_QUEUE(vdcf->queue[queue], params->aifs,
898 params->cw_min, params->cw_max, params->burst_time);
899 } else
900 return -EINVAL;
901
902 p54_set_vdcf(dev);
903
904 return 0;
905}
906
907static int p54_get_stats(struct ieee80211_hw *dev,
908 struct ieee80211_low_level_stats *stats)
909{
910 /* TODO */
911 return 0;
912}
913
914static int p54_get_tx_stats(struct ieee80211_hw *dev,
915 struct ieee80211_tx_queue_stats *stats)
916{
917 struct p54_common *priv = dev->priv;
918 unsigned int i;
919
920 for (i = 0; i < dev->queues; i++)
921 memcpy(&stats->data[i], &priv->tx_stats.data[i],
922 sizeof(stats->data[i]));
923
924 return 0;
925}
926
927static const struct ieee80211_ops p54_ops = {
928 .tx = p54_tx,
929 .start = p54_start,
930 .stop = p54_stop,
931 .add_interface = p54_add_interface,
932 .remove_interface = p54_remove_interface,
933 .config = p54_config,
934 .config_interface = p54_config_interface,
935 .configure_filter = p54_configure_filter,
936 .conf_tx = p54_conf_tx,
937 .get_stats = p54_get_stats,
938 .get_tx_stats = p54_get_tx_stats
939};
940
941struct ieee80211_hw *p54_init_common(size_t priv_data_len)
942{
943 struct ieee80211_hw *dev;
944 struct p54_common *priv;
945 int i;
946
947 dev = ieee80211_alloc_hw(priv_data_len, &p54_ops);
948 if (!dev)
949 return NULL;
950
951 priv = dev->priv;
952 priv->mode = IEEE80211_IF_TYPE_INVALID;
953 skb_queue_head_init(&priv->tx_queue);
954 memcpy(priv->channels, p54_channels, sizeof(p54_channels));
955 memcpy(priv->rates, p54_rates, sizeof(p54_rates));
956 priv->modes[1].mode = MODE_IEEE80211B;
957 priv->modes[1].num_rates = 4;
958 priv->modes[1].rates = priv->rates;
959 priv->modes[1].num_channels = ARRAY_SIZE(p54_channels);
960 priv->modes[1].channels = priv->channels;
961 priv->modes[0].mode = MODE_IEEE80211G;
962 priv->modes[0].num_rates = ARRAY_SIZE(p54_rates);
963 priv->modes[0].rates = priv->rates;
964 priv->modes[0].num_channels = ARRAY_SIZE(p54_channels);
965 priv->modes[0].channels = priv->channels;
966 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | /* not sure */
967 IEEE80211_HW_RX_INCLUDES_FCS;
968 dev->channel_change_time = 1000; /* TODO: find actual value */
969 dev->max_rssi = 127;
970
971 priv->tx_stats.data[0].limit = 5;
972 dev->queues = 1;
973
974 dev->extra_tx_headroom = sizeof(struct p54_control_hdr) + 4 +
975 sizeof(struct p54_tx_control_allocdata);
976
977 priv->cached_vdcf = kzalloc(sizeof(struct p54_tx_control_vdcf) +
978 priv->tx_hdr_len + sizeof(struct p54_control_hdr), GFP_KERNEL);
979
980 if (!priv->cached_vdcf) {
981 ieee80211_free_hw(dev);
982 return NULL;
983 }
984
985 p54_init_vdcf(dev);
986
987 for (i = 0; i < 2; i++) {
988 if (ieee80211_register_hwmode(dev, &priv->modes[i])) {
989 kfree(priv->cached_vdcf);
990 ieee80211_free_hw(dev);
991 return NULL;
992 }
993 }
994
995 return dev;
996}
997EXPORT_SYMBOL_GPL(p54_init_common);
998
999void p54_free_common(struct ieee80211_hw *dev)
1000{
1001 struct p54_common *priv = dev->priv;
1002 kfree(priv->iq_autocal);
1003 kfree(priv->output_limit);
1004 kfree(priv->curve_data);
1005 kfree(priv->cached_vdcf);
1006}
1007EXPORT_SYMBOL_GPL(p54_free_common);
1008
1009static int __init p54_init(void)
1010{
1011 return 0;
1012}
1013
1014static void __exit p54_exit(void)
1015{
1016}
1017
1018module_init(p54_init);
1019module_exit(p54_exit);