tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1#ifndef VMX_H
2#define VMX_H
3
4/*
5 * vmx.h: VMX Architecture related definitions
6 * Copyright (c) 2004, Intel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
19 * Place - Suite 330, Boston, MA 02111-1307 USA.
20 *
21 * A few random additions are:
22 * Copyright (C) 2006 Qumranet
23 * Avi Kivity <avi@qumranet.com>
24 * Yaniv Kamay <yaniv@qumranet.com>
25 *
26 */
27
28#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
29#define CPU_BASED_USE_TSC_OFFSETING 0x00000008
30#define CPU_BASED_HLT_EXITING 0x00000080
31#define CPU_BASED_INVLPG_EXITING 0x00000200
32#define CPU_BASED_MWAIT_EXITING 0x00000400
33#define CPU_BASED_RDPMC_EXITING 0x00000800
34#define CPU_BASED_RDTSC_EXITING 0x00001000
35#define CPU_BASED_CR8_LOAD_EXITING 0x00080000
36#define CPU_BASED_CR8_STORE_EXITING 0x00100000
37#define CPU_BASED_TPR_SHADOW 0x00200000
38#define CPU_BASED_MOV_DR_EXITING 0x00800000
39#define CPU_BASED_UNCOND_IO_EXITING 0x01000000
40#define CPU_BASED_USE_IO_BITMAPS 0x02000000
41#define CPU_BASED_USE_MSR_BITMAPS 0x10000000
42#define CPU_BASED_MONITOR_EXITING 0x20000000
43#define CPU_BASED_PAUSE_EXITING 0x40000000
44#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
45
46#define PIN_BASED_EXT_INTR_MASK 0x00000001
47#define PIN_BASED_NMI_EXITING 0x00000008
48#define PIN_BASED_VIRTUAL_NMIS 0x00000020
49
50#define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
51#define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
52
53#define VM_ENTRY_IA32E_MODE 0x00000200
54#define VM_ENTRY_SMM 0x00000400
55#define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
56
57#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
58
59/* VMCS Encodings */
60enum vmcs_field {
61 GUEST_ES_SELECTOR = 0x00000800,
62 GUEST_CS_SELECTOR = 0x00000802,
63 GUEST_SS_SELECTOR = 0x00000804,
64 GUEST_DS_SELECTOR = 0x00000806,
65 GUEST_FS_SELECTOR = 0x00000808,
66 GUEST_GS_SELECTOR = 0x0000080a,
67 GUEST_LDTR_SELECTOR = 0x0000080c,
68 GUEST_TR_SELECTOR = 0x0000080e,
69 HOST_ES_SELECTOR = 0x00000c00,
70 HOST_CS_SELECTOR = 0x00000c02,
71 HOST_SS_SELECTOR = 0x00000c04,
72 HOST_DS_SELECTOR = 0x00000c06,
73 HOST_FS_SELECTOR = 0x00000c08,
74 HOST_GS_SELECTOR = 0x00000c0a,
75 HOST_TR_SELECTOR = 0x00000c0c,
76 IO_BITMAP_A = 0x00002000,
77 IO_BITMAP_A_HIGH = 0x00002001,
78 IO_BITMAP_B = 0x00002002,
79 IO_BITMAP_B_HIGH = 0x00002003,
80 MSR_BITMAP = 0x00002004,
81 MSR_BITMAP_HIGH = 0x00002005,
82 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
83 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
84 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
85 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
86 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
87 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
88 TSC_OFFSET = 0x00002010,
89 TSC_OFFSET_HIGH = 0x00002011,
90 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
91 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
92 VMCS_LINK_POINTER = 0x00002800,
93 VMCS_LINK_POINTER_HIGH = 0x00002801,
94 GUEST_IA32_DEBUGCTL = 0x00002802,
95 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
96 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
97 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
98 EXCEPTION_BITMAP = 0x00004004,
99 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
100 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
101 CR3_TARGET_COUNT = 0x0000400a,
102 VM_EXIT_CONTROLS = 0x0000400c,
103 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
104 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
105 VM_ENTRY_CONTROLS = 0x00004012,
106 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
107 VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
108 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
109 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
110 TPR_THRESHOLD = 0x0000401c,
111 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
112 VM_INSTRUCTION_ERROR = 0x00004400,
113 VM_EXIT_REASON = 0x00004402,
114 VM_EXIT_INTR_INFO = 0x00004404,
115 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
116 IDT_VECTORING_INFO_FIELD = 0x00004408,
117 IDT_VECTORING_ERROR_CODE = 0x0000440a,
118 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
119 VMX_INSTRUCTION_INFO = 0x0000440e,
120 GUEST_ES_LIMIT = 0x00004800,
121 GUEST_CS_LIMIT = 0x00004802,
122 GUEST_SS_LIMIT = 0x00004804,
123 GUEST_DS_LIMIT = 0x00004806,
124 GUEST_FS_LIMIT = 0x00004808,
125 GUEST_GS_LIMIT = 0x0000480a,
126 GUEST_LDTR_LIMIT = 0x0000480c,
127 GUEST_TR_LIMIT = 0x0000480e,
128 GUEST_GDTR_LIMIT = 0x00004810,
129 GUEST_IDTR_LIMIT = 0x00004812,
130 GUEST_ES_AR_BYTES = 0x00004814,
131 GUEST_CS_AR_BYTES = 0x00004816,
132 GUEST_SS_AR_BYTES = 0x00004818,
133 GUEST_DS_AR_BYTES = 0x0000481a,
134 GUEST_FS_AR_BYTES = 0x0000481c,
135 GUEST_GS_AR_BYTES = 0x0000481e,
136 GUEST_LDTR_AR_BYTES = 0x00004820,
137 GUEST_TR_AR_BYTES = 0x00004822,
138 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
139 GUEST_ACTIVITY_STATE = 0X00004826,
140 GUEST_SYSENTER_CS = 0x0000482A,
141 HOST_IA32_SYSENTER_CS = 0x00004c00,
142 CR0_GUEST_HOST_MASK = 0x00006000,
143 CR4_GUEST_HOST_MASK = 0x00006002,
144 CR0_READ_SHADOW = 0x00006004,
145 CR4_READ_SHADOW = 0x00006006,
146 CR3_TARGET_VALUE0 = 0x00006008,
147 CR3_TARGET_VALUE1 = 0x0000600a,
148 CR3_TARGET_VALUE2 = 0x0000600c,
149 CR3_TARGET_VALUE3 = 0x0000600e,
150 EXIT_QUALIFICATION = 0x00006400,
151 GUEST_LINEAR_ADDRESS = 0x0000640a,
152 GUEST_CR0 = 0x00006800,
153 GUEST_CR3 = 0x00006802,
154 GUEST_CR4 = 0x00006804,
155 GUEST_ES_BASE = 0x00006806,
156 GUEST_CS_BASE = 0x00006808,
157 GUEST_SS_BASE = 0x0000680a,
158 GUEST_DS_BASE = 0x0000680c,
159 GUEST_FS_BASE = 0x0000680e,
160 GUEST_GS_BASE = 0x00006810,
161 GUEST_LDTR_BASE = 0x00006812,
162 GUEST_TR_BASE = 0x00006814,
163 GUEST_GDTR_BASE = 0x00006816,
164 GUEST_IDTR_BASE = 0x00006818,
165 GUEST_DR7 = 0x0000681a,
166 GUEST_RSP = 0x0000681c,
167 GUEST_RIP = 0x0000681e,
168 GUEST_RFLAGS = 0x00006820,
169 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
170 GUEST_SYSENTER_ESP = 0x00006824,
171 GUEST_SYSENTER_EIP = 0x00006826,
172 HOST_CR0 = 0x00006c00,
173 HOST_CR3 = 0x00006c02,
174 HOST_CR4 = 0x00006c04,
175 HOST_FS_BASE = 0x00006c06,
176 HOST_GS_BASE = 0x00006c08,
177 HOST_TR_BASE = 0x00006c0a,
178 HOST_GDTR_BASE = 0x00006c0c,
179 HOST_IDTR_BASE = 0x00006c0e,
180 HOST_IA32_SYSENTER_ESP = 0x00006c10,
181 HOST_IA32_SYSENTER_EIP = 0x00006c12,
182 HOST_RSP = 0x00006c14,
183 HOST_RIP = 0x00006c16,
184};
185
186#define VMX_EXIT_REASONS_FAILED_VMENTRY 0x80000000
187
188#define EXIT_REASON_EXCEPTION_NMI 0
189#define EXIT_REASON_EXTERNAL_INTERRUPT 1
190#define EXIT_REASON_TRIPLE_FAULT 2
191
192#define EXIT_REASON_PENDING_INTERRUPT 7
193
194#define EXIT_REASON_TASK_SWITCH 9
195#define EXIT_REASON_CPUID 10
196#define EXIT_REASON_HLT 12
197#define EXIT_REASON_INVLPG 14
198#define EXIT_REASON_RDPMC 15
199#define EXIT_REASON_RDTSC 16
200#define EXIT_REASON_VMCALL 18
201#define EXIT_REASON_VMCLEAR 19
202#define EXIT_REASON_VMLAUNCH 20
203#define EXIT_REASON_VMPTRLD 21
204#define EXIT_REASON_VMPTRST 22
205#define EXIT_REASON_VMREAD 23
206#define EXIT_REASON_VMRESUME 24
207#define EXIT_REASON_VMWRITE 25
208#define EXIT_REASON_VMOFF 26
209#define EXIT_REASON_VMON 27
210#define EXIT_REASON_CR_ACCESS 28
211#define EXIT_REASON_DR_ACCESS 29
212#define EXIT_REASON_IO_INSTRUCTION 30
213#define EXIT_REASON_MSR_READ 31
214#define EXIT_REASON_MSR_WRITE 32
215#define EXIT_REASON_MWAIT_INSTRUCTION 36
216#define EXIT_REASON_TPR_BELOW_THRESHOLD 43
217
218/*
219 * Interruption-information format
220 */
221#define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
222#define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
223#define INTR_INFO_DELIEVER_CODE_MASK 0x800 /* 11 */
224#define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
225
226#define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK
227#define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK
228#define VECTORING_INFO_DELIEVER_CODE_MASK INTR_INFO_DELIEVER_CODE_MASK
229#define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK
230
231#define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */
232#define INTR_TYPE_EXCEPTION (3 << 8) /* processor exception */
233
234/*
235 * Exit Qualifications for MOV for Control Register Access
236 */
237#define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control register */
238#define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
239#define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose register */
240#define LMSW_SOURCE_DATA_SHIFT 16
241#define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
242#define REG_EAX (0 << 8)
243#define REG_ECX (1 << 8)
244#define REG_EDX (2 << 8)
245#define REG_EBX (3 << 8)
246#define REG_ESP (4 << 8)
247#define REG_EBP (5 << 8)
248#define REG_ESI (6 << 8)
249#define REG_EDI (7 << 8)
250#define REG_R8 (8 << 8)
251#define REG_R9 (9 << 8)
252#define REG_R10 (10 << 8)
253#define REG_R11 (11 << 8)
254#define REG_R12 (12 << 8)
255#define REG_R13 (13 << 8)
256#define REG_R14 (14 << 8)
257#define REG_R15 (15 << 8)
258
259/*
260 * Exit Qualifications for MOV for Debug Register Access
261 */
262#define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug register */
263#define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
264#define TYPE_MOV_TO_DR (0 << 4)
265#define TYPE_MOV_FROM_DR (1 << 4)
266#define DEBUG_REG_ACCESS_REG 0xf00 /* 11:8, general purpose register */
267
268
269/* segment AR */
270#define SEGMENT_AR_L_MASK (1 << 13)
271
272#define AR_TYPE_ACCESSES_MASK 1
273#define AR_TYPE_READABLE_MASK (1 << 1)
274#define AR_TYPE_WRITEABLE_MASK (1 << 2)
275#define AR_TYPE_CODE_MASK (1 << 3)
276#define AR_TYPE_MASK 0x0f
277#define AR_TYPE_BUSY_64_TSS 11
278#define AR_TYPE_BUSY_32_TSS 11
279#define AR_TYPE_BUSY_16_TSS 3
280#define AR_TYPE_LDT 2
281
282#define AR_UNUSABLE_MASK (1 << 16)
283#define AR_S_MASK (1 << 4)
284#define AR_P_MASK (1 << 7)
285#define AR_L_MASK (1 << 13)
286#define AR_DB_MASK (1 << 14)
287#define AR_G_MASK (1 << 15)
288#define AR_DPL_SHIFT 5
289#define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
290
291#define AR_RESERVD_MASK 0xfffe0f00
292
293#define MSR_IA32_VMX_BASIC 0x480
294#define MSR_IA32_VMX_PINBASED_CTLS 0x481
295#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
296#define MSR_IA32_VMX_EXIT_CTLS 0x483
297#define MSR_IA32_VMX_ENTRY_CTLS 0x484
298#define MSR_IA32_VMX_MISC 0x485
299#define MSR_IA32_VMX_CR0_FIXED0 0x486
300#define MSR_IA32_VMX_CR0_FIXED1 0x487
301#define MSR_IA32_VMX_CR4_FIXED0 0x488
302#define MSR_IA32_VMX_CR4_FIXED1 0x489
303#define MSR_IA32_VMX_VMCS_ENUM 0x48a
304#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48b
305
306#define MSR_IA32_FEATURE_CONTROL 0x3a
307#define MSR_IA32_FEATURE_CONTROL_LOCKED 0x1
308#define MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED 0x4
309
310#endif