tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3 */
4#ifndef _ASM_POWERPC_SYSTEM_H
5#define _ASM_POWERPC_SYSTEM_H
6
7#include <linux/kernel.h>
8
9#include <asm/hw_irq.h>
10
11/*
12 * Memory barrier.
13 * The sync instruction guarantees that all memory accesses initiated
14 * by this processor have been performed (with respect to all other
15 * mechanisms that access memory). The eieio instruction is a barrier
16 * providing an ordering (separately) for (a) cacheable stores and (b)
17 * loads and stores to non-cacheable memory (e.g. I/O devices).
18 *
19 * mb() prevents loads and stores being reordered across this point.
20 * rmb() prevents loads being reordered across this point.
21 * wmb() prevents stores being reordered across this point.
22 * read_barrier_depends() prevents data-dependent loads being reordered
23 * across this point (nop on PPC).
24 *
25 * We have to use the sync instructions for mb(), since lwsync doesn't
26 * order loads with respect to previous stores. Lwsync is fine for
27 * rmb(), though. Note that rmb() actually uses a sync on 32-bit
28 * architectures.
29 *
30 * For wmb(), we use sync since wmb is used in drivers to order
31 * stores to system memory with respect to writes to the device.
32 * However, smp_wmb() can be a lighter-weight eieio barrier on
33 * SMP since it is only used to order updates to system memory.
34 */
35#define mb() __asm__ __volatile__ ("sync" : : : "memory")
36#define rmb() __asm__ __volatile__ (__stringify(LWSYNC) : : : "memory")
37#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
38#define read_barrier_depends() do { } while(0)
39
40#define set_mb(var, value) do { var = value; mb(); } while (0)
41
42#ifdef __KERNEL__
43#define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
44#ifdef CONFIG_SMP
45#define smp_mb() mb()
46#define smp_rmb() rmb()
47#define smp_wmb() eieio()
48#define smp_read_barrier_depends() read_barrier_depends()
49#else
50#define smp_mb() barrier()
51#define smp_rmb() barrier()
52#define smp_wmb() barrier()
53#define smp_read_barrier_depends() do { } while(0)
54#endif /* CONFIG_SMP */
55
56/*
57 * This is a barrier which prevents following instructions from being
58 * started until the value of the argument x is known. For example, if
59 * x is a variable loaded from memory, this prevents following
60 * instructions from being executed until the load has been performed.
61 */
62#define data_barrier(x) \
63 asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
64
65struct task_struct;
66struct pt_regs;
67
68#ifdef CONFIG_DEBUGGER
69
70extern int (*__debugger)(struct pt_regs *regs);
71extern int (*__debugger_ipi)(struct pt_regs *regs);
72extern int (*__debugger_bpt)(struct pt_regs *regs);
73extern int (*__debugger_sstep)(struct pt_regs *regs);
74extern int (*__debugger_iabr_match)(struct pt_regs *regs);
75extern int (*__debugger_dabr_match)(struct pt_regs *regs);
76extern int (*__debugger_fault_handler)(struct pt_regs *regs);
77
78#define DEBUGGER_BOILERPLATE(__NAME) \
79static inline int __NAME(struct pt_regs *regs) \
80{ \
81 if (unlikely(__ ## __NAME)) \
82 return __ ## __NAME(regs); \
83 return 0; \
84}
85
86DEBUGGER_BOILERPLATE(debugger)
87DEBUGGER_BOILERPLATE(debugger_ipi)
88DEBUGGER_BOILERPLATE(debugger_bpt)
89DEBUGGER_BOILERPLATE(debugger_sstep)
90DEBUGGER_BOILERPLATE(debugger_iabr_match)
91DEBUGGER_BOILERPLATE(debugger_dabr_match)
92DEBUGGER_BOILERPLATE(debugger_fault_handler)
93
94#else
95static inline int debugger(struct pt_regs *regs) { return 0; }
96static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
97static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
98static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
99static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
100static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
101static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
102#endif
103
104extern int set_dabr(unsigned long dabr);
105extern void print_backtrace(unsigned long *);
106extern void show_regs(struct pt_regs * regs);
107extern void flush_instruction_cache(void);
108extern void hard_reset_now(void);
109extern void poweroff_now(void);
110
111#ifdef CONFIG_6xx
112extern long _get_L2CR(void);
113extern long _get_L3CR(void);
114extern void _set_L2CR(unsigned long);
115extern void _set_L3CR(unsigned long);
116#else
117#define _get_L2CR() 0L
118#define _get_L3CR() 0L
119#define _set_L2CR(val) do { } while(0)
120#define _set_L3CR(val) do { } while(0)
121#endif
122
123extern void via_cuda_init(void);
124extern void read_rtc_time(void);
125extern void pmac_find_display(void);
126extern void giveup_fpu(struct task_struct *);
127extern void disable_kernel_fp(void);
128extern void enable_kernel_fp(void);
129extern void flush_fp_to_thread(struct task_struct *);
130extern void enable_kernel_altivec(void);
131extern void giveup_altivec(struct task_struct *);
132extern void load_up_altivec(struct task_struct *);
133extern int emulate_altivec(struct pt_regs *);
134extern void enable_kernel_spe(void);
135extern void giveup_spe(struct task_struct *);
136extern void load_up_spe(struct task_struct *);
137extern int fix_alignment(struct pt_regs *);
138extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
139extern void cvt_df(double *from, float *to, struct thread_struct *thread);
140
141#ifndef CONFIG_SMP
142extern void discard_lazy_cpu_state(void);
143#else
144static inline void discard_lazy_cpu_state(void)
145{
146}
147#endif
148
149#ifdef CONFIG_ALTIVEC
150extern void flush_altivec_to_thread(struct task_struct *);
151#else
152static inline void flush_altivec_to_thread(struct task_struct *t)
153{
154}
155#endif
156
157#ifdef CONFIG_SPE
158extern void flush_spe_to_thread(struct task_struct *);
159#else
160static inline void flush_spe_to_thread(struct task_struct *t)
161{
162}
163#endif
164
165extern int call_rtas(const char *, int, int, unsigned long *, ...);
166extern void cacheable_memzero(void *p, unsigned int nb);
167extern void *cacheable_memcpy(void *, const void *, unsigned int);
168extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
169extern void bad_page_fault(struct pt_regs *, unsigned long, int);
170extern int die(const char *, struct pt_regs *, long);
171extern void _exception(int, struct pt_regs *, int, unsigned long);
172#ifdef CONFIG_BOOKE_WDT
173extern u32 booke_wdt_enabled;
174extern u32 booke_wdt_period;
175#endif /* CONFIG_BOOKE_WDT */
176
177struct device_node;
178extern void note_scsi_host(struct device_node *, void *);
179
180extern struct task_struct *__switch_to(struct task_struct *,
181 struct task_struct *);
182#define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
183
184struct thread_struct;
185extern struct task_struct *_switch(struct thread_struct *prev,
186 struct thread_struct *next);
187
188extern unsigned int rtas_data;
189extern int mem_init_done; /* set on boot once kmalloc can be called */
190extern unsigned long memory_limit;
191extern unsigned long klimit;
192
193extern void *alloc_maybe_bootmem(size_t size, gfp_t mask);
194extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
195
196extern int powersave_nap; /* set if nap mode can be used in idle loop */
197
198/*
199 * Atomic exchange
200 *
201 * Changes the memory location '*ptr' to be val and returns
202 * the previous value stored there.
203 */
204static __inline__ unsigned long
205__xchg_u32(volatile void *p, unsigned long val)
206{
207 unsigned long prev;
208
209 __asm__ __volatile__(
210 LWSYNC_ON_SMP
211"1: lwarx %0,0,%2 \n"
212 PPC405_ERR77(0,%2)
213" stwcx. %3,0,%2 \n\
214 bne- 1b"
215 ISYNC_ON_SMP
216 : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
217 : "r" (p), "r" (val)
218 : "cc", "memory");
219
220 return prev;
221}
222
223/*
224 * Atomic exchange
225 *
226 * Changes the memory location '*ptr' to be val and returns
227 * the previous value stored there.
228 */
229static __inline__ unsigned long
230__xchg_u32_local(volatile void *p, unsigned long val)
231{
232 unsigned long prev;
233
234 __asm__ __volatile__(
235"1: lwarx %0,0,%2 \n"
236 PPC405_ERR77(0,%2)
237" stwcx. %3,0,%2 \n\
238 bne- 1b"
239 : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
240 : "r" (p), "r" (val)
241 : "cc", "memory");
242
243 return prev;
244}
245
246#ifdef CONFIG_PPC64
247static __inline__ unsigned long
248__xchg_u64(volatile void *p, unsigned long val)
249{
250 unsigned long prev;
251
252 __asm__ __volatile__(
253 LWSYNC_ON_SMP
254"1: ldarx %0,0,%2 \n"
255 PPC405_ERR77(0,%2)
256" stdcx. %3,0,%2 \n\
257 bne- 1b"
258 ISYNC_ON_SMP
259 : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
260 : "r" (p), "r" (val)
261 : "cc", "memory");
262
263 return prev;
264}
265
266static __inline__ unsigned long
267__xchg_u64_local(volatile void *p, unsigned long val)
268{
269 unsigned long prev;
270
271 __asm__ __volatile__(
272"1: ldarx %0,0,%2 \n"
273 PPC405_ERR77(0,%2)
274" stdcx. %3,0,%2 \n\
275 bne- 1b"
276 : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
277 : "r" (p), "r" (val)
278 : "cc", "memory");
279
280 return prev;
281}
282#endif
283
284/*
285 * This function doesn't exist, so you'll get a linker error
286 * if something tries to do an invalid xchg().
287 */
288extern void __xchg_called_with_bad_pointer(void);
289
290static __inline__ unsigned long
291__xchg(volatile void *ptr, unsigned long x, unsigned int size)
292{
293 switch (size) {
294 case 4:
295 return __xchg_u32(ptr, x);
296#ifdef CONFIG_PPC64
297 case 8:
298 return __xchg_u64(ptr, x);
299#endif
300 }
301 __xchg_called_with_bad_pointer();
302 return x;
303}
304
305static __inline__ unsigned long
306__xchg_local(volatile void *ptr, unsigned long x, unsigned int size)
307{
308 switch (size) {
309 case 4:
310 return __xchg_u32_local(ptr, x);
311#ifdef CONFIG_PPC64
312 case 8:
313 return __xchg_u64_local(ptr, x);
314#endif
315 }
316 __xchg_called_with_bad_pointer();
317 return x;
318}
319#define xchg(ptr,x) \
320 ({ \
321 __typeof__(*(ptr)) _x_ = (x); \
322 (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
323 })
324
325#define xchg_local(ptr,x) \
326 ({ \
327 __typeof__(*(ptr)) _x_ = (x); \
328 (__typeof__(*(ptr))) __xchg_local((ptr), \
329 (unsigned long)_x_, sizeof(*(ptr))); \
330 })
331
332/*
333 * Compare and exchange - if *p == old, set it to new,
334 * and return the old value of *p.
335 */
336#define __HAVE_ARCH_CMPXCHG 1
337
338static __inline__ unsigned long
339__cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
340{
341 unsigned int prev;
342
343 __asm__ __volatile__ (
344 LWSYNC_ON_SMP
345"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
346 cmpw 0,%0,%3\n\
347 bne- 2f\n"
348 PPC405_ERR77(0,%2)
349" stwcx. %4,0,%2\n\
350 bne- 1b"
351 ISYNC_ON_SMP
352 "\n\
3532:"
354 : "=&r" (prev), "+m" (*p)
355 : "r" (p), "r" (old), "r" (new)
356 : "cc", "memory");
357
358 return prev;
359}
360
361static __inline__ unsigned long
362__cmpxchg_u32_local(volatile unsigned int *p, unsigned long old,
363 unsigned long new)
364{
365 unsigned int prev;
366
367 __asm__ __volatile__ (
368"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
369 cmpw 0,%0,%3\n\
370 bne- 2f\n"
371 PPC405_ERR77(0,%2)
372" stwcx. %4,0,%2\n\
373 bne- 1b"
374 "\n\
3752:"
376 : "=&r" (prev), "+m" (*p)
377 : "r" (p), "r" (old), "r" (new)
378 : "cc", "memory");
379
380 return prev;
381}
382
383#ifdef CONFIG_PPC64
384static __inline__ unsigned long
385__cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
386{
387 unsigned long prev;
388
389 __asm__ __volatile__ (
390 LWSYNC_ON_SMP
391"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
392 cmpd 0,%0,%3\n\
393 bne- 2f\n\
394 stdcx. %4,0,%2\n\
395 bne- 1b"
396 ISYNC_ON_SMP
397 "\n\
3982:"
399 : "=&r" (prev), "+m" (*p)
400 : "r" (p), "r" (old), "r" (new)
401 : "cc", "memory");
402
403 return prev;
404}
405
406static __inline__ unsigned long
407__cmpxchg_u64_local(volatile unsigned long *p, unsigned long old,
408 unsigned long new)
409{
410 unsigned long prev;
411
412 __asm__ __volatile__ (
413"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
414 cmpd 0,%0,%3\n\
415 bne- 2f\n\
416 stdcx. %4,0,%2\n\
417 bne- 1b"
418 "\n\
4192:"
420 : "=&r" (prev), "+m" (*p)
421 : "r" (p), "r" (old), "r" (new)
422 : "cc", "memory");
423
424 return prev;
425}
426#endif
427
428/* This function doesn't exist, so you'll get a linker error
429 if something tries to do an invalid cmpxchg(). */
430extern void __cmpxchg_called_with_bad_pointer(void);
431
432static __inline__ unsigned long
433__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
434 unsigned int size)
435{
436 switch (size) {
437 case 4:
438 return __cmpxchg_u32(ptr, old, new);
439#ifdef CONFIG_PPC64
440 case 8:
441 return __cmpxchg_u64(ptr, old, new);
442#endif
443 }
444 __cmpxchg_called_with_bad_pointer();
445 return old;
446}
447
448static __inline__ unsigned long
449__cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
450 unsigned int size)
451{
452 switch (size) {
453 case 4:
454 return __cmpxchg_u32_local(ptr, old, new);
455#ifdef CONFIG_PPC64
456 case 8:
457 return __cmpxchg_u64_local(ptr, old, new);
458#endif
459 }
460 __cmpxchg_called_with_bad_pointer();
461 return old;
462}
463
464#define cmpxchg(ptr,o,n) \
465 ({ \
466 __typeof__(*(ptr)) _o_ = (o); \
467 __typeof__(*(ptr)) _n_ = (n); \
468 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
469 (unsigned long)_n_, sizeof(*(ptr))); \
470 })
471
472
473#define cmpxchg_local(ptr,o,n) \
474 ({ \
475 __typeof__(*(ptr)) _o_ = (o); \
476 __typeof__(*(ptr)) _n_ = (n); \
477 (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \
478 (unsigned long)_n_, sizeof(*(ptr))); \
479 })
480
481#ifdef CONFIG_PPC64
482/*
483 * We handle most unaligned accesses in hardware. On the other hand
484 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
485 * powers of 2 writes until it reaches sufficient alignment).
486 *
487 * Based on this we disable the IP header alignment in network drivers.
488 * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
489 * cacheline alignment of buffers.
490 */
491#define NET_IP_ALIGN 0
492#define NET_SKB_PAD L1_CACHE_BYTES
493#endif
494
495#define arch_align_stack(x) (x)
496
497/* Used in very early kernel initialization. */
498extern unsigned long reloc_offset(void);
499extern unsigned long add_reloc_offset(unsigned long);
500extern void reloc_got2(unsigned long);
501
502#define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x)))
503
504static inline void create_instruction(unsigned long addr, unsigned int instr)
505{
506 unsigned int *p;
507 p = (unsigned int *)addr;
508 *p = instr;
509 asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p));
510}
511
512/* Flags for create_branch:
513 * "b" == create_branch(addr, target, 0);
514 * "ba" == create_branch(addr, target, BRANCH_ABSOLUTE);
515 * "bl" == create_branch(addr, target, BRANCH_SET_LINK);
516 * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
517 */
518#define BRANCH_SET_LINK 0x1
519#define BRANCH_ABSOLUTE 0x2
520
521static inline void create_branch(unsigned long addr,
522 unsigned long target, int flags)
523{
524 unsigned int instruction;
525
526 if (! (flags & BRANCH_ABSOLUTE))
527 target = target - addr;
528
529 /* Mask out the flags and target, so they don't step on each other. */
530 instruction = 0x48000000 | (flags & 0x3) | (target & 0x03FFFFFC);
531
532 create_instruction(addr, instruction);
533}
534
535static inline void create_function_call(unsigned long addr, void * func)
536{
537 unsigned long func_addr;
538
539#ifdef CONFIG_PPC64
540 /*
541 * On PPC64 the function pointer actually points to the function's
542 * descriptor. The first entry in the descriptor is the address
543 * of the function text.
544 */
545 func_addr = *(unsigned long *)func;
546#else
547 func_addr = (unsigned long)func;
548#endif
549 create_branch(addr, func_addr, BRANCH_SET_LINK);
550}
551
552#ifdef CONFIG_VIRT_CPU_ACCOUNTING
553extern void account_system_vtime(struct task_struct *);
554#endif
555
556extern struct dentry *powerpc_debugfs_root;
557
558#endif /* __KERNEL__ */
559#endif /* _ASM_POWERPC_SYSTEM_H */