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Linux kernel mirror (for testing)
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1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
4#include <asm/asm-compat.h>
5
6#define PPC_FEATURE_32 0x80000000
7#define PPC_FEATURE_64 0x40000000
8#define PPC_FEATURE_601_INSTR 0x20000000
9#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10#define PPC_FEATURE_HAS_FPU 0x08000000
11#define PPC_FEATURE_HAS_MMU 0x04000000
12#define PPC_FEATURE_HAS_4xxMAC 0x02000000
13#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14#define PPC_FEATURE_HAS_SPE 0x00800000
15#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
16#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
17#define PPC_FEATURE_NO_TB 0x00100000
18#define PPC_FEATURE_POWER4 0x00080000
19#define PPC_FEATURE_POWER5 0x00040000
20#define PPC_FEATURE_POWER5_PLUS 0x00020000
21#define PPC_FEATURE_CELL 0x00010000
22#define PPC_FEATURE_BOOKE 0x00008000
23#define PPC_FEATURE_SMT 0x00004000
24#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
25#define PPC_FEATURE_ARCH_2_05 0x00001000
26#define PPC_FEATURE_PA6T 0x00000800
27#define PPC_FEATURE_HAS_DFP 0x00000400
28#define PPC_FEATURE_POWER6_EXT 0x00000200
29
30#define PPC_FEATURE_TRUE_LE 0x00000002
31#define PPC_FEATURE_PPC_LE 0x00000001
32
33#ifdef __KERNEL__
34#ifndef __ASSEMBLY__
35
36/* This structure can grow, it's real size is used by head.S code
37 * via the mkdefs mechanism.
38 */
39struct cpu_spec;
40
41typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
42typedef void (*cpu_restore_t)(void);
43
44enum powerpc_oprofile_type {
45 PPC_OPROFILE_INVALID = 0,
46 PPC_OPROFILE_RS64 = 1,
47 PPC_OPROFILE_POWER4 = 2,
48 PPC_OPROFILE_G4 = 3,
49 PPC_OPROFILE_BOOKE = 4,
50 PPC_OPROFILE_CELL = 5,
51 PPC_OPROFILE_PA6T = 6,
52};
53
54enum powerpc_pmc_type {
55 PPC_PMC_DEFAULT = 0,
56 PPC_PMC_IBM = 1,
57 PPC_PMC_PA6T = 2,
58};
59
60/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
61struct cpu_spec {
62 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
63 unsigned int pvr_mask;
64 unsigned int pvr_value;
65
66 char *cpu_name;
67 unsigned long cpu_features; /* Kernel features */
68 unsigned int cpu_user_features; /* Userland features */
69
70 /* cache line sizes */
71 unsigned int icache_bsize;
72 unsigned int dcache_bsize;
73
74 /* number of performance monitor counters */
75 unsigned int num_pmcs;
76 enum powerpc_pmc_type pmc_type;
77
78 /* this is called to initialize various CPU bits like L1 cache,
79 * BHT, SPD, etc... from head.S before branching to identify_machine
80 */
81 cpu_setup_t cpu_setup;
82 /* Used to restore cpu setup on secondary processors and at resume */
83 cpu_restore_t cpu_restore;
84
85 /* Used by oprofile userspace to select the right counters */
86 char *oprofile_cpu_type;
87
88 /* Processor specific oprofile operations */
89 enum powerpc_oprofile_type oprofile_type;
90
91 /* Bit locations inside the mmcra change */
92 unsigned long oprofile_mmcra_sihv;
93 unsigned long oprofile_mmcra_sipr;
94
95 /* Bits to clear during an oprofile exception */
96 unsigned long oprofile_mmcra_clear;
97
98 /* Name of processor class, for the ELF AT_PLATFORM entry */
99 char *platform;
100};
101
102extern struct cpu_spec *cur_cpu_spec;
103
104extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
105
106extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
107extern void do_feature_fixups(unsigned long value, void *fixup_start,
108 void *fixup_end);
109
110#endif /* __ASSEMBLY__ */
111
112/* CPU kernel features */
113
114/* Retain the 32b definitions all use bottom half of word */
115#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
116#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
117#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
118#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
119#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
120#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
121#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
122#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
123#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
124#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
125#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
126#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
127#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
128#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
129#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
130#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
131#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
132#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
133#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
134#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
135#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
136#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
137#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
138#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
139#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
140#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
141#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
142
143/*
144 * Add the 64-bit processor unique features in the top half of the word;
145 * on 32-bit, make the names available but defined to be 0.
146 */
147#ifdef __powerpc64__
148#define LONG_ASM_CONST(x) ASM_CONST(x)
149#else
150#define LONG_ASM_CONST(x) 0
151#endif
152
153#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
154#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
155#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
156#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
157#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
158#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
159#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
160#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
161#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
162#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
163#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
164#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
165#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
166#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
167#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
168#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
169#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
170
171#ifndef __ASSEMBLY__
172
173#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
174 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
175 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
176
177/* We only set the altivec features if the kernel was compiled with altivec
178 * support
179 */
180#ifdef CONFIG_ALTIVEC
181#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
182#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
183#else
184#define CPU_FTR_ALTIVEC_COMP 0
185#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
186#endif
187
188/* We only set the spe features if the kernel was compiled with spe
189 * support
190 */
191#ifdef CONFIG_SPE
192#define CPU_FTR_SPE_COMP CPU_FTR_SPE
193#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
194#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
195#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
196#else
197#define CPU_FTR_SPE_COMP 0
198#define PPC_FEATURE_HAS_SPE_COMP 0
199#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
200#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
201#endif
202
203/* We need to mark all pages as being coherent if we're SMP or we have a
204 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
205 * require it for PCI "streaming/prefetch" to work properly.
206 */
207#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
208 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260)
209#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
210#else
211#define CPU_FTR_COMMON 0
212#endif
213
214/* The powersave features NAP & DOZE seems to confuse BDI when
215 debugging. So if a BDI is used, disable theses
216 */
217#ifndef CONFIG_BDI_SWITCH
218#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
219#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
220#else
221#define CPU_FTR_MAYBE_CAN_DOZE 0
222#define CPU_FTR_MAYBE_CAN_NAP 0
223#endif
224
225#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
226 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
227 !defined(CONFIG_BOOKE))
228
229#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \
230 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
231#define CPU_FTRS_603 (CPU_FTR_COMMON | \
232 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
233 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
234#define CPU_FTRS_604 (CPU_FTR_COMMON | \
235 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
236 CPU_FTR_PPC_LE)
237#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
238 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
239 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
240#define CPU_FTRS_740 (CPU_FTR_COMMON | \
241 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
242 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
243 CPU_FTR_PPC_LE)
244#define CPU_FTRS_750 (CPU_FTR_COMMON | \
245 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
246 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
247 CPU_FTR_PPC_LE)
248#define CPU_FTRS_750CL (CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS)
249#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
250#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
251#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \
252 CPU_FTR_HAS_HIGH_BATS)
253#define CPU_FTRS_750GX (CPU_FTRS_750FX)
254#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
255 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
256 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
257 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
258#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
259 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
260 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
261 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
262#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
263 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
264 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
265 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
266#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
267 CPU_FTR_USE_TB | \
268 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
269 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
270 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
271 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
272#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
273 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
274 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
275 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
276 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
277#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
278 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
279 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
280 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
281 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
282#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
283 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
284 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
285 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
286 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
287 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
288#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
289 CPU_FTR_USE_TB | \
290 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
291 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
292 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
293 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
294#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
295 CPU_FTR_USE_TB | \
296 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
297 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
298 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
299 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
300 CPU_FTR_NEED_PAIRED_STWCX)
301#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
302 CPU_FTR_USE_TB | \
303 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
304 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
305 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
306 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
307#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
308 CPU_FTR_USE_TB | \
309 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
310 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
311 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
312 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
313#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
314 CPU_FTR_USE_TB | \
315 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
316 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
317 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
318 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
319#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
320 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
321#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
322 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
323#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
324 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
325 CPU_FTR_COMMON)
326#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
327 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
328 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
329#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | \
330 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
331#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
332#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
333#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
334#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
335 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
336 CPU_FTR_UNIFIED_ID_CACHE)
337#define CPU_FTRS_E500 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
338 CPU_FTR_NODSISRALIGN)
339#define CPU_FTRS_E500_2 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
340 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
341#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
342
343/* 64-bit CPUs */
344#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
345 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
346#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
347 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
348 CPU_FTR_MMCRA | CPU_FTR_CTRL)
349#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | \
350 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
351 CPU_FTR_MMCRA)
352#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | \
353 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
354 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
355#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | \
356 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
357 CPU_FTR_MMCRA | CPU_FTR_SMT | \
358 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
359 CPU_FTR_PURR)
360#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | \
361 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
362 CPU_FTR_MMCRA | CPU_FTR_SMT | \
363 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
364 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
365 CPU_FTR_DSCR)
366#define CPU_FTRS_CELL (CPU_FTR_USE_TB | \
367 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
368 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
369 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
370#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \
371 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
372 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
373 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
374#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | \
375 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
376
377#ifdef __powerpc64__
378#define CPU_FTRS_POSSIBLE \
379 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
380 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
381 CPU_FTRS_CELL | CPU_FTRS_PA6T | CPU_FTR_1T_SEGMENT)
382#else
383enum {
384 CPU_FTRS_POSSIBLE =
385#if CLASSIC_PPC
386 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
387 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
388 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
389 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
390 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
391 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
392 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
393 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
394 CPU_FTRS_CLASSIC32 |
395#else
396 CPU_FTRS_GENERIC_32 |
397#endif
398#ifdef CONFIG_8xx
399 CPU_FTRS_8XX |
400#endif
401#ifdef CONFIG_40x
402 CPU_FTRS_40X |
403#endif
404#ifdef CONFIG_44x
405 CPU_FTRS_44X |
406#endif
407#ifdef CONFIG_E200
408 CPU_FTRS_E200 |
409#endif
410#ifdef CONFIG_E500
411 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
412#endif
413 0,
414};
415#endif /* __powerpc64__ */
416
417#ifdef __powerpc64__
418#define CPU_FTRS_ALWAYS \
419 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
420 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
421 CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
422#else
423enum {
424 CPU_FTRS_ALWAYS =
425#if CLASSIC_PPC
426 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
427 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
428 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
429 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
430 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
431 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
432 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
433 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
434 CPU_FTRS_CLASSIC32 &
435#else
436 CPU_FTRS_GENERIC_32 &
437#endif
438#ifdef CONFIG_8xx
439 CPU_FTRS_8XX &
440#endif
441#ifdef CONFIG_40x
442 CPU_FTRS_40X &
443#endif
444#ifdef CONFIG_44x
445 CPU_FTRS_44X &
446#endif
447#ifdef CONFIG_E200
448 CPU_FTRS_E200 &
449#endif
450#ifdef CONFIG_E500
451 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
452#endif
453 CPU_FTRS_POSSIBLE,
454};
455#endif /* __powerpc64__ */
456
457static inline int cpu_has_feature(unsigned long feature)
458{
459 return (CPU_FTRS_ALWAYS & feature) ||
460 (CPU_FTRS_POSSIBLE
461 & cur_cpu_spec->cpu_features
462 & feature);
463}
464
465#endif /* !__ASSEMBLY__ */
466
467#ifdef __ASSEMBLY__
468
469#define BEGIN_FTR_SECTION_NESTED(label) label:
470#define BEGIN_FTR_SECTION BEGIN_FTR_SECTION_NESTED(97)
471#define END_FTR_SECTION_NESTED(msk, val, label) \
472 MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
473#define END_FTR_SECTION(msk, val) \
474 END_FTR_SECTION_NESTED(msk, val, 97)
475
476#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
477#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
478#endif /* __ASSEMBLY__ */
479
480#endif /* __KERNEL__ */
481#endif /* __ASM_POWERPC_CPUTABLE_H */