Linux kernel mirror (for testing)
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1/* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
2 *
3 * linux/drivers/serial/sh-sci.h
4 *
5 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 1999, 2000 Niibe Yutaka
7 * Copyright (C) 2000 Greg Banks
8 * Copyright (C) 2002, 2003 Paul Mundt
9 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
12 * Removed SH7300 support (Jul 2007).
13 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Aug 2007).
14 */
15#include <linux/serial_core.h>
16#include <asm/io.h>
17
18#include <asm/gpio.h>
19
20#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
21#include <asm/regs306x.h>
22#endif
23#if defined(CONFIG_H8S2678)
24#include <asm/regs267x.h>
25#endif
26
27#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
28 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
29 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
30 defined(CONFIG_CPU_SUBTYPE_SH7709)
31# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
32# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
33# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
34# define SCI_AND_SCIF
35#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
36# define SCIF0 0xA4400000
37# define SCIF2 0xA4410000
38# define SCSMR_Ir 0xA44A0000
39# define IRDA_SCIF SCIF0
40# define SCPCR 0xA4000116
41# define SCPDR 0xA4000136
42
43/* Set the clock source,
44 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
45 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
46 */
47# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
48# define SCIF_ONLY
49#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
50# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
51# define SCIF_ONLY
52#define SCIF_ORER 0x0200 /* overrun error bit */
53#elif defined(CONFIG_SH_RTS7751R2D)
54# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
55# define SCIF_ORER 0x0001 /* overrun error bit */
56# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
57# define SCIF_ONLY
58#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
59 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
60 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
61 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
62 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
63 defined(CONFIG_CPU_SUBTYPE_SH7751R)
64# define SCSPTR1 0xffe0001c /* 8 bit SCI */
65# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
66# define SCIF_ORER 0x0001 /* overrun error bit */
67# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
68 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
69 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
70# define SCI_AND_SCIF
71#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
72# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
73# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
74# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
75# define SCIF_ORER 0x0001 /* overrun error bit */
76# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
77# define SCIF_ONLY
78#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
79# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
80# define SCI_NPORTS 2
81# define SCIF_ORER 0x0001 /* overrun error bit */
82# define PACR 0xa4050100
83# define PBCR 0xa4050102
84# define SCSCR_INIT(port) 0x3B
85# define SCIF_ONLY
86#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
87# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
88# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
89# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
90# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
91# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
92# define SCIF_ONLY
93#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
94# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
95# define SCSPTR0 SCPDR0
96# define SCIF_ORER 0x0001 /* overrun error bit */
97# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
98# define SCIF_ONLY
99# define PORT_PSCR 0xA405011E
100#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
101# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
102# define SCIF_ORER 0x0001 /* overrun error bit */
103# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
104# define SCIF_ONLY
105#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
106# define SCSPTR1 0xffe00020 /* 16 bit SCIF */
107# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
108# define SCIF_ORER 0x0001 /* overrun error bit */
109# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
110# define SCIF_ONLY
111#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
112# include <asm/hardware.h>
113# define SCIF_BASE_ADDR 0x01030000
114# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
115# define SCIF_PTR2_OFFS 0x0000020
116# define SCIF_LSR2_OFFS 0x0000024
117# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
118# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
119# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,
120 TE=1,RE=1,REIE=1 */
121# define SCIF_ONLY
122#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
123# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
124# define SCI_ONLY
125# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
126#elif defined(CONFIG_H8S2678)
127# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
128# define SCI_ONLY
129# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
130#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
131# define SCSPTR0 0xff923020 /* 16 bit SCIF */
132# define SCSPTR1 0xff924020 /* 16 bit SCIF */
133# define SCSPTR2 0xff925020 /* 16 bit SCIF */
134# define SCIF_ORER 0x0001 /* overrun error bit */
135# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
136# define SCIF_ONLY
137#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
138# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
139# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
140# define SCIF_ORER 0x0001 /* Overrun error bit */
141# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
142# define SCIF_ONLY
143#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
144# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
145# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
146# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
147# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
148# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
149# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
150# define SCIF_OPER 0x0001 /* Overrun error bit */
151# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
152# define SCIF_ONLY
153#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
154# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
155# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
156# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
157# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
158# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
159# define SCIF_ONLY
160#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
161# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
162# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
163# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
164# define SCIF_ORER 0x0001 /* overrun error bit */
165# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
166# define SCIF_ONLY
167#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
168# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
169# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
170# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
171# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
172# define SCIF_ORER 0x0001 /* Overrun error bit */
173# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
174# define SCIF_ONLY
175#else
176# error CPU subtype not defined
177#endif
178
179/* SCSCR */
180#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
181#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
182#define SCI_CTRL_FLAGS_TE 0x20 /* all */
183#define SCI_CTRL_FLAGS_RE 0x10 /* all */
184#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
185 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
186 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
187 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
188 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
189 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
190 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
191 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
192 defined(CONFIG_CPU_SUBTYPE_SHX3)
193#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
194#else
195#define SCI_CTRL_FLAGS_REIE 0
196#endif
197/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
198/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
199/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
200/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
201
202/* SCxSR SCI */
203#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
204#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
205#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
206#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
207#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
208#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
209/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
210/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
211
212#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
213
214/* SCxSR SCIF */
215#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
216#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
217#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
218#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
219#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
220#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
221#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
222#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
223
224#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
225 defined(CONFIG_CPU_SUBTYPE_SH7720)
226#define SCIF_ORER 0x0200
227#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
228#define SCIF_RFDC_MASK 0x007f
229#define SCIF_TXROOM_MAX 64
230#else
231#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
232#define SCIF_RFDC_MASK 0x001f
233#define SCIF_TXROOM_MAX 16
234#endif
235
236#if defined(SCI_ONLY)
237# define SCxSR_TEND(port) SCI_TEND
238# define SCxSR_ERRORS(port) SCI_ERRORS
239# define SCxSR_RDxF(port) SCI_RDRF
240# define SCxSR_TDxE(port) SCI_TDRE
241# define SCxSR_ORER(port) SCI_ORER
242# define SCxSR_FER(port) SCI_FER
243# define SCxSR_PER(port) SCI_PER
244# define SCxSR_BRK(port) 0x00
245# define SCxSR_RDxF_CLEAR(port) 0xbc
246# define SCxSR_ERROR_CLEAR(port) 0xc4
247# define SCxSR_TDxE_CLEAR(port) 0x78
248# define SCxSR_BREAK_CLEAR(port) 0xc4
249#elif defined(SCIF_ONLY)
250# define SCxSR_TEND(port) SCIF_TEND
251# define SCxSR_ERRORS(port) SCIF_ERRORS
252# define SCxSR_RDxF(port) SCIF_RDF
253# define SCxSR_TDxE(port) SCIF_TDFE
254#if defined(CONFIG_CPU_SUBTYPE_SH7705)
255# define SCxSR_ORER(port) SCIF_ORER
256#else
257# define SCxSR_ORER(port) 0x0000
258#endif
259# define SCxSR_FER(port) SCIF_FER
260# define SCxSR_PER(port) SCIF_PER
261# define SCxSR_BRK(port) SCIF_BRK
262#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
263 defined(CONFIG_CPU_SUBTYPE_SH7720)
264# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
265# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
266# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
267# define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
268#else
269/* SH7705 can also use this, clearing is same between 7705 and 7709 */
270# define SCxSR_RDxF_CLEAR(port) 0x00fc
271# define SCxSR_ERROR_CLEAR(port) 0x0073
272# define SCxSR_TDxE_CLEAR(port) 0x00df
273# define SCxSR_BREAK_CLEAR(port) 0x00e3
274#endif
275#else
276# define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
277# define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
278# define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
279# define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
280# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
281# define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
282# define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
283# define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
284# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
285# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
286# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
287# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
288#endif
289
290/* SCFCR */
291#define SCFCR_RFRST 0x0002
292#define SCFCR_TFRST 0x0004
293#define SCFCR_TCRST 0x4000
294#define SCFCR_MCE 0x0008
295
296#define SCI_MAJOR 204
297#define SCI_MINOR_START 8
298
299/* Generic serial flags */
300#define SCI_RX_THROTTLE 0x0000001
301
302#define SCI_MAGIC 0xbabeface
303
304/*
305 * Events are used to schedule things to happen at timer-interrupt
306 * time, instead of at rs interrupt time.
307 */
308#define SCI_EVENT_WRITE_WAKEUP 0
309
310#define SCI_IN(size, offset) \
311 unsigned int addr = port->mapbase + (offset); \
312 if ((size) == 8) { \
313 return ctrl_inb(addr); \
314 } else { \
315 return ctrl_inw(addr); \
316 }
317#define SCI_OUT(size, offset, value) \
318 unsigned int addr = port->mapbase + (offset); \
319 if ((size) == 8) { \
320 ctrl_outb(value, addr); \
321 } else { \
322 ctrl_outw(value, addr); \
323 }
324
325#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
326 static inline unsigned int sci_##name##_in(struct uart_port *port) \
327 { \
328 if (port->type == PORT_SCI) { \
329 SCI_IN(sci_size, sci_offset) \
330 } else { \
331 SCI_IN(scif_size, scif_offset); \
332 } \
333 } \
334 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
335 { \
336 if (port->type == PORT_SCI) { \
337 SCI_OUT(sci_size, sci_offset, value) \
338 } else { \
339 SCI_OUT(scif_size, scif_offset, value); \
340 } \
341 }
342
343#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
344 static inline unsigned int sci_##name##_in(struct uart_port *port) \
345 { \
346 SCI_IN(scif_size, scif_offset); \
347 } \
348 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
349 { \
350 SCI_OUT(scif_size, scif_offset, value); \
351 }
352
353#define CPU_SCI_FNS(name, sci_offset, sci_size) \
354 static inline unsigned int sci_##name##_in(struct uart_port* port) \
355 { \
356 SCI_IN(sci_size, sci_offset); \
357 } \
358 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
359 { \
360 SCI_OUT(sci_size, sci_offset, value); \
361 }
362
363#ifdef CONFIG_CPU_SH3
364#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
365#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
366 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
367 h8_sci_offset, h8_sci_size) \
368 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
369#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
370 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
371#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
372 defined(CONFIG_CPU_SUBTYPE_SH7720)
373#define SCIF_FNS(name, scif_offset, scif_size) \
374 CPU_SCIF_FNS(name, scif_offset, scif_size)
375#else
376#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
377 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
378 h8_sci_offset, h8_sci_size) \
379 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
380#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
381 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
382#endif
383#elif defined(__H8300H__) || defined(__H8300S__)
384#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
385 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
386 h8_sci_offset, h8_sci_size) \
387 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
388#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
389#else
390#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
391 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
392 h8_sci_offset, h8_sci_size) \
393 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
394#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
395 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
396#endif
397
398#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
399 defined(CONFIG_CPU_SUBTYPE_SH7720)
400
401SCIF_FNS(SCSMR, 0x00, 16)
402SCIF_FNS(SCBRR, 0x04, 8)
403SCIF_FNS(SCSCR, 0x08, 16)
404SCIF_FNS(SCTDSR, 0x0c, 8)
405SCIF_FNS(SCFER, 0x10, 16)
406SCIF_FNS(SCxSR, 0x14, 16)
407SCIF_FNS(SCFCR, 0x18, 16)
408SCIF_FNS(SCFDR, 0x1c, 16)
409SCIF_FNS(SCxTDR, 0x20, 8)
410SCIF_FNS(SCxRDR, 0x24, 8)
411SCIF_FNS(SCLSR, 0x24, 16)
412#else
413/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
414/* name off sz off sz off sz off sz off sz*/
415SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
416SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
417SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
418SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
419SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
420SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
421SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
422#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
423 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
424 defined(CONFIG_CPU_SUBTYPE_SH7785)
425SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
426SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
427SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
428SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
429SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
430#else
431SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
432SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
433SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
434#endif
435#endif
436#define sci_in(port, reg) sci_##reg##_in(port)
437#define sci_out(port, reg, value) sci_##reg##_out(port, value)
438
439/* H8/300 series SCI pins assignment */
440#if defined(__H8300H__) || defined(__H8300S__)
441static const struct __attribute__((packed)) {
442 int port; /* GPIO port no */
443 unsigned short rx,tx; /* GPIO bit no */
444} h8300_sci_pins[] = {
445#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
446 { /* SCI0 */
447 .port = H8300_GPIO_P9,
448 .rx = H8300_GPIO_B2,
449 .tx = H8300_GPIO_B0,
450 },
451 { /* SCI1 */
452 .port = H8300_GPIO_P9,
453 .rx = H8300_GPIO_B3,
454 .tx = H8300_GPIO_B1,
455 },
456 { /* SCI2 */
457 .port = H8300_GPIO_PB,
458 .rx = H8300_GPIO_B7,
459 .tx = H8300_GPIO_B6,
460 }
461#elif defined(CONFIG_H8S2678)
462 { /* SCI0 */
463 .port = H8300_GPIO_P3,
464 .rx = H8300_GPIO_B2,
465 .tx = H8300_GPIO_B0,
466 },
467 { /* SCI1 */
468 .port = H8300_GPIO_P3,
469 .rx = H8300_GPIO_B3,
470 .tx = H8300_GPIO_B1,
471 },
472 { /* SCI2 */
473 .port = H8300_GPIO_P5,
474 .rx = H8300_GPIO_B1,
475 .tx = H8300_GPIO_B0,
476 }
477#endif
478};
479#endif
480
481#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
482 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
483 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
484 defined(CONFIG_CPU_SUBTYPE_SH7709)
485static inline int sci_rxd_in(struct uart_port *port)
486{
487 if (port->mapbase == 0xfffffe80)
488 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
489 if (port->mapbase == 0xa4000150)
490 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
491 if (port->mapbase == 0xa4000140)
492 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
493 return 1;
494}
495#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
496static inline int sci_rxd_in(struct uart_port *port)
497{
498 if (port->mapbase == SCIF0)
499 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
500 if (port->mapbase == SCIF2)
501 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
502 return 1;
503}
504#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
505static inline int sci_rxd_in(struct uart_port *port)
506{
507 return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
508}
509static inline void set_sh771x_scif_pfc(struct uart_port *port)
510{
511 if (port->mapbase == 0xA4400000){
512 ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
513 ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
514 return;
515 }
516 if (port->mapbase == 0xA4410000){
517 ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
518 return;
519 }
520}
521#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
522static inline int sci_rxd_in(struct uart_port *port)
523{
524 if (port->mapbase == 0xa4430000)
525 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
526 else if (port->mapbase == 0xa4438000)
527 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
528 return 1;
529}
530#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
531 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
532 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
533 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
534 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
535 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
536 defined(CONFIG_CPU_SUBTYPE_SH4_202)
537static inline int sci_rxd_in(struct uart_port *port)
538{
539#ifndef SCIF_ONLY
540 if (port->mapbase == 0xffe00000)
541 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
542#endif
543#ifndef SCI_ONLY
544 if (port->mapbase == 0xffe80000)
545 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
546#endif
547 return 1;
548}
549#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
550static inline int sci_rxd_in(struct uart_port *port)
551{
552 if (port->mapbase == 0xfe600000)
553 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
554 if (port->mapbase == 0xfe610000)
555 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
556 if (port->mapbase == 0xfe620000)
557 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
558 return 1;
559}
560#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
561static inline int sci_rxd_in(struct uart_port *port)
562{
563 if (port->mapbase == 0xffe00000)
564 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
565 if (port->mapbase == 0xffe10000)
566 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
567 if (port->mapbase == 0xffe20000)
568 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
569 if (port->mapbase == 0xffe30000)
570 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
571 return 1;
572}
573#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
574static inline int sci_rxd_in(struct uart_port *port)
575{
576 if (port->mapbase == 0xffe00000)
577 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
578 return 1;
579}
580#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
581static inline int sci_rxd_in(struct uart_port *port)
582{
583 if (port->mapbase == 0xffe00000)
584 return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */
585 else
586 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
587
588}
589#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
590static inline int sci_rxd_in(struct uart_port *port)
591{
592 return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
593}
594#elif defined(__H8300H__) || defined(__H8300S__)
595static inline int sci_rxd_in(struct uart_port *port)
596{
597 int ch = (port->mapbase - SMR0) >> 3;
598 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
599}
600#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
601static inline int sci_rxd_in(struct uart_port *port)
602{
603 if (port->mapbase == 0xff923000)
604 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
605 if (port->mapbase == 0xff924000)
606 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
607 if (port->mapbase == 0xff925000)
608 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
609 return 1;
610}
611#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
612static inline int sci_rxd_in(struct uart_port *port)
613{
614 if (port->mapbase == 0xffe00000)
615 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
616 if (port->mapbase == 0xffe10000)
617 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
618 return 1;
619}
620#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
621static inline int sci_rxd_in(struct uart_port *port)
622{
623 if (port->mapbase == 0xffea0000)
624 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
625 if (port->mapbase == 0xffeb0000)
626 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
627 if (port->mapbase == 0xffec0000)
628 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
629 if (port->mapbase == 0xffed0000)
630 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
631 if (port->mapbase == 0xffee0000)
632 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
633 if (port->mapbase == 0xffef0000)
634 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
635 return 1;
636}
637#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
638static inline int sci_rxd_in(struct uart_port *port)
639{
640 if (port->mapbase == 0xfffe8000)
641 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
642 if (port->mapbase == 0xfffe8800)
643 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
644 if (port->mapbase == 0xfffe9000)
645 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
646 if (port->mapbase == 0xfffe9800)
647 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
648 return 1;
649}
650#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
651static inline int sci_rxd_in(struct uart_port *port)
652{
653 if (port->mapbase == 0xf8400000)
654 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
655 if (port->mapbase == 0xf8410000)
656 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
657 if (port->mapbase == 0xf8420000)
658 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
659 return 1;
660}
661#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
662static inline int sci_rxd_in(struct uart_port *port)
663{
664 if (port->mapbase == 0xffc30000)
665 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
666 if (port->mapbase == 0xffc40000)
667 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
668 if (port->mapbase == 0xffc50000)
669 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
670 if (port->mapbase == 0xffc60000)
671 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
672 return 1;
673}
674#endif
675
676/*
677 * Values for the BitRate Register (SCBRR)
678 *
679 * The values are actually divisors for a frequency which can
680 * be internal to the SH3 (14.7456MHz) or derived from an external
681 * clock source. This driver assumes the internal clock is used;
682 * to support using an external clock source, config options or
683 * possibly command-line options would need to be added.
684 *
685 * Also, to support speeds below 2400 (why?) the lower 2 bits of
686 * the SCSMR register would also need to be set to non-zero values.
687 *
688 * -- Greg Banks 27Feb2000
689 *
690 * Answer: The SCBRR register is only eight bits, and the value in
691 * it gets larger with lower baud rates. At around 2400 (depending on
692 * the peripherial module clock) you run out of bits. However the
693 * lower two bits of SCSMR allow the module clock to be divided down,
694 * scaling the value which is needed in SCBRR.
695 *
696 * -- Stuart Menefy - 23 May 2000
697 *
698 * I meant, why would anyone bother with bitrates below 2400.
699 *
700 * -- Greg Banks - 7Jul2000
701 *
702 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
703 * tape reader as a console!
704 *
705 * -- Mitch Davis - 15 Jul 2000
706 */
707
708#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
709 defined(CONFIG_CPU_SUBTYPE_SH7785)
710#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
711#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
712 defined(CONFIG_CPU_SUBTYPE_SH7720)
713#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
714#elif defined(__H8300H__) || defined(__H8300S__)
715#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
716#elif defined(CONFIG_SUPERH64)
717#define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
718#else /* Generic SH */
719#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
720#endif