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1/* $Id: system.h,v 1.86 2001/10/30 04:57:10 davem Exp $ */
2
3#ifndef __SPARC_SYSTEM_H
4#define __SPARC_SYSTEM_H
5
6#include <linux/kernel.h>
7#include <linux/threads.h> /* NR_CPUS */
8#include <linux/thread_info.h>
9
10#include <asm/page.h>
11#include <asm/psr.h>
12#include <asm/ptrace.h>
13#include <asm/btfixup.h>
14#include <asm/smp.h>
15
16#ifndef __ASSEMBLY__
17
18/*
19 * Sparc (general) CPU types
20 */
21enum sparc_cpu {
22 sun4 = 0x00,
23 sun4c = 0x01,
24 sun4m = 0x02,
25 sun4d = 0x03,
26 sun4e = 0x04,
27 sun4u = 0x05, /* V8 ploos ploos */
28 sun_unknown = 0x06,
29 ap1000 = 0x07, /* almost a sun4m */
30};
31
32/* Really, userland should not be looking at any of this... */
33#ifdef __KERNEL__
34
35extern enum sparc_cpu sparc_cpu_model;
36
37#ifndef CONFIG_SUN4
38#define ARCH_SUN4C_SUN4 (sparc_cpu_model==sun4c)
39#define ARCH_SUN4 0
40#else
41#define ARCH_SUN4C_SUN4 1
42#define ARCH_SUN4 1
43#endif
44
45#define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */
46
47extern struct thread_info *current_set[NR_CPUS];
48
49extern unsigned long empty_bad_page;
50extern unsigned long empty_bad_page_table;
51extern unsigned long empty_zero_page;
52
53extern void sun_do_break(void);
54extern int serial_console;
55extern int stop_a_enabled;
56
57static __inline__ int con_is_present(void)
58{
59 return serial_console ? 0 : 1;
60}
61
62/* When a context switch happens we must flush all user windows so that
63 * the windows of the current process are flushed onto its stack. This
64 * way the windows are all clean for the next process and the stack
65 * frames are up to date.
66 */
67extern void flush_user_windows(void);
68extern void kill_user_windows(void);
69extern void synchronize_user_stack(void);
70extern void fpsave(unsigned long *fpregs, unsigned long *fsr,
71 void *fpqueue, unsigned long *fpqdepth);
72
73#ifdef CONFIG_SMP
74#define SWITCH_ENTER(prv) \
75 do { \
76 if (test_tsk_thread_flag(prv, TIF_USEDFPU)) { \
77 put_psr(get_psr() | PSR_EF); \
78 fpsave(&(prv)->thread.float_regs[0], &(prv)->thread.fsr, \
79 &(prv)->thread.fpqueue[0], &(prv)->thread.fpqdepth); \
80 clear_tsk_thread_flag(prv, TIF_USEDFPU); \
81 (prv)->thread.kregs->psr &= ~PSR_EF; \
82 } \
83 } while(0)
84
85#define SWITCH_DO_LAZY_FPU(next) /* */
86#else
87#define SWITCH_ENTER(prv) /* */
88#define SWITCH_DO_LAZY_FPU(nxt) \
89 do { \
90 if (last_task_used_math != (nxt)) \
91 (nxt)->thread.kregs->psr&=~PSR_EF; \
92 } while(0)
93#endif
94
95/*
96 * Flush windows so that the VM switch which follows
97 * would not pull the stack from under us.
98 *
99 * SWITCH_ENTER and SWITH_DO_LAZY_FPU do not work yet (e.g. SMP does not work)
100 * XXX WTF is the above comment? Found in late teen 2.4.x.
101 */
102#define prepare_arch_switch(next) do { \
103 __asm__ __volatile__( \
104 ".globl\tflush_patch_switch\nflush_patch_switch:\n\t" \
105 "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
106 "save %sp, -0x40, %sp; save %sp, -0x40, %sp; save %sp, -0x40, %sp\n\t" \
107 "save %sp, -0x40, %sp\n\t" \
108 "restore; restore; restore; restore; restore; restore; restore"); \
109} while(0)
110
111 /* Much care has gone into this code, do not touch it.
112 *
113 * We need to loadup regs l0/l1 for the newly forked child
114 * case because the trap return path relies on those registers
115 * holding certain values, gcc is told that they are clobbered.
116 * Gcc needs registers for 3 values in and 1 value out, so we
117 * clobber every non-fixed-usage register besides l2/l3/o4/o5. -DaveM
118 *
119 * Hey Dave, that do not touch sign is too much of an incentive
120 * - Anton & Pete
121 */
122#define switch_to(prev, next, last) do { \
123 SWITCH_ENTER(prev); \
124 SWITCH_DO_LAZY_FPU(next); \
125 cpu_set(smp_processor_id(), next->active_mm->cpu_vm_mask); \
126 __asm__ __volatile__( \
127 "sethi %%hi(here - 0x8), %%o7\n\t" \
128 "mov %%g6, %%g3\n\t" \
129 "or %%o7, %%lo(here - 0x8), %%o7\n\t" \
130 "rd %%psr, %%g4\n\t" \
131 "std %%sp, [%%g6 + %4]\n\t" \
132 "rd %%wim, %%g5\n\t" \
133 "wr %%g4, 0x20, %%psr\n\t" \
134 "nop\n\t" \
135 "std %%g4, [%%g6 + %3]\n\t" \
136 "ldd [%2 + %3], %%g4\n\t" \
137 "mov %2, %%g6\n\t" \
138 ".globl patchme_store_new_current\n" \
139"patchme_store_new_current:\n\t" \
140 "st %2, [%1]\n\t" \
141 "wr %%g4, 0x20, %%psr\n\t" \
142 "nop\n\t" \
143 "nop\n\t" \
144 "nop\n\t" /* LEON needs all 3 nops: load to %sp depends on CWP. */ \
145 "ldd [%%g6 + %4], %%sp\n\t" \
146 "wr %%g5, 0x0, %%wim\n\t" \
147 "ldd [%%sp + 0x00], %%l0\n\t" \
148 "ldd [%%sp + 0x38], %%i6\n\t" \
149 "wr %%g4, 0x0, %%psr\n\t" \
150 "nop\n\t" \
151 "nop\n\t" \
152 "jmpl %%o7 + 0x8, %%g0\n\t" \
153 " ld [%%g3 + %5], %0\n\t" \
154 "here:\n" \
155 : "=&r" (last) \
156 : "r" (&(current_set[hard_smp_processor_id()])), \
157 "r" (task_thread_info(next)), \
158 "i" (TI_KPSR), \
159 "i" (TI_KSP), \
160 "i" (TI_TASK) \
161 : "g1", "g2", "g3", "g4", "g5", "g7", \
162 "l0", "l1", "l3", "l4", "l5", "l6", "l7", \
163 "i0", "i1", "i2", "i3", "i4", "i5", \
164 "o0", "o1", "o2", "o3", "o7"); \
165 } while(0)
166
167/*
168 * Changing the IRQ level on the Sparc.
169 */
170extern void local_irq_restore(unsigned long);
171extern unsigned long __local_irq_save(void);
172extern void local_irq_enable(void);
173
174static inline unsigned long getipl(void)
175{
176 unsigned long retval;
177
178 __asm__ __volatile__("rd %%psr, %0" : "=r" (retval));
179 return retval;
180}
181
182#define local_save_flags(flags) ((flags) = getipl())
183#define local_irq_save(flags) ((flags) = __local_irq_save())
184#define local_irq_disable() ((void) __local_irq_save())
185#define irqs_disabled() ((getipl() & PSR_PIL) != 0)
186
187/* XXX Change this if we ever use a PSO mode kernel. */
188#define mb() __asm__ __volatile__ ("" : : : "memory")
189#define rmb() mb()
190#define wmb() mb()
191#define read_barrier_depends() do { } while(0)
192#define set_mb(__var, __value) do { __var = __value; mb(); } while(0)
193#define smp_mb() __asm__ __volatile__("":::"memory")
194#define smp_rmb() __asm__ __volatile__("":::"memory")
195#define smp_wmb() __asm__ __volatile__("":::"memory")
196#define smp_read_barrier_depends() do { } while(0)
197
198#define nop() __asm__ __volatile__ ("nop")
199
200/* This has special calling conventions */
201#ifndef CONFIG_SMP
202BTFIXUPDEF_CALL(void, ___xchg32, void)
203#endif
204
205static inline unsigned long xchg_u32(__volatile__ unsigned long *m, unsigned long val)
206{
207#ifdef CONFIG_SMP
208 __asm__ __volatile__("swap [%2], %0"
209 : "=&r" (val)
210 : "0" (val), "r" (m)
211 : "memory");
212 return val;
213#else
214 register unsigned long *ptr asm("g1");
215 register unsigned long ret asm("g2");
216
217 ptr = (unsigned long *) m;
218 ret = val;
219
220 /* Note: this is magic and the nop there is
221 really needed. */
222 __asm__ __volatile__(
223 "mov %%o7, %%g4\n\t"
224 "call ___f____xchg32\n\t"
225 " nop\n\t"
226 : "=&r" (ret)
227 : "0" (ret), "r" (ptr)
228 : "g3", "g4", "g7", "memory", "cc");
229
230 return ret;
231#endif
232}
233
234#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
235
236extern void __xchg_called_with_bad_pointer(void);
237
238static __inline__ unsigned long __xchg(unsigned long x, __volatile__ void * ptr, int size)
239{
240 switch (size) {
241 case 4:
242 return xchg_u32(ptr, x);
243 };
244 __xchg_called_with_bad_pointer();
245 return x;
246}
247
248extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
249
250#endif /* __KERNEL__ */
251
252#endif /* __ASSEMBLY__ */
253
254#define arch_align_stack(x) (x)
255
256#endif /* !(__SPARC_SYSTEM_H) */