tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Low-level SLB routines
3 *
4 * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
5 *
6 * Based on earlier C version:
7 * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
8 * Copyright (c) 2001 Dave Engebretsen
9 * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16
17#include <asm/processor.h>
18#include <asm/ppc_asm.h>
19#include <asm/asm-offsets.h>
20#include <asm/cputable.h>
21#include <asm/page.h>
22#include <asm/mmu.h>
23#include <asm/pgtable.h>
24#include <asm/firmware.h>
25
26/* void slb_allocate_realmode(unsigned long ea);
27 *
28 * Create an SLB entry for the given EA (user or kernel).
29 * r3 = faulting address, r13 = PACA
30 * r9, r10, r11 are clobbered by this function
31 * No other registers are examined or changed.
32 */
33_GLOBAL(slb_allocate_realmode)
34 /* r3 = faulting address */
35
36 srdi r9,r3,60 /* get region */
37 srdi r10,r3,28 /* get esid */
38 cmpldi cr7,r9,0xc /* cmp PAGE_OFFSET for later use */
39
40 /* r3 = address, r10 = esid, cr7 = <> PAGE_OFFSET */
41 blt cr7,0f /* user or kernel? */
42
43 /* kernel address: proto-VSID = ESID */
44 /* WARNING - MAGIC: we don't use the VSID 0xfffffffff, but
45 * this code will generate the protoVSID 0xfffffffff for the
46 * top segment. That's ok, the scramble below will translate
47 * it to VSID 0, which is reserved as a bad VSID - one which
48 * will never have any pages in it. */
49
50 /* Check if hitting the linear mapping of the vmalloc/ioremap
51 * kernel space
52 */
53 bne cr7,1f
54
55 /* Linear mapping encoding bits, the "li" instruction below will
56 * be patched by the kernel at boot
57 */
58_GLOBAL(slb_miss_kernel_load_linear)
59 li r11,0
60 b slb_finish_load
61
621: /* vmalloc/ioremap mapping encoding bits, the "li" instructions below
63 * will be patched by the kernel at boot
64 */
65BEGIN_FTR_SECTION
66 /* check whether this is in vmalloc or ioremap space */
67 clrldi r11,r10,48
68 cmpldi r11,(VMALLOC_SIZE >> 28) - 1
69 bgt 5f
70 lhz r11,PACAVMALLOCSLLP(r13)
71 b slb_finish_load
725:
73END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE)
74_GLOBAL(slb_miss_kernel_load_io)
75 li r11,0
76 b slb_finish_load
77
78
790: /* user address: proto-VSID = context << 15 | ESID. First check
80 * if the address is within the boundaries of the user region
81 */
82 srdi. r9,r10,USER_ESID_BITS
83 bne- 8f /* invalid ea bits set */
84
85
86 /* when using slices, we extract the psize off the slice bitmaps
87 * and then we need to get the sllp encoding off the mmu_psize_defs
88 * array.
89 *
90 * XXX This is a bit inefficient especially for the normal case,
91 * so we should try to implement a fast path for the standard page
92 * size using the old sllp value so we avoid the array. We cannot
93 * really do dynamic patching unfortunately as processes might flip
94 * between 4k and 64k standard page size
95 */
96#ifdef CONFIG_PPC_MM_SLICES
97 cmpldi r10,16
98
99 /* Get the slice index * 4 in r11 and matching slice size mask in r9 */
100 ld r9,PACALOWSLICESPSIZE(r13)
101 sldi r11,r10,2
102 blt 5f
103 ld r9,PACAHIGHSLICEPSIZE(r13)
104 srdi r11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT - 2)
105 andi. r11,r11,0x3c
106
1075: /* Extract the psize and multiply to get an array offset */
108 srd r9,r9,r11
109 andi. r9,r9,0xf
110 mulli r9,r9,MMUPSIZEDEFSIZE
111
112 /* Now get to the array and obtain the sllp
113 */
114 ld r11,PACATOC(r13)
115 ld r11,mmu_psize_defs@got(r11)
116 add r11,r11,r9
117 ld r11,MMUPSIZESLLP(r11)
118 ori r11,r11,SLB_VSID_USER
119#else
120 /* paca context sllp already contains the SLB_VSID_USER bits */
121 lhz r11,PACACONTEXTSLLP(r13)
122#endif /* CONFIG_PPC_MM_SLICES */
123
124 ld r9,PACACONTEXTID(r13)
125 rldimi r10,r9,USER_ESID_BITS,0
126 b slb_finish_load
127
1288: /* invalid EA */
129 li r10,0 /* BAD_VSID */
130 li r11,SLB_VSID_USER /* flags don't much matter */
131 b slb_finish_load
132
133#ifdef __DISABLED__
134
135/* void slb_allocate_user(unsigned long ea);
136 *
137 * Create an SLB entry for the given EA (user or kernel).
138 * r3 = faulting address, r13 = PACA
139 * r9, r10, r11 are clobbered by this function
140 * No other registers are examined or changed.
141 *
142 * It is called with translation enabled in order to be able to walk the
143 * page tables. This is not currently used.
144 */
145_GLOBAL(slb_allocate_user)
146 /* r3 = faulting address */
147 srdi r10,r3,28 /* get esid */
148
149 crset 4*cr7+lt /* set "user" flag for later */
150
151 /* check if we fit in the range covered by the pagetables*/
152 srdi. r9,r3,PGTABLE_EADDR_SIZE
153 crnot 4*cr0+eq,4*cr0+eq
154 beqlr
155
156 /* now we need to get to the page tables in order to get the page
157 * size encoding from the PMD. In the future, we'll be able to deal
158 * with 1T segments too by getting the encoding from the PGD instead
159 */
160 ld r9,PACAPGDIR(r13)
161 cmpldi cr0,r9,0
162 beqlr
163 rlwinm r11,r10,8,25,28
164 ldx r9,r9,r11 /* get pgd_t */
165 cmpldi cr0,r9,0
166 beqlr
167 rlwinm r11,r10,3,17,28
168 ldx r9,r9,r11 /* get pmd_t */
169 cmpldi cr0,r9,0
170 beqlr
171
172 /* build vsid flags */
173 andi. r11,r9,SLB_VSID_LLP
174 ori r11,r11,SLB_VSID_USER
175
176 /* get context to calculate proto-VSID */
177 ld r9,PACACONTEXTID(r13)
178 rldimi r10,r9,USER_ESID_BITS,0
179
180 /* fall through slb_finish_load */
181
182#endif /* __DISABLED__ */
183
184
185/*
186 * Finish loading of an SLB entry and return
187 *
188 * r3 = EA, r10 = proto-VSID, r11 = flags, clobbers r9, cr7 = <> PAGE_OFFSET
189 */
190slb_finish_load:
191 ASM_VSID_SCRAMBLE(r10,r9)
192 rldimi r11,r10,SLB_VSID_SHIFT,16 /* combine VSID and flags */
193
194 /* r3 = EA, r11 = VSID data */
195 /*
196 * Find a slot, round robin. Previously we tried to find a
197 * free slot first but that took too long. Unfortunately we
198 * dont have any LRU information to help us choose a slot.
199 */
200#ifdef CONFIG_PPC_ISERIES
201BEGIN_FW_FTR_SECTION
202 /*
203 * On iSeries, the "bolted" stack segment can be cast out on
204 * shared processor switch so we need to check for a miss on
205 * it and restore it to the right slot.
206 */
207 ld r9,PACAKSAVE(r13)
208 clrrdi r9,r9,28
209 clrrdi r3,r3,28
210 li r10,SLB_NUM_BOLTED-1 /* Stack goes in last bolted slot */
211 cmpld r9,r3
212 beq 3f
213END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
214#endif /* CONFIG_PPC_ISERIES */
215
216 ld r10,PACASTABRR(r13)
217 addi r10,r10,1
218 /* use a cpu feature mask if we ever change our slb size */
219 cmpldi r10,SLB_NUM_ENTRIES
220
221 blt+ 4f
222 li r10,SLB_NUM_BOLTED
223
2244:
225 std r10,PACASTABRR(r13)
226
2273:
228 rldimi r3,r10,0,36 /* r3= EA[0:35] | entry */
229 oris r10,r3,SLB_ESID_V@h /* r3 |= SLB_ESID_V */
230
231 /* r3 = ESID data, r11 = VSID data */
232
233 /*
234 * No need for an isync before or after this slbmte. The exception
235 * we enter with and the rfid we exit with are context synchronizing.
236 */
237 slbmte r11,r10
238
239 /* we're done for kernel addresses */
240 crclr 4*cr0+eq /* set result to "success" */
241 bgelr cr7
242
243 /* Update the slb cache */
244 lhz r3,PACASLBCACHEPTR(r13) /* offset = paca->slb_cache_ptr */
245 cmpldi r3,SLB_CACHE_ENTRIES
246 bge 1f
247
248 /* still room in the slb cache */
249 sldi r11,r3,1 /* r11 = offset * sizeof(u16) */
250 rldicl r10,r10,36,28 /* get low 16 bits of the ESID */
251 add r11,r11,r13 /* r11 = (u16 *)paca + offset */
252 sth r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */
253 addi r3,r3,1 /* offset++ */
254 b 2f
2551: /* offset >= SLB_CACHE_ENTRIES */
256 li r3,SLB_CACHE_ENTRIES+1
2572:
258 sth r3,PACASLBCACHEPTR(r13) /* paca->slb_cache_ptr = offset */
259 crclr 4*cr0+eq /* set result to "success" */
260 blr
261