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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004 by Ralf Baechle
7 */
8#ifndef _ASM_WAR_H
9#define _ASM_WAR_H
10
11
12/*
13 * Another R4600 erratum. Due to the lack of errata information the exact
14 * technical details aren't known. I've experimentally found that disabling
15 * interrupts during indexed I-cache flushes seems to be sufficient to deal
16 * with the issue.
17 *
18 * #define R4600_V1_INDEX_ICACHEOP_WAR 1
19 */
20
21/*
22 * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
23 *
24 * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
25 * Hit_Invalidate_D and Create_Dirty_Excl_D should only be
26 * executed if there is no other dcache activity. If the dcache is
27 * accessed for another instruction immeidately preceding when these
28 * cache instructions are executing, it is possible that the dcache
29 * tag match outputs used by these cache instructions will be
30 * incorrect. These cache instructions should be preceded by at least
31 * four instructions that are not any kind of load or store
32 * instruction.
33 *
34 * This is not allowed: lw
35 * nop
36 * nop
37 * nop
38 * cache Hit_Writeback_Invalidate_D
39 *
40 * This is allowed: lw
41 * nop
42 * nop
43 * nop
44 * nop
45 * cache Hit_Writeback_Invalidate_D
46 *
47 * #define R4600_V1_HIT_CACHEOP_WAR 1
48 */
49
50
51/*
52 * Writeback and invalidate the primary cache dcache before DMA.
53 *
54 * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
55 * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
56 * operate correctly if the internal data cache refill buffer is empty. These
57 * CACHE instructions should be separated from any potential data cache miss
58 * by a load instruction to an uncached address to empty the response buffer."
59 * (Revision 2.0 device errata from IDT available on http://www.idt.com/
60 * in .pdf format.)
61 *
62 * #define R4600_V2_HIT_CACHEOP_WAR 1
63 */
64
65/*
66 * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
67 */
68#ifdef CONFIG_SGI_IP22
69
70#define R4600_V1_INDEX_ICACHEOP_WAR 1
71#define R4600_V1_HIT_CACHEOP_WAR 1
72#define R4600_V2_HIT_CACHEOP_WAR 1
73
74#endif
75
76/*
77 * But the RM200C seems to have been shipped only with V2.0 R4600s
78 */
79#ifdef CONFIG_SNI_RM
80
81#define R4600_V2_HIT_CACHEOP_WAR 1
82
83#endif
84
85#ifdef CONFIG_CPU_R5432
86
87/*
88 * When an interrupt happens on a CP0 register read instruction, CPU may
89 * lock up or read corrupted values of CP0 registers after it enters
90 * the exception handler.
91 *
92 * This workaround makes sure that we read a "safe" CP0 register as the
93 * first thing in the exception handler, which breaks one of the
94 * pre-conditions for this problem.
95 */
96#define R5432_CP0_INTERRUPT_WAR 1
97
98#endif
99
100#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
101 defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
102
103/*
104 * Workaround for the Sibyte M3 errata the text of which can be found at
105 *
106 * http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt
107 *
108 * This will enable the use of a special TLB refill handler which does a
109 * consistency check on the information in c0_badvaddr and c0_entryhi and
110 * will just return and take the exception again if the information was
111 * found to be inconsistent.
112 */
113#define BCM1250_M3_WAR 1
114
115/*
116 * This is a DUART workaround related to glitches around register accesses
117 */
118#define SIBYTE_1956_WAR 1
119
120#endif
121
122/*
123 * Fill buffers not flushed on CACHE instructions
124 *
125 * Hit_Invalidate_I cacheops invalidate an icache line but the refill
126 * for that line can get stale data from the fill buffer instead of
127 * accessing memory if the previous icache miss was also to that line.
128 *
129 * Workaround: generate an icache refill from a different line
130 *
131 * Affects:
132 * MIPS 4K RTL revision <3.0, PRID revision <4
133 */
134#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \
135 defined(CONFIG_MIPS_SEAD)
136#define MIPS4K_ICACHE_REFILL_WAR 1
137#endif
138
139/*
140 * Missing implicit forced flush of evictions caused by CACHE
141 * instruction
142 *
143 * Evictions caused by a CACHE instructions are not forced on to the
144 * bus. The BIU gives higher priority to fetches than to the data from
145 * the eviction buffer and no collision detection is performed between
146 * fetches and pending data from the eviction buffer.
147 *
148 * Workaround: Execute a SYNC instruction after the cache instruction
149 *
150 * Affects:
151 * MIPS 5Kc,5Kf RTL revision <2.3, PRID revision <8
152 * MIPS 20Kc RTL revision <4.0, PRID revision <?
153 */
154#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \
155 defined(CONFIG_MIPS_SEAD)
156#define MIPS_CACHE_SYNC_WAR 1
157#endif
158
159/*
160 * From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
161 * the line which this instruction itself exists, the following
162 * operation is not guaranteed."
163 *
164 * Workaround: do two phase flushing for Index_Invalidate_I
165 */
166#ifdef CONFIG_CPU_TX49XX
167#define TX49XX_ICACHE_INDEX_INV_WAR 1
168#endif
169
170/*
171 * On the RM9000 there is a problem which makes the CreateDirtyExclusive
172 * eache operation unusable on SMP systems.
173 */
174#if defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE)
175#define RM9000_CDEX_SMP_WAR 1
176#endif
177
178/*
179 * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
180 * opposes it being called that) where invalid instructions in the same
181 * I-cache line worth of instructions being fetched may case spurious
182 * exceptions.
183 */
184#if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MIPS_ATLAS) || \
185 defined(CONFIG_MIPS_MALTA) || defined(CONFIG_PMC_YOSEMITE) || \
186 defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC)
187#define ICACHE_REFILLS_WORKAROUND_WAR 1
188#endif
189
190/*
191 * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
192 * may cause ll / sc and lld / scd sequences to execute non-atomically.
193 */
194#ifdef CONFIG_SGI_IP27
195#define R10000_LLSC_WAR 1
196#endif
197
198/*
199 * 34K core erratum: "Problems Executing the TLBR Instruction"
200 */
201#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
202 defined(CONFIG_PMC_MSP7120_FPGA)
203#define MIPS34K_MISSED_ITLB_WAR 1
204#endif
205
206/*
207 * Workarounds default to off
208 */
209#ifndef ICACHE_REFILLS_WORKAROUND_WAR
210#define ICACHE_REFILLS_WORKAROUND_WAR 0
211#endif
212#ifndef R4600_V1_INDEX_ICACHEOP_WAR
213#define R4600_V1_INDEX_ICACHEOP_WAR 0
214#endif
215#ifndef R4600_V1_HIT_CACHEOP_WAR
216#define R4600_V1_HIT_CACHEOP_WAR 0
217#endif
218#ifndef R4600_V2_HIT_CACHEOP_WAR
219#define R4600_V2_HIT_CACHEOP_WAR 0
220#endif
221#ifndef R5432_CP0_INTERRUPT_WAR
222#define R5432_CP0_INTERRUPT_WAR 0
223#endif
224#ifndef BCM1250_M3_WAR
225#define BCM1250_M3_WAR 0
226#endif
227#ifndef SIBYTE_1956_WAR
228#define SIBYTE_1956_WAR 0
229#endif
230#ifndef MIPS4K_ICACHE_REFILL_WAR
231#define MIPS4K_ICACHE_REFILL_WAR 0
232#endif
233#ifndef MIPS_CACHE_SYNC_WAR
234#define MIPS_CACHE_SYNC_WAR 0
235#endif
236#ifndef TX49XX_ICACHE_INDEX_INV_WAR
237#define TX49XX_ICACHE_INDEX_INV_WAR 0
238#endif
239#ifndef RM9000_CDEX_SMP_WAR
240#define RM9000_CDEX_SMP_WAR 0
241#endif
242#ifndef R10000_LLSC_WAR
243#define R10000_LLSC_WAR 0
244#endif
245#ifndef MIPS34K_MISSED_ITLB_WAR
246#define MIPS34K_MISSED_ITLB_WAR 0
247#endif
248
249#endif /* _ASM_WAR_H */