Linux kernel mirror (for testing)
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1/*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX4_DEVICE_H
34#define MLX4_DEVICE_H
35
36#include <linux/pci.h>
37#include <linux/completion.h>
38#include <linux/radix-tree.h>
39
40#include <asm/atomic.h>
41
42enum {
43 MLX4_FLAG_MSI_X = 1 << 0,
44 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
45};
46
47enum {
48 MLX4_MAX_PORTS = 2
49};
50
51enum {
52 MLX4_DEV_CAP_FLAG_RC = 1 << 0,
53 MLX4_DEV_CAP_FLAG_UC = 1 << 1,
54 MLX4_DEV_CAP_FLAG_UD = 1 << 2,
55 MLX4_DEV_CAP_FLAG_SRQ = 1 << 6,
56 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7,
57 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8,
58 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9,
59 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16,
60 MLX4_DEV_CAP_FLAG_APM = 1 << 17,
61 MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18,
62 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19,
63 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20,
64 MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21
65};
66
67enum mlx4_event {
68 MLX4_EVENT_TYPE_COMP = 0x00,
69 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
70 MLX4_EVENT_TYPE_COMM_EST = 0x02,
71 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
72 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
73 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
74 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
75 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
76 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
77 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
78 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
79 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
80 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
81 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
82 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
83 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
84 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
85 MLX4_EVENT_TYPE_CMD = 0x0a
86};
87
88enum {
89 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
90 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
91};
92
93enum {
94 MLX4_PERM_LOCAL_READ = 1 << 10,
95 MLX4_PERM_LOCAL_WRITE = 1 << 11,
96 MLX4_PERM_REMOTE_READ = 1 << 12,
97 MLX4_PERM_REMOTE_WRITE = 1 << 13,
98 MLX4_PERM_ATOMIC = 1 << 14
99};
100
101enum {
102 MLX4_OPCODE_NOP = 0x00,
103 MLX4_OPCODE_SEND_INVAL = 0x01,
104 MLX4_OPCODE_RDMA_WRITE = 0x08,
105 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
106 MLX4_OPCODE_SEND = 0x0a,
107 MLX4_OPCODE_SEND_IMM = 0x0b,
108 MLX4_OPCODE_LSO = 0x0e,
109 MLX4_OPCODE_RDMA_READ = 0x10,
110 MLX4_OPCODE_ATOMIC_CS = 0x11,
111 MLX4_OPCODE_ATOMIC_FA = 0x12,
112 MLX4_OPCODE_ATOMIC_MASK_CS = 0x14,
113 MLX4_OPCODE_ATOMIC_MASK_FA = 0x15,
114 MLX4_OPCODE_BIND_MW = 0x18,
115 MLX4_OPCODE_FMR = 0x19,
116 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
117 MLX4_OPCODE_CONFIG_CMD = 0x1f,
118
119 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
120 MLX4_RECV_OPCODE_SEND = 0x01,
121 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
122 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
123
124 MLX4_CQE_OPCODE_ERROR = 0x1e,
125 MLX4_CQE_OPCODE_RESIZE = 0x16,
126};
127
128enum {
129 MLX4_STAT_RATE_OFFSET = 5
130};
131
132struct mlx4_caps {
133 u64 fw_ver;
134 int num_ports;
135 int vl_cap[MLX4_MAX_PORTS + 1];
136 int mtu_cap[MLX4_MAX_PORTS + 1];
137 int gid_table_len[MLX4_MAX_PORTS + 1];
138 int pkey_table_len[MLX4_MAX_PORTS + 1];
139 int local_ca_ack_delay;
140 int num_uars;
141 int bf_reg_size;
142 int bf_regs_per_page;
143 int max_sq_sg;
144 int max_rq_sg;
145 int num_qps;
146 int max_wqes;
147 int max_sq_desc_sz;
148 int max_rq_desc_sz;
149 int max_qp_init_rdma;
150 int max_qp_dest_rdma;
151 int reserved_qps;
152 int sqp_start;
153 int num_srqs;
154 int max_srq_wqes;
155 int max_srq_sge;
156 int reserved_srqs;
157 int num_cqs;
158 int max_cqes;
159 int reserved_cqs;
160 int num_eqs;
161 int reserved_eqs;
162 int num_mpts;
163 int num_mtt_segs;
164 int fmr_reserved_mtts;
165 int reserved_mtts;
166 int reserved_mrws;
167 int reserved_uars;
168 int num_mgms;
169 int num_amgms;
170 int reserved_mcgs;
171 int num_qp_per_mgm;
172 int num_pds;
173 int reserved_pds;
174 int mtt_entry_sz;
175 u32 max_msg_sz;
176 u32 page_size_cap;
177 u32 flags;
178 u16 stat_rate_support;
179 u8 port_width_cap[MLX4_MAX_PORTS + 1];
180};
181
182struct mlx4_buf_list {
183 void *buf;
184 dma_addr_t map;
185};
186
187struct mlx4_buf {
188 union {
189 struct mlx4_buf_list direct;
190 struct mlx4_buf_list *page_list;
191 } u;
192 int nbufs;
193 int npages;
194 int page_shift;
195};
196
197struct mlx4_mtt {
198 u32 first_seg;
199 int order;
200 int page_shift;
201};
202
203struct mlx4_mr {
204 struct mlx4_mtt mtt;
205 u64 iova;
206 u64 size;
207 u32 key;
208 u32 pd;
209 u32 access;
210 int enabled;
211};
212
213struct mlx4_uar {
214 unsigned long pfn;
215 int index;
216};
217
218struct mlx4_cq {
219 void (*comp) (struct mlx4_cq *);
220 void (*event) (struct mlx4_cq *, enum mlx4_event);
221
222 struct mlx4_uar *uar;
223
224 u32 cons_index;
225
226 __be32 *set_ci_db;
227 __be32 *arm_db;
228 int arm_sn;
229
230 int cqn;
231
232 atomic_t refcount;
233 struct completion free;
234};
235
236struct mlx4_qp {
237 void (*event) (struct mlx4_qp *, enum mlx4_event);
238
239 int qpn;
240
241 atomic_t refcount;
242 struct completion free;
243};
244
245struct mlx4_srq {
246 void (*event) (struct mlx4_srq *, enum mlx4_event);
247
248 int srqn;
249 int max;
250 int max_gs;
251 int wqe_shift;
252
253 atomic_t refcount;
254 struct completion free;
255};
256
257struct mlx4_av {
258 __be32 port_pd;
259 u8 reserved1;
260 u8 g_slid;
261 __be16 dlid;
262 u8 reserved2;
263 u8 gid_index;
264 u8 stat_rate;
265 u8 hop_limit;
266 __be32 sl_tclass_flowlabel;
267 u8 dgid[16];
268};
269
270struct mlx4_dev {
271 struct pci_dev *pdev;
272 unsigned long flags;
273 struct mlx4_caps caps;
274 struct radix_tree_root qp_table_tree;
275};
276
277struct mlx4_init_port_param {
278 int set_guid0;
279 int set_node_guid;
280 int set_si_guid;
281 u16 mtu;
282 int port_width_cap;
283 u16 vl_cap;
284 u16 max_gid;
285 u16 max_pkey;
286 u64 guid0;
287 u64 node_guid;
288 u64 si_guid;
289};
290
291int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
292 struct mlx4_buf *buf);
293void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
294
295int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
296void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
297
298int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
299void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
300
301int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
302 struct mlx4_mtt *mtt);
303void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
304u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
305
306int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
307 int npages, int page_shift, struct mlx4_mr *mr);
308void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
309int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
310int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
311 int start_index, int npages, u64 *page_list);
312int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
313 struct mlx4_buf *buf);
314
315int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
316 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq);
317void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
318
319int mlx4_qp_alloc(struct mlx4_dev *dev, int sqpn, struct mlx4_qp *qp);
320void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
321
322int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
323 u64 db_rec, struct mlx4_srq *srq);
324void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
325int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
326int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
327
328int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
329int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
330
331int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
332int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
333
334#endif /* MLX4_DEVICE_H */