tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Defines of the MIPS boards specific address-MAP, registers, etc.
19 */
20#ifndef __ASM_MIPS_BOARDS_GENERIC_H
21#define __ASM_MIPS_BOARDS_GENERIC_H
22
23#include <asm/addrspace.h>
24#include <asm/byteorder.h>
25#include <asm/mips-boards/bonito64.h>
26
27/*
28 * Display register base.
29 */
30#ifdef CONFIG_MIPS_SEAD
31#define ASCII_DISPLAY_POS_BASE 0x1f0005c0
32#else
33#define ASCII_DISPLAY_WORD_BASE 0x1f000410
34#define ASCII_DISPLAY_POS_BASE 0x1f000418
35#endif
36
37
38/*
39 * Yamon Prom print address.
40 */
41#define YAMON_PROM_PRINT_ADDR 0x1fc00504
42
43
44/*
45 * Reset register.
46 */
47#ifdef CONFIG_MIPS_SEAD
48#define SOFTRES_REG 0x1e800050
49#define GORESET 0x4d
50#else
51#define SOFTRES_REG 0x1f000500
52#define GORESET 0x42
53#endif
54
55/*
56 * Revision register.
57 */
58#define MIPS_REVISION_REG 0x1fc00010
59#define MIPS_REVISION_CORID_QED_RM5261 0
60#define MIPS_REVISION_CORID_CORE_LV 1
61#define MIPS_REVISION_CORID_BONITO64 2
62#define MIPS_REVISION_CORID_CORE_20K 3
63#define MIPS_REVISION_CORID_CORE_FPGA 4
64#define MIPS_REVISION_CORID_CORE_MSC 5
65#define MIPS_REVISION_CORID_CORE_EMUL 6
66#define MIPS_REVISION_CORID_CORE_FPGA2 7
67#define MIPS_REVISION_CORID_CORE_FPGAR2 8
68#define MIPS_REVISION_CORID_CORE_FPGA3 9
69#define MIPS_REVISION_CORID_CORE_24K 10
70#define MIPS_REVISION_CORID_CORE_FPGA4 11
71
72/**** Artificial corid defines ****/
73/*
74 * CoreEMUL with Bonito System Controller is treated like a Core20K
75 * CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC
76 */
77#define MIPS_REVISION_CORID_CORE_EMUL_BON -1
78#define MIPS_REVISION_CORID_CORE_EMUL_MSC -2
79
80#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
81
82extern int mips_revision_corid;
83
84#define MIPS_REVISION_SCON_OTHER 0
85#define MIPS_REVISION_SCON_SOCITSC 1
86#define MIPS_REVISION_SCON_SOCITSCP 2
87
88/* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */
89#define MIPS_REVISION_SCON_UNKNOWN -1
90#define MIPS_REVISION_SCON_GT64120 -2
91#define MIPS_REVISION_SCON_BONITO -3
92#define MIPS_REVISION_SCON_BRTL -4
93#define MIPS_REVISION_SCON_SOCIT -5
94#define MIPS_REVISION_SCON_ROCIT -6
95
96#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff)
97
98extern int mips_revision_sconid;
99
100#ifdef CONFIG_PCI
101extern void mips_pcibios_init(void);
102#else
103#define mips_pcibios_init() do { } while (0)
104#endif
105
106#endif /* __ASM_MIPS_BOARDS_GENERIC_H */