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1/*
2 * include/asm-xtensa/elf.h
3 *
4 * ELF register definitions
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2001 - 2005 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_ELF_H
14#define _XTENSA_ELF_H
15
16#include <asm/ptrace.h>
17
18/* Xtensa processor ELF architecture-magic number */
19
20#define EM_XTENSA 94
21#define EM_XTENSA_OLD 0xABC7
22
23/* ELF register definitions. This is needed for core dump support. */
24
25/*
26 * elf_gregset_t contains the application-level state in the following order:
27 * Processor info: config_version, cpuxy
28 * Processor state: pc, ps, exccause, excvaddr, wb, ws,
29 * lbeg, lend, lcount, sar
30 * GP regs: ar0 - arXX
31 */
32
33typedef unsigned long elf_greg_t;
34
35typedef struct {
36 elf_greg_t xchal_config_id0;
37 elf_greg_t xchal_config_id1;
38 elf_greg_t cpux;
39 elf_greg_t cpuy;
40 elf_greg_t pc;
41 elf_greg_t ps;
42 elf_greg_t exccause;
43 elf_greg_t excvaddr;
44 elf_greg_t windowbase;
45 elf_greg_t windowstart;
46 elf_greg_t lbeg;
47 elf_greg_t lend;
48 elf_greg_t lcount;
49 elf_greg_t sar;
50 elf_greg_t syscall;
51 elf_greg_t ar[64];
52} xtensa_gregset_t;
53
54#define ELF_NGREG (sizeof(xtensa_gregset_t) / sizeof(elf_greg_t))
55
56typedef elf_greg_t elf_gregset_t[ELF_NGREG];
57
58/*
59 * Compute the size of the coprocessor and extra state layout (register info)
60 * table (in bytes).
61 * This is actually the maximum size of the table, as opposed to the size,
62 * which is available from the _xtensa_reginfo_table_size global variable.
63 *
64 * (See also arch/xtensa/kernel/coprocessor.S)
65 *
66 */
67
68#ifndef XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM
69# define XTENSA_CPE_LTABLE_SIZE 0
70#else
71# define XTENSA_CPE_SEGMENT(num) (num ? (1+num) : 0)
72# define XTENSA_CPE_LTABLE_ENTRIES \
73 ( XTENSA_CPE_SEGMENT(XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM) \
74 + XTENSA_CPE_SEGMENT(XCHAL_CP0_SA_CONTENTS_LIBDB_NUM) \
75 + XTENSA_CPE_SEGMENT(XCHAL_CP1_SA_CONTENTS_LIBDB_NUM) \
76 + XTENSA_CPE_SEGMENT(XCHAL_CP2_SA_CONTENTS_LIBDB_NUM) \
77 + XTENSA_CPE_SEGMENT(XCHAL_CP3_SA_CONTENTS_LIBDB_NUM) \
78 + XTENSA_CPE_SEGMENT(XCHAL_CP4_SA_CONTENTS_LIBDB_NUM) \
79 + XTENSA_CPE_SEGMENT(XCHAL_CP5_SA_CONTENTS_LIBDB_NUM) \
80 + XTENSA_CPE_SEGMENT(XCHAL_CP6_SA_CONTENTS_LIBDB_NUM) \
81 + XTENSA_CPE_SEGMENT(XCHAL_CP7_SA_CONTENTS_LIBDB_NUM) \
82 + 1 /* final entry */ \
83 )
84# define XTENSA_CPE_LTABLE_SIZE (XTENSA_CPE_LTABLE_ENTRIES * 8)
85#endif
86
87
88/*
89 * Instantiations of the elf_fpregset_t type contain, in most
90 * architectures, the floating point (FPU) register set.
91 * For Xtensa, this type is extended to contain all custom state,
92 * ie. coprocessor and "extra" (non-coprocessor) state (including,
93 * for example, TIE-defined states and register files; as well
94 * as other optional processor state).
95 * This includes FPU state if a floating-point coprocessor happens
96 * to have been configured within the Xtensa processor.
97 *
98 * TOTAL_FPREGS_SIZE is the required size (without rounding)
99 * of elf_fpregset_t. It provides space for the following:
100 *
101 * a) 32-bit mask of active coprocessors for this task (similar
102 * to CPENABLE in single-threaded Xtensa processor systems)
103 *
104 * b) table describing the layout of custom states (ie. of
105 * individual registers, etc) within the save areas
106 *
107 * c) save areas for each coprocessor and for non-coprocessor
108 * ("extra") state
109 *
110 * Note that save areas may require up to 16-byte alignment when
111 * accessed by save/restore sequences. We do not need to ensure
112 * such alignment in an elf_fpregset_t structure because custom
113 * state is not directly loaded/stored into it; rather, save area
114 * contents are copied to elf_fpregset_t from the active save areas
115 * (see 'struct task_struct' definition in processor.h for that)
116 * using memcpy(). But we do allow space for such alignment,
117 * to allow optimizations of layout and copying.
118 */
119#if 0
120#define TOTAL_FPREGS_SIZE \
121 (4 + XTENSA_CPE_LTABLE_SIZE + XTENSA_CP_EXTRA_SIZE)
122#define ELF_NFPREG \
123 ((TOTAL_FPREGS_SIZE + sizeof(elf_fpreg_t) - 1) / sizeof(elf_fpreg_t))
124#else
125#define TOTAL_FPREGS_SIZE 0
126#define ELF_NFPREG 0
127#endif
128
129typedef unsigned int elf_fpreg_t;
130typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
131
132#define ELF_CORE_COPY_REGS(_eregs, _pregs) \
133 xtensa_elf_core_copy_regs (&_eregs, _pregs);
134
135extern void xtensa_elf_core_copy_regs (xtensa_gregset_t *, struct pt_regs *);
136
137/*
138 * This is used to ensure we don't load something for the wrong architecture.
139 */
140
141#define elf_check_arch(x) ( ( (x)->e_machine == EM_XTENSA ) || \
142 ( (x)->e_machine == EM_XTENSA_OLD ) )
143
144/*
145 * These are used to set parameters in the core dumps.
146 */
147
148#ifdef __XTENSA_EL__
149# define ELF_DATA ELFDATA2LSB
150#elif defined(__XTENSA_EB__)
151# define ELF_DATA ELFDATA2MSB
152#else
153# error processor byte order undefined!
154#endif
155
156#define ELF_CLASS ELFCLASS32
157#define ELF_ARCH EM_XTENSA
158
159#define USE_ELF_CORE_DUMP
160#define ELF_EXEC_PAGESIZE PAGE_SIZE
161
162/*
163 * This is the location that an ET_DYN program is loaded if exec'ed. Typical
164 * use of this is to invoke "./ld.so someprog" to test out a new version of
165 * the loader. We need to make sure that it is out of the way of the program
166 * that it will "exec", and that there is sufficient room for the brk.
167 */
168
169#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
170
171/*
172 * This yields a mask that user programs can use to figure out what
173 * instruction set this CPU supports. This could be done in user space,
174 * but it's not easy, and we've already done it here.
175 */
176
177#define ELF_HWCAP (0)
178
179/*
180 * This yields a string that ld.so will use to load implementation
181 * specific libraries for optimization. This is more specific in
182 * intent than poking at uname or /proc/cpuinfo.
183 * For the moment, we have only optimizations for the Intel generations,
184 * but that could change...
185 */
186
187#define ELF_PLATFORM (NULL)
188
189/*
190 * The Xtensa processor ABI says that when the program starts, a2
191 * contains a pointer to a function which might be registered using
192 * `atexit'. This provides a mean for the dynamic linker to call
193 * DT_FINI functions for shared libraries that have been loaded before
194 * the code runs.
195 *
196 * A value of 0 tells we have no such handler.
197 *
198 * We might as well make sure everything else is cleared too (except
199 * for the stack pointer in a1), just to make things more
200 * deterministic. Also, clearing a0 terminates debugger backtraces.
201 */
202
203#define ELF_PLAT_INIT(_r, load_addr) \
204 do { _r->areg[0]=0; /*_r->areg[1]=0;*/ _r->areg[2]=0; _r->areg[3]=0; \
205 _r->areg[4]=0; _r->areg[5]=0; _r->areg[6]=0; _r->areg[7]=0; \
206 _r->areg[8]=0; _r->areg[9]=0; _r->areg[10]=0; _r->areg[11]=0; \
207 _r->areg[12]=0; _r->areg[13]=0; _r->areg[14]=0; _r->areg[15]=0; \
208 } while (0)
209
210#ifdef __KERNEL__
211
212#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT)
213
214struct task_struct;
215
216extern void do_copy_regs (xtensa_gregset_t*, struct pt_regs*,
217 struct task_struct*);
218extern void do_restore_regs (xtensa_gregset_t*, struct pt_regs*,
219 struct task_struct*);
220extern void do_save_fpregs (elf_fpregset_t*, struct pt_regs*,
221 struct task_struct*);
222extern int do_restore_fpregs (elf_fpregset_t*, struct pt_regs*,
223 struct task_struct*);
224
225#endif /* __KERNEL__ */
226#endif /* _XTENSA_ELF_H */