tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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kernel / include / asm-mips / tx4927 / tx4927.h
at v2.6.23-rc2 524 lines 28 kB view raw
1/* 2 * Author: MontaVista Software, Inc. 3 * source@mvista.com 4 * 5 * Copyright 2001-2006 MontaVista Software Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 15 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 17 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 18 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 19 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 20 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 21 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, write to the Free Software Foundation, Inc., 25 * 675 Mass Ave, Cambridge, MA 02139, USA. 26 */ 27#ifndef __ASM_TX4927_TX4927_H 28#define __ASM_TX4927_TX4927_H 29 30#include <asm/tx4927/tx4927_mips.h> 31 32/* 33 This register naming came from the integrated CPU/controller name TX4927 34 followed by the device name from table 4.2.2 on page 4-3 and then followed 35 by the register name from table 4.2.3 on pages 4-4 to 4-8. The manaul 36 used was "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001". 37 */ 38 39#define TX4927_SIO_0_BASE 40 41/* TX4927 controller */ 42#define TX4927_BASE 0xfff1f0000 43#define TX4927_BASE 0xfff1f0000 44#define TX4927_LIMIT 0xfff1fffff 45 46 47/* TX4927 SDRAM controller (64-bit registers) */ 48#define TX4927_SDRAMC_BASE 0x8000 49#define TX4927_SDRAMC_SDCCR0 0x8000 50#define TX4927_SDRAMC_SDCCR1 0x8008 51#define TX4927_SDRAMC_SDCCR2 0x8010 52#define TX4927_SDRAMC_SDCCR3 0x8018 53#define TX4927_SDRAMC_SDCTR 0x8040 54#define TX4927_SDRAMC_SDCMD 0x8058 55#define TX4927_SDRAMC_LIMIT 0x8fff 56 57 58/* TX4927 external bus controller (64-bit registers) */ 59#define TX4927_EBUSC_BASE 0x9000 60#define TX4927_EBUSC_EBCCR0 0x9000 61#define TX4927_EBUSC_EBCCR1 0x9008 62#define TX4927_EBUSC_EBCCR2 0x9010 63#define TX4927_EBUSC_EBCCR3 0x9018 64#define TX4927_EBUSC_EBCCR4 0x9020 65#define TX4927_EBUSC_EBCCR5 0x9028 66#define TX4927_EBUSC_EBCCR6 0x9030 67#define TX4927_EBUSC_EBCCR7 0x9008 68#define TX4927_EBUSC_LIMIT 0x9fff 69 70 71/* TX4927 SDRRAM Error Check Correction (64-bit registers) */ 72#define TX4927_ECC_BASE 0xa000 73#define TX4927_ECC_ECCCR 0xa000 74#define TX4927_ECC_ECCSR 0xa008 75#define TX4927_ECC_LIMIT 0xafff 76 77 78/* TX4927 DMA Controller (64-bit registers) */ 79#define TX4927_DMAC_BASE 0xb000 80#define TX4927_DMAC_TBD 0xb000 81#define TX4927_DMAC_LIMIT 0xbfff 82 83 84/* TX4927 PCI Controller (32-bit registers) */ 85#define TX4927_PCIC_BASE 0xd000 86#define TX4927_PCIC_TBD 0xb000 87#define TX4927_PCIC_LIMIT 0xdfff 88 89 90/* TX4927 Configuration registers (64-bit registers) */ 91#define TX4927_CONFIG_BASE 0xe000 92#define TX4927_CONFIG_CCFG 0xe000 93#define TX4927_CONFIG_CCFG_RESERVED_42_63 BM_63_42 94#define TX4927_CONFIG_CCFG_WDRST BM_41_41 95#define TX4927_CONFIG_CCFG_WDREXEN BM_40_40 96#define TX4927_CONFIG_CCFG_BCFG BM_39_32 97#define TX4927_CONFIG_CCFG_RESERVED_27_31 BM_31_27 98#define TX4927_CONFIG_CCFG_GTOT BM_26_25 99#define TX4927_CONFIG_CCFG_GTOT_4096 BM_26_25 100#define TX4927_CONFIG_CCFG_GTOT_2048 BM_26_26 101#define TX4927_CONFIG_CCFG_GTOT_1024 BM_25_25 102#define TX4927_CONFIG_CCFG_GTOT_0512 (~BM_26_25) 103#define TX4927_CONFIG_CCFG_TINTDIS BM_24_24 104#define TX4927_CONFIG_CCFG_PCI66 BM_23_23 105#define TX4927_CONFIG_CCFG_PCIMODE BM_22_22 106#define TX4927_CONFIG_CCFG_RESERVED_20_21 BM_21_20 107#define TX4927_CONFIG_CCFG_DIVMODE BM_19_17 108#define TX4927_CONFIG_CCFG_DIVMODE_2_0 BM_19_19 109#define TX4927_CONFIG_CCFG_DIVMODE_3_0 (BM_19_19|BM_17_17) 110#define TX4927_CONFIG_CCFG_DIVMODE_4_0 BM_19_18 111#define TX4927_CONFIG_CCFG_DIVMODE_2_5 BM_19_17 112#define TX4927_CONFIG_CCFG_DIVMODE_8_0 (~BM_19_17) 113#define TX4927_CONFIG_CCFG_DIVMODE_12_0 BM_17_17 114#define TX4927_CONFIG_CCFG_DIVMODE_16_0 BM_18_18 115#define TX4927_CONFIG_CCFG_DIVMODE_10_0 BM_18_17 116#define TX4927_CONFIG_CCFG_BEOW BM_16_16 117#define TX4927_CONFIG_CCFG_WR BM_15_15 118#define TX4927_CONFIG_CCFG_TOE BM_14_14 119#define TX4927_CONFIG_CCFG_PCIARB BM_13_13 120#define TX4927_CONFIG_CCFG_PCIDIVMODE BM_12_11 121#define TX4927_CONFIG_CCFG_RESERVED_08_10 BM_10_08 122#define TX4927_CONFIG_CCFG_SYSSP BM_07_06 123#define TX4927_CONFIG_CCFG_RESERVED_03_05 BM_05_03 124#define TX4927_CONFIG_CCFG_ENDIAN BM_02_02 125#define TX4927_CONFIG_CCFG_ARMODE BM_01_01 126#define TX4927_CONFIG_CCFG_ACEHOLD BM_00_00 127#define TX4927_CONFIG_REVID 0xe008 128#define TX4927_CONFIG_REVID_RESERVED_32_63 BM_32_63 129#define TX4927_CONFIG_REVID_PCODE BM_16_31 130#define TX4927_CONFIG_REVID_MJERREV BM_12_15 131#define TX4927_CONFIG_REVID_MINEREV BM_08_11 132#define TX4927_CONFIG_REVID_MJREV BM_04_07 133#define TX4927_CONFIG_REVID_MINREV BM_00_03 134#define TX4927_CONFIG_PCFG 0xe010 135#define TX4927_CONFIG_PCFG_RESERVED_57_63 BM_57_63 136#define TX4927_CONFIG_PCFG_DRVDATA BM_56_56 137#define TX4927_CONFIG_PCFG_DRVCB BM_55_55 138#define TX4927_CONFIG_PCFG_DRVDQM BM_54_54 139#define TX4927_CONFIG_PCFG_DRVADDR BM_53_53 140#define TX4927_CONFIG_PCFG_DRVCKE BM_52_52 141#define TX4927_CONFIG_PCFG_DRVRAS BM_51_51 142#define TX4927_CONFIG_PCFG_DRVCAS BM_50_50 143#define TX4927_CONFIG_PCFG_DRVWE BM_49_49 144#define TX4927_CONFIG_PCFG_DRVCS3 BM_48_48 145#define TX4927_CONFIG_PCFG_DRVCS2 BM_47_47 146#define TX4927_CONFIG_PCFG_DRVCS1 BM_46_4k 147#define TX4927_CONFIG_PCFG_DRVCS0 BM_45_45 148#define TX4927_CONFIG_PCFG_DRVCK3 BM_44_44 149#define TX4927_CONFIG_PCFG_DRVCK2 BM_43_43 150#define TX4927_CONFIG_PCFG_DRVCK1 BM_42_42 151#define TX4927_CONFIG_PCFG_DRVCK0 BM_41_41 152#define TX4927_CONFIG_PCFG_DRVCKIN BM_40_40 153#define TX4927_CONFIG_PCFG_RESERVED_33_39 BM_33_39 154#define TX4927_CONFIG_PCFG_BYPASS_PLL BM_32_32 155#define TX4927_CONFIG_PCFG_RESERVED_30_31 BM_30_31 156#define TX4927_CONFIG_PCFG_SDCLKDLY BM_28_29 157#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_1 (~BM_28_29) 158#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_2 BM_28_28 159#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_3 BM_29_29 160#define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_4 BM_28_29 161#define TX4927_CONFIG_PCFG_SYSCLKEN BM_27_27 162#define TX4927_CONFIG_PCFG_SDCLKEN3 BM_26_26 163#define TX4927_CONFIG_PCFG_SDCLKEN2 BM_25_25 164#define TX4927_CONFIG_PCFG_SDCLKEN1 BM_24_24 165#define TX4927_CONFIG_PCFG_SDCLKEN0 BM_23_23 166#define TX4927_CONFIG_PCFG_SDCLKINEN BM_22_22 167#define TX4927_CONFIG_PCFG_PCICLKEN5 BM_21_21 168#define TX4927_CONFIG_PCFG_PCICLKEN4 BM_20_20 169#define TX4927_CONFIG_PCFG_PCICLKEN3 BM_19_19 170#define TX4927_CONFIG_PCFG_PCICLKEN2 BM_18_18 171#define TX4927_CONFIG_PCFG_PCICLKEN1 BM_17_17 172#define TX4927_CONFIG_PCFG_PCICLKEN0 BM_16_16 173#define TX4927_CONFIG_PCFG_RESERVED_10_15 BM_10_15 174#define TX4927_CONFIG_PCFG_SEL2 BM_09_09 175#define TX4927_CONFIG_PCFG_SEL1 BM_08_08 176#define TX4927_CONFIG_PCFG_DMASEL3 BM_06_07 177#define TX4927_CONFIG_PCFG_DMASEL3_DMAREQ3 (~BM_06_07) 178#define TX4927_CONFIG_PCFG_DMASEL3_SIO0 BM_06_06 179#define TX4927_CONFIG_PCFG_DMASEL3_ACLC3 BM_07_07 180#define TX4927_CONFIG_PCFG_DMASEL3_ACLC1 BM_06_07 181#define TX4927_CONFIG_PCFG_DMASEL2 BM_06_07 182#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_DMAREQ2 (~BM_06_07) 183#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_SIO0 BM_06_06 184#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_10 BM_07_07 185#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_11 BM_06_07 186#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC1 (~BM_06_07) 187#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_SIO0 BM_06_06 188#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC2 BM_07_07 189#define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC0 BM_06_07 190#define TX4927_CONFIG_PCFG_DMASEL1 BM_02_03 191#define TX4927_CONFIG_PCFG_DMASEL1_DMAREQ1 (~BM_02_03) 192#define TX4927_CONFIG_PCFG_DMASEL1_SIO1 BM_02_02 193#define TX4927_CONFIG_PCFG_DMASEL1_ACLC1 BM_03_03 194#define TX4927_CONFIG_PCFG_DMASEL1_ACLC3 BM_02_03 195#define TX4927_CONFIG_PCFG_DMASEL0 BM_00_01 196#define TX4927_CONFIG_PCFG_DMASEL0_DMAREQ0 (~BM_00_01) 197#define TX4927_CONFIG_PCFG_DMASEL0_SIO1 BM_00_00 198#define TX4927_CONFIG_PCFG_DMASEL0_ACLC0 BM_01_01 199#define TX4927_CONFIG_PCFG_DMASEL0_ACLC2 BM_00_01 200#define TX4927_CONFIG_TOEA 0xe018 201#define TX4927_CONFIG_TOEA_RESERVED_36_63 BM_36_63 202#define TX4927_CONFIG_TOEA_TOEA BM_00_35 203#define TX4927_CONFIG_CLKCTR 0xe020 204#define TX4927_CONFIG_CLKCTR_RESERVED_26_63 BM_26_63 205#define TX4927_CONFIG_CLKCTR_ACLCKD BM_25_25 206#define TX4927_CONFIG_CLKCTR_PIOCKD BM_24_24 207#define TX4927_CONFIG_CLKCTR_DMACKD BM_23_23 208#define TX4927_CONFIG_CLKCTR_PCICKD BM_22_22 209#define TX4927_CONFIG_CLKCTR_SET_21 BM_21_21 210#define TX4927_CONFIG_CLKCTR_TM0CKD BM_20_20 211#define TX4927_CONFIG_CLKCTR_TM1CKD BM_19_19 212#define TX4927_CONFIG_CLKCTR_TM2CKD BM_18_18 213#define TX4927_CONFIG_CLKCTR_SIO0CKD BM_17_17 214#define TX4927_CONFIG_CLKCTR_SIO1CKD BM_16_16 215#define TX4927_CONFIG_CLKCTR_RESERVED_10_15 BM_10_15 216#define TX4927_CONFIG_CLKCTR_ACLRST BM_09_09 217#define TX4927_CONFIG_CLKCTR_PIORST BM_08_08 218#define TX4927_CONFIG_CLKCTR_DMARST BM_07_07 219#define TX4927_CONFIG_CLKCTR_PCIRST BM_06_06 220#define TX4927_CONFIG_CLKCTR_RESERVED_05_05 BM_05_05 221#define TX4927_CONFIG_CLKCTR_TM0RST BM_04_04 222#define TX4927_CONFIG_CLKCTR_TM1RST BM_03_03 223#define TX4927_CONFIG_CLKCTR_TM2RST BM_02_02 224#define TX4927_CONFIG_CLKCTR_SIO0RST BM_01_01 225#define TX4927_CONFIG_CLKCTR_SIO1RST BM_00_00 226#define TX4927_CONFIG_GARBC 0xe030 227#define TX4927_CONFIG_GARBC_RESERVED_10_63 BM_10_63 228#define TX4927_CONFIG_GARBC_SET_09 BM_09_09 229#define TX4927_CONFIG_GARBC_ARBMD BM_08_08 230#define TX4927_CONFIG_GARBC_RESERVED_06_07 BM_06_07 231#define TX4927_CONFIG_GARBC_PRIORITY_H1 BM_04_05 232#define TX4927_CONFIG_GARBC_PRIORITY_H1_PCI (~BM_04_05) 233#define TX4927_CONFIG_GARBC_PRIORITY_H1_PDMAC BM_04_04 234#define TX4927_CONFIG_GARBC_PRIORITY_H1_DMAC BM_05_05 235#define TX4927_CONFIG_GARBC_PRIORITY_H1_BAD_VALUE BM_04_05 236#define TX4927_CONFIG_GARBC_PRIORITY_H2 BM_02_03 237#define TX4927_CONFIG_GARBC_PRIORITY_H2_PCI (~BM_02_03) 238#define TX4927_CONFIG_GARBC_PRIORITY_H2_PDMAC BM_02_02 239#define TX4927_CONFIG_GARBC_PRIORITY_H2_DMAC BM_03_03 240#define TX4927_CONFIG_GARBC_PRIORITY_H2_BAD_VALUE BM_02_03 241#define TX4927_CONFIG_GARBC_PRIORITY_H3 BM_00_01 242#define TX4927_CONFIG_GARBC_PRIORITY_H3_PCI (~BM_00_01) 243#define TX4927_CONFIG_GARBC_PRIORITY_H3_PDMAC BM_00_00 244#define TX4927_CONFIG_GARBC_PRIORITY_H3_DMAC BM_01_01 245#define TX4927_CONFIG_GARBC_PRIORITY_H3_BAD_VALUE BM_00_01 246#define TX4927_CONFIG_RAMP 0xe048 247#define TX4927_CONFIG_RAMP_RESERVED_20_63 BM_20_63 248#define TX4927_CONFIG_RAMP_RAMP BM_00_19 249#define TX4927_CONFIG_LIMIT 0xefff 250 251 252/* TX4927 Timer 0 (32-bit registers) */ 253#define TX4927_TMR0_BASE 0xf000 254#define TX4927_TMR0_TMTCR0 0xf000 255#define TX4927_TMR0_TMTISR0 0xf004 256#define TX4927_TMR0_TMCPRA0 0xf008 257#define TX4927_TMR0_TMCPRB0 0xf00c 258#define TX4927_TMR0_TMITMR0 0xf010 259#define TX4927_TMR0_TMCCDR0 0xf020 260#define TX4927_TMR0_TMPGMR0 0xf030 261#define TX4927_TMR0_TMTRR0 0xf0f0 262#define TX4927_TMR0_LIMIT 0xf0ff 263 264 265/* TX4927 Timer 1 (32-bit registers) */ 266#define TX4927_TMR1_BASE 0xf100 267#define TX4927_TMR1_TMTCR1 0xf100 268#define TX4927_TMR1_TMTISR1 0xf104 269#define TX4927_TMR1_TMCPRA1 0xf108 270#define TX4927_TMR1_TMCPRB1 0xf10c 271#define TX4927_TMR1_TMITMR1 0xf110 272#define TX4927_TMR1_TMCCDR1 0xf120 273#define TX4927_TMR1_TMPGMR1 0xf130 274#define TX4927_TMR1_TMTRR1 0xf1f0 275#define TX4927_TMR1_LIMIT 0xf1ff 276 277 278/* TX4927 Timer 2 (32-bit registers) */ 279#define TX4927_TMR2_BASE 0xf200 280#define TX4927_TMR2_TMTCR2 0xf200 281#define TX4927_TMR2_TMTISR2 0xf204 282#define TX4927_TMR2_TMCPRA2 0xf208 283#define TX4927_TMR2_TMITMR2 0xf210 284#define TX4927_TMR2_TMCCDR2 0xf220 285#define TX4927_TMR2_TMWTMR2 0xf240 286#define TX4927_TMR2_TMTRR2 0xf2f0 287#define TX4927_TMR2_LIMIT 0xf2ff 288 289 290/* TX4927 serial port 0 (32-bit registers) */ 291#define TX4927_SIO0_BASE 0xf300 292#define TX4927_SIO0_SILCR0 0xf300 293#define TX4927_SIO0_SILCR0_RESERVED_16_31 BM_16_31 294#define TX4927_SIO0_SILCR0_RWUB BM_15_15 295#define TX4927_SIO0_SILCR0_TWUB BM_14_14 296#define TX4927_SIO0_SILCR0_UODE BM_13_13 297#define TX4927_SIO0_SILCR0_RESERVED_07_12 BM_07_12 298#define TX4927_SIO0_SILCR0_SCS BM_05_06 299#define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_IC (~BM_05_06) 300#define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_BRG BM_05_05 301#define TX4927_SIO0_SILCR0_SCS_SCLK_EC BM_06_06 302#define TX4927_SIO0_SILCR0_SCS_SCLK_BRG BM_05_06 303#define TX4927_SIO0_SILCR0_UEPS BM_04_04 304#define TX4927_SIO0_SILCR0_UPEN BM_03_03 305#define TX4927_SIO0_SILCR0_USBL BM_02_02 306#define TX4927_SIO0_SILCR0_UMODE BM_00_01 307#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT BM_00_01 308#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT (~BM_00_01) 309#define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC BM_01_01 310#define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC BM_00_01 311#define TX4927_SIO0_SIDICR0 0xf304 312#define TX4927_SIO0_SIDICR0_RESERVED_16_31 BM_16_31 313#define TX4927_SIO0_SIDICR0_TDE BM_15_15 314#define TX4927_SIO0_SIDICR0_RDE BM_14_14 315#define TX4927_SIO0_SIDICR0_TIE BM_13_13 316#define TX4927_SIO0_SIDICR0_RIE BM_12_12 317#define TX4927_SIO0_SIDICR0_SPIE BM_11_11 318#define TX4927_SIO0_SIDICR0_CTSAC BM_09_10 319#define TX4927_SIO0_SIDICR0_CTSAC_NONE (~BM_09_10) 320#define TX4927_SIO0_SIDICR0_CTSAC_RISE BM_09_09 321#define TX4927_SIO0_SIDICR0_CTSAC_FALL BM_10_10 322#define TX4927_SIO0_SIDICR0_CTSAC_BOTH BM_09_10 323#define TX4927_SIO0_SIDICR0_RESERVED_06_08 BM_06_08 324#define TX4927_SIO0_SIDICR0_STIE BM_00_05 325#define TX4927_SIO0_SIDICR0_STIE_NONE (~BM_00_05) 326#define TX4927_SIO0_SIDICR0_STIE_OERS BM_05_05 327#define TX4927_SIO0_SIDICR0_STIE_CTSAC BM_04_04 328#define TX4927_SIO0_SIDICR0_STIE_RBRKD BM_03_03 329#define TX4927_SIO0_SIDICR0_STIE_TRDY BM_02_02 330#define TX4927_SIO0_SIDICR0_STIE_TXALS BM_01_01 331#define TX4927_SIO0_SIDICR0_STIE_UBRKD BM_00_00 332#define TX4927_SIO0_SIDISR0 0xf308 333#define TX4927_SIO0_SIDISR0_RESERVED_16_31 BM_16_31 334#define TX4927_SIO0_SIDISR0_UBRK BM_15_15 335#define TX4927_SIO0_SIDISR0_UVALID BM_14_14 336#define TX4927_SIO0_SIDISR0_UFER BM_13_13 337#define TX4927_SIO0_SIDISR0_UPER BM_12_12 338#define TX4927_SIO0_SIDISR0_UOER BM_11_11 339#define TX4927_SIO0_SIDISR0_ERI BM_10_10 340#define TX4927_SIO0_SIDISR0_TOUT BM_09_09 341#define TX4927_SIO0_SIDISR0_TDIS BM_08_08 342#define TX4927_SIO0_SIDISR0_RDIS BM_07_07 343#define TX4927_SIO0_SIDISR0_STIS BM_06_06 344#define TX4927_SIO0_SIDISR0_RESERVED_05_05 BM_05_05 345#define TX4927_SIO0_SIDISR0_RFDN BM_00_04 346#define TX4927_SIO0_SISCISR0 0xf30c 347#define TX4927_SIO0_SISCISR0_RESERVED_06_31 BM_06_31 348#define TX4927_SIO0_SISCISR0_OERS BM_05_05 349#define TX4927_SIO0_SISCISR0_CTSS BM_04_04 350#define TX4927_SIO0_SISCISR0_RBRKD BM_03_03 351#define TX4927_SIO0_SISCISR0_TRDY BM_02_02 352#define TX4927_SIO0_SISCISR0_TXALS BM_01_01 353#define TX4927_SIO0_SISCISR0_UBRKD BM_00_00 354#define TX4927_SIO0_SIFCR0 0xf310 355#define TX4927_SIO0_SIFCR0_RESERVED_16_31 BM_16_31 356#define TX4927_SIO0_SIFCR0_SWRST BM_16_31 357#define TX4927_SIO0_SIFCR0_RESERVED_09_14 BM_09_14 358#define TX4927_SIO0_SIFCR0_RDIL BM_16_31 359#define TX4927_SIO0_SIFCR0_RDIL_BYTES_1 (~BM_07_08) 360#define TX4927_SIO0_SIFCR0_RDIL_BYTES_4 BM_07_07 361#define TX4927_SIO0_SIFCR0_RDIL_BYTES_8 BM_08_08 362#define TX4927_SIO0_SIFCR0_RDIL_BYTES_12 BM_07_08 363#define TX4927_SIO0_SIFCR0_RESERVED_05_06 BM_05_06 364#define TX4927_SIO0_SIFCR0_TDIL BM_03_04 365#define TX4927_SIO0_SIFCR0_TDIL_BYTES_1 (~BM_03_04) 366#define TX4927_SIO0_SIFCR0_TDIL_BYTES_4 BM_03_03 367#define TX4927_SIO0_SIFCR0_TDIL_BYTES_8 BM_04_04 368#define TX4927_SIO0_SIFCR0_TDIL_BYTES_0 BM_03_04 369#define TX4927_SIO0_SIFCR0_TFRST BM_02_02 370#define TX4927_SIO0_SIFCR0_RFRST BM_01_01 371#define TX4927_SIO0_SIFCR0_FRSTE BM_00_00 372#define TX4927_SIO0_SIFLCR0 0xf314 373#define TX4927_SIO0_SIFLCR0_RESERVED_13_31 BM_13_31 374#define TX4927_SIO0_SIFLCR0_RCS BM_12_12 375#define TX4927_SIO0_SIFLCR0_TES BM_11_11 376#define TX4927_SIO0_SIFLCR0_RESERVED_10_10 BM_10_10 377#define TX4927_SIO0_SIFLCR0_RTSSC BM_09_09 378#define TX4927_SIO0_SIFLCR0_RSDE BM_08_08 379#define TX4927_SIO0_SIFLCR0_TSDE BM_07_07 380#define TX4927_SIO0_SIFLCR0_RESERVED_05_06 BM_05_06 381#define TX4927_SIO0_SIFLCR0_RTSTL BM_01_04 382#define TX4927_SIO0_SIFLCR0_TBRK BM_00_00 383#define TX4927_SIO0_SIBGR0 0xf318 384#define TX4927_SIO0_SIBGR0_RESERVED_10_31 BM_10_31 385#define TX4927_SIO0_SIBGR0_BCLK BM_08_09 386#define TX4927_SIO0_SIBGR0_BCLK_T0 (~BM_08_09) 387#define TX4927_SIO0_SIBGR0_BCLK_T2 BM_08_08 388#define TX4927_SIO0_SIBGR0_BCLK_T4 BM_09_09 389#define TX4927_SIO0_SIBGR0_BCLK_T6 BM_08_09 390#define TX4927_SIO0_SIBGR0_BRD BM_00_07 391#define TX4927_SIO0_SITFIF00 0xf31c 392#define TX4927_SIO0_SITFIF00_RESERVED_08_31 BM_08_31 393#define TX4927_SIO0_SITFIF00_TXD BM_00_07 394#define TX4927_SIO0_SIRFIFO0 0xf320 395#define TX4927_SIO0_SIRFIFO0_RESERVED_08_31 BM_08_31 396#define TX4927_SIO0_SIRFIFO0_RXD BM_00_07 397#define TX4927_SIO0_SIRFIFO0 0xf320 398#define TX4927_SIO0_LIMIT 0xf3ff 399 400 401/* TX4927 serial port 1 (32-bit registers) */ 402#define TX4927_SIO1_BASE 0xf400 403#define TX4927_SIO1_SILCR1 0xf400 404#define TX4927_SIO1_SIDICR1 0xf404 405#define TX4927_SIO1_SIDISR1 0xf408 406#define TX4927_SIO1_SISCISR1 0xf40c 407#define TX4927_SIO1_SIFCR1 0xf410 408#define TX4927_SIO1_SIFLCR1 0xf414 409#define TX4927_SIO1_SIBGR1 0xf418 410#define TX4927_SIO1_SITFIF01 0xf41c 411#define TX4927_SIO1_SIRFIFO1 0xf420 412#define TX4927_SIO1_LIMIT 0xf4ff 413 414 415/* TX4927 parallel port (32-bit registers) */ 416#define TX4927_PIO_BASE 0xf500 417#define TX4927_PIO_PIOD0 0xf500 418#define TX4927_PIO_PIODI 0xf504 419#define TX4927_PIO_PIODIR 0xf508 420#define TX4927_PIO_PIOOD 0xf50c 421#define TX4927_PIO_LIMIT 0xf50f 422 423 424/* TX4927 Interrupt Controller (32-bit registers) */ 425#define TX4927_IRC_BASE 0xf510 426#define TX4927_IRC_IRFLAG0 0xf510 427#define TX4927_IRC_IRFLAG1 0xf514 428#define TX4927_IRC_IRPOL 0xf518 429#define TX4927_IRC_IRRCNT 0xf51c 430#define TX4927_IRC_IRMASKINT 0xf520 431#define TX4927_IRC_IRMASKEXT 0xf524 432#define TX4927_IRC_IRDEN 0xf600 433#define TX4927_IRC_IRDM0 0xf604 434#define TX4927_IRC_IRDM1 0xf608 435#define TX4927_IRC_IRLVL0 0xf610 436#define TX4927_IRC_IRLVL1 0xf614 437#define TX4927_IRC_IRLVL2 0xf618 438#define TX4927_IRC_IRLVL3 0xf61c 439#define TX4927_IRC_IRLVL4 0xf620 440#define TX4927_IRC_IRLVL5 0xf624 441#define TX4927_IRC_IRLVL6 0xf628 442#define TX4927_IRC_IRLVL7 0xf62c 443#define TX4927_IRC_IRMSK 0xf640 444#define TX4927_IRC_IREDC 0xf660 445#define TX4927_IRC_IRPND 0xf680 446#define TX4927_IRC_IRCS 0xf6a0 447#define TX4927_IRC_LIMIT 0xf6ff 448 449 450/* TX4927 AC-link controller (32-bit registers) */ 451#define TX4927_ACLC_BASE 0xf700 452#define TX4927_ACLC_ACCTLEN 0xf700 453#define TX4927_ACLC_ACCTLDIS 0xf704 454#define TX4927_ACLC_ACREGACC 0xf708 455#define TX4927_ACLC_ACINTSTS 0xf710 456#define TX4927_ACLC_ACINTMSTS 0xf714 457#define TX4927_ACLC_ACINTEN 0xf718 458#define TX4927_ACLC_ACINTDIS 0xf71c 459#define TX4927_ACLC_ACSEMAPH 0xf720 460#define TX4927_ACLC_ACGPIDAT 0xf740 461#define TX4927_ACLC_ACGPODAT 0xf744 462#define TX4927_ACLC_ACSLTEN 0xf748 463#define TX4927_ACLC_ACSLTDIS 0xf74c 464#define TX4927_ACLC_ACFIFOSTS 0xf750 465#define TX4927_ACLC_ACDMASTS 0xf780 466#define TX4927_ACLC_ACDMASEL 0xf784 467#define TX4927_ACLC_ACAUDODAT 0xf7a0 468#define TX4927_ACLC_ACSURRDAT 0xf7a4 469#define TX4927_ACLC_ACCENTDAT 0xf7a8 470#define TX4927_ACLC_ACLFEDAT 0xf7ac 471#define TX4927_ACLC_ACAUDIDAT 0xf7b0 472#define TX4927_ACLC_ACMODODAT 0xf7b8 473#define TX4927_ACLC_ACMODIDAT 0xf7bc 474#define TX4927_ACLC_ACREVID 0xf7fc 475#define TX4927_ACLC_LIMIT 0xf7ff 476 477 478#define TX4927_REG(x) ((TX4927_BASE)+(x)) 479 480#define TX4927_RD08( reg ) (*(vu08*)(reg)) 481#define TX4927_WR08( reg, val ) ((*(vu08*)(reg))=(val)) 482 483#define TX4927_RD16( reg ) (*(vu16*)(reg)) 484#define TX4927_WR16( reg, val ) ((*(vu16*)(reg))=(val)) 485 486#define TX4927_RD32( reg ) (*(vu32*)(reg)) 487#define TX4927_WR32( reg, val ) ((*(vu32*)(reg))=(val)) 488 489#define TX4927_RD64( reg ) (*(vu64*)(reg)) 490#define TX4927_WR64( reg, val ) ((*(vu64*)(reg))=(val)) 491 492#define TX4927_RD( reg ) TX4927_RD32( reg ) 493#define TX4927_WR( reg, val ) TX4927_WR32( reg, val ) 494 495 496 497 498 499#define MI8259_IRQ_ISA_RAW_BEG 0 /* optional backplane i8259 */ 500#define MI8259_IRQ_ISA_RAW_END 15 501#define TX4927_IRQ_CP0_RAW_BEG 0 /* tx4927 cpu built-in cp0 */ 502#define TX4927_IRQ_CP0_RAW_END 7 503#define TX4927_IRQ_PIC_RAW_BEG 0 /* tx4927 cpu build-in pic */ 504#define TX4927_IRQ_PIC_RAW_END 31 505 506 507#define MI8259_IRQ_ISA_BEG MI8259_IRQ_ISA_RAW_BEG /* 0 */ 508#define MI8259_IRQ_ISA_END MI8259_IRQ_ISA_RAW_END /* 15 */ 509 510#define TX4927_IRQ_CP0_BEG ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_BEG) /* 16 */ 511#define TX4927_IRQ_CP0_END ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_END) /* 23 */ 512 513#define TX4927_IRQ_PIC_BEG ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_BEG) /* 24 */ 514#define TX4927_IRQ_PIC_END ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_END) /* 55 */ 515 516 517#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) 518#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1) 519#define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2) 520#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7) 521 522#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3) 523 524#endif /* __ASM_TX4927_TX4927_H */