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1/* 2 * include/asm-x86_64/cache.h 3 */ 4#ifndef __ARCH_X8664_CACHE_H 5#define __ARCH_X8664_CACHE_H 6 7 8/* L1 cache line size */ 9#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT) 10#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 11 12#ifdef CONFIG_X86_VSMP 13 14/* vSMP Internode cacheline shift */ 15#define INTERNODE_CACHE_SHIFT (12) 16#ifdef CONFIG_SMP 17#define __cacheline_aligned_in_smp \ 18 __attribute__((__aligned__(1 << (INTERNODE_CACHE_SHIFT)))) \ 19 __attribute__((__section__(".data.page_aligned"))) 20#endif 21 22#endif 23 24#define __read_mostly __attribute__((__section__(".data.read_mostly"))) 25 26#endif