tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994-1996 Linus Torvalds & authors
7 *
8 * Copied from i386; many of the especially older MIPS or ISA-based platforms
9 * are basically identical. Using this file probably implies i8259 PIC
10 * support in a system but the very least interrupt numbers 0 - 15 need to
11 * be put aside for legacy devices.
12 */
13#ifndef __ASM_MACH_GENERIC_IDE_H
14#define __ASM_MACH_GENERIC_IDE_H
15
16#ifdef __KERNEL__
17
18#include <linux/pci.h>
19#include <linux/stddef.h>
20#include <asm/processor.h>
21
22#ifndef MAX_HWIFS
23# ifdef CONFIG_BLK_DEV_IDEPCI
24#define MAX_HWIFS 10
25# else
26#define MAX_HWIFS 6
27# endif
28#endif
29
30#define IDE_ARCH_OBSOLETE_DEFAULTS
31
32static __inline__ int ide_probe_legacy(void)
33{
34#ifdef CONFIG_PCI
35 struct pci_dev *dev;
36 if ((dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL)) != NULL ||
37 (dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL)) != NULL) {
38 pci_dev_put(dev);
39
40 return 1;
41 }
42 return 0;
43#elif defined(CONFIG_EISA) || defined(CONFIG_ISA)
44 return 1;
45#else
46 return 0;
47#endif
48}
49
50static __inline__ int ide_default_irq(unsigned long base)
51{
52 if (ide_probe_legacy())
53 switch (base) {
54 case 0x1f0:
55 return 14;
56 case 0x170:
57 return 15;
58 case 0x1e8:
59 return 11;
60 case 0x168:
61 return 10;
62 case 0x1e0:
63 return 8;
64 case 0x160:
65 return 12;
66 default:
67 return 0;
68 }
69 else
70 return 0;
71}
72
73static __inline__ unsigned long ide_default_io_base(int index)
74{
75 if (ide_probe_legacy())
76 switch (index) {
77 case 0:
78 return 0x1f0;
79 case 1:
80 return 0x170;
81 case 2:
82 return 0x1e8;
83 case 3:
84 return 0x168;
85 case 4:
86 return 0x1e0;
87 case 5:
88 return 0x160;
89 default:
90 return 0;
91 }
92 else
93 return 0;
94}
95
96#define IDE_ARCH_OBSOLETE_INIT
97#define ide_default_io_ctl(base) ((base) + 0x206) /* obsolete */
98
99#ifdef CONFIG_BLK_DEV_IDEPCI
100#define ide_init_default_irq(base) (0)
101#else
102#define ide_init_default_irq(base) ide_default_irq(base)
103#endif
104
105/* MIPS port and memory-mapped I/O string operations. */
106static inline void __ide_flush_prologue(void)
107{
108#ifdef CONFIG_SMP
109 if (cpu_has_dc_aliases)
110 preempt_disable();
111#endif
112}
113
114static inline void __ide_flush_epilogue(void)
115{
116#ifdef CONFIG_SMP
117 if (cpu_has_dc_aliases)
118 preempt_enable();
119#endif
120}
121
122static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
123{
124 if (cpu_has_dc_aliases) {
125 unsigned long end = addr + size;
126
127 while (addr < end) {
128 local_flush_data_cache_page((void *)addr);
129 addr += PAGE_SIZE;
130 }
131 }
132}
133
134/*
135 * insw() and gang might be called with interrupts disabled, so we can't
136 * send IPIs for flushing due to the potencial of deadlocks, see the comment
137 * above smp_call_function() in arch/mips/kernel/smp.c. We work around the
138 * problem by disabling preemption so we know we actually perform the flush
139 * on the processor that actually has the lines to be flushed which hopefully
140 * is even better for performance anyway.
141 */
142static inline void __ide_insw(unsigned long port, void *addr,
143 unsigned int count)
144{
145 __ide_flush_prologue();
146 insw(port, addr, count);
147 __ide_flush_dcache_range((unsigned long)addr, count * 2);
148 __ide_flush_epilogue();
149}
150
151static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
152{
153 __ide_flush_prologue();
154 insl(port, addr, count);
155 __ide_flush_dcache_range((unsigned long)addr, count * 4);
156 __ide_flush_epilogue();
157}
158
159static inline void __ide_outsw(unsigned long port, const void *addr,
160 unsigned long count)
161{
162 __ide_flush_prologue();
163 outsw(port, addr, count);
164 __ide_flush_dcache_range((unsigned long)addr, count * 2);
165 __ide_flush_epilogue();
166}
167
168static inline void __ide_outsl(unsigned long port, const void *addr,
169 unsigned long count)
170{
171 __ide_flush_prologue();
172 outsl(port, addr, count);
173 __ide_flush_dcache_range((unsigned long)addr, count * 4);
174 __ide_flush_epilogue();
175}
176
177static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count)
178{
179 __ide_flush_prologue();
180 readsw(port, addr, count);
181 __ide_flush_dcache_range((unsigned long)addr, count * 2);
182 __ide_flush_epilogue();
183}
184
185static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count)
186{
187 __ide_flush_prologue();
188 readsl(port, addr, count);
189 __ide_flush_dcache_range((unsigned long)addr, count * 4);
190 __ide_flush_epilogue();
191}
192
193static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count)
194{
195 __ide_flush_prologue();
196 writesw(port, addr, count);
197 __ide_flush_dcache_range((unsigned long)addr, count * 2);
198 __ide_flush_epilogue();
199}
200
201static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count)
202{
203 __ide_flush_prologue();
204 writesl(port, addr, count);
205 __ide_flush_dcache_range((unsigned long)addr, count * 4);
206 __ide_flush_epilogue();
207}
208
209/* ide_insw calls insw, not __ide_insw. Why? */
210#undef insw
211#undef insl
212#undef outsw
213#undef outsl
214#define insw(port, addr, count) __ide_insw(port, addr, count)
215#define insl(port, addr, count) __ide_insl(port, addr, count)
216#define outsw(port, addr, count) __ide_outsw(port, addr, count)
217#define outsl(port, addr, count) __ide_outsl(port, addr, count)
218
219#endif /* __KERNEL__ */
220
221#endif /* __ASM_MACH_GENERIC_IDE_H */