tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * include/asm-v850/ma.h -- V850E/MA series of cpu chips
3 *
4 * Copyright (C) 2001,02,03 NEC Electronics Corporation
5 * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
6 *
7 * This file is subject to the terms and conditions of the GNU General
8 * Public License. See the file COPYING in the main directory of this
9 * archive for more details.
10 *
11 * Written by Miles Bader <miles@gnu.org>
12 */
13
14#ifndef __V850_MA_H__
15#define __V850_MA_H__
16
17/* The MA series uses the V850E cpu core. */
18#include <asm/v850e.h>
19
20
21/* For <asm/entry.h> */
22/* We use on-chip RAM, for a few miscellaneous variables that must be
23 accessible using a load instruction relative to R0. The amount
24 varies between chip models, but there's always at least 4K, and it
25 should always start at FFFFC000. */
26#define R0_RAM_ADDR 0xFFFFC000
27
28
29/* MA series UART details. */
30#define V850E_UART_BASE_FREQ CPU_CLOCK_FREQ
31
32/* This is a function that gets called before configuring the UART. */
33#define V850E_UART_PRE_CONFIGURE ma_uart_pre_configure
34#ifndef __ASSEMBLY__
35extern void ma_uart_pre_configure (unsigned chan,
36 unsigned cflags, unsigned baud);
37#endif
38
39
40/* MA series timer C details. */
41#define V850E_TIMER_C_BASE_ADDR 0xFFFFF600
42
43
44/* MA series timer D details. */
45#define V850E_TIMER_D_BASE_ADDR 0xFFFFF540
46#define V850E_TIMER_D_TMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x0)
47#define V850E_TIMER_D_CMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x2)
48#define V850E_TIMER_D_TMCD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x4)
49
50#define V850E_TIMER_D_BASE_FREQ CPU_CLOCK_FREQ
51
52
53/* Port 0 */
54/* Direct I/O. Bits 0-7 are pins P00-P07. */
55#define MA_PORT0_IO_ADDR 0xFFFFF400
56#define MA_PORT0_IO (*(volatile u8 *)MA_PORT0_IO_ADDR)
57/* Port mode (for direct I/O, 0 = output, 1 = input). */
58#define MA_PORT0_PM_ADDR 0xFFFFF420
59#define MA_PORT0_PM (*(volatile u8 *)MA_PORT0_PM_ADDR)
60/* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode). */
61#define MA_PORT0_PMC_ADDR 0xFFFFF440
62#define MA_PORT0_PMC (*(volatile u8 *)MA_PORT0_PMC_ADDR)
63/* Port function control (for P04-P07, 0 = IRQ, 1 = DMARQ). */
64#define MA_PORT0_PFC_ADDR 0xFFFFF460
65#define MA_PORT0_PFC (*(volatile u8 *)MA_PORT0_PFC_ADDR)
66
67/* Port 1 */
68/* Direct I/O. Bits 0-3 are pins P10-P13. */
69#define MA_PORT1_IO_ADDR 0xFFFFF402
70#define MA_PORT1_IO (*(volatile u8 *)MA_PORT1_IO_ADDR)
71/* Port mode (for direct I/O, 0 = output, 1 = input). */
72#define MA_PORT1_PM_ADDR 0xFFFFF420
73#define MA_PORT1_PM (*(volatile u8 *)MA_PORT1_PM_ADDR)
74/* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode). */
75#define MA_PORT1_PMC_ADDR 0xFFFFF442
76#define MA_PORT1_PMC (*(volatile u8 *)MA_PORT1_PMC_ADDR)
77
78/* Port 4 */
79/* Direct I/O. Bits 0-5 are pins P40-P45. */
80#define MA_PORT4_IO_ADDR 0xFFFFF408
81#define MA_PORT4_IO (*(volatile u8 *)MA_PORT4_IO_ADDR)
82/* Port mode (for direct I/O, 0 = output, 1 = input). */
83#define MA_PORT4_PM_ADDR 0xFFFFF428
84#define MA_PORT4_PM (*(volatile u8 *)MA_PORT4_PM_ADDR)
85/* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode). */
86#define MA_PORT4_PMC_ADDR 0xFFFFF448
87#define MA_PORT4_PMC (*(volatile u8 *)MA_PORT4_PMC_ADDR)
88/* Port function control (for serial interfaces, 0 = CSI, 1 = UART). */
89#define MA_PORT4_PFC_ADDR 0xFFFFF468
90#define MA_PORT4_PFC (*(volatile u8 *)MA_PORT4_PFC_ADDR)
91
92
93#ifndef __ASSEMBLY__
94
95/* Initialize MA chip interrupts. */
96extern void ma_init_irqs (void);
97
98#endif /* !__ASSEMBLY__ */
99
100
101#endif /* __V850_MA_H__ */