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1/*
2 * include/asm-xtensa/byteorder.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_BYTEORDER_H
12#define _XTENSA_BYTEORDER_H
13
14#include <asm/types.h>
15
16static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
17{
18 __u32 res;
19 /* instruction sequence from Xtensa ISA release 2/2000 */
20 __asm__("ssai 8 \n\t"
21 "srli %0, %1, 16 \n\t"
22 "src %0, %0, %1 \n\t"
23 "src %0, %0, %0 \n\t"
24 "src %0, %1, %0 \n"
25 : "=&a" (res)
26 : "a" (x)
27 );
28 return res;
29}
30
31static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
32{
33 /* Given that 'short' values are signed (i.e., can be negative),
34 * we cannot assume that the upper 16-bits of the register are
35 * zero. We are careful to mask values after shifting.
36 */
37
38 /* There exists an anomaly between xt-gcc and xt-xcc. xt-gcc
39 * inserts an extui instruction after putting this function inline
40 * to ensure that it uses only the least-significant 16 bits of
41 * the result. xt-xcc doesn't use an extui, but assumes the
42 * __asm__ macro follows convention that the upper 16 bits of an
43 * 'unsigned short' result are still zero. This macro doesn't
44 * follow convention; indeed, it leaves garbage in the upport 16
45 * bits of the register.
46
47 * Declaring the temporary variables 'res' and 'tmp' to be 32-bit
48 * types while the return type of the function is a 16-bit type
49 * forces both compilers to insert exactly one extui instruction
50 * (or equivalent) to mask off the upper 16 bits. */
51
52 __u32 res;
53 __u32 tmp;
54
55 __asm__("extui %1, %2, 8, 8\n\t"
56 "slli %0, %2, 8 \n\t"
57 "or %0, %0, %1 \n"
58 : "=&a" (res), "=&a" (tmp)
59 : "a" (x)
60 );
61
62 return res;
63}
64
65#define __arch__swab32(x) ___arch__swab32(x)
66#define __arch__swab16(x) ___arch__swab16(x)
67
68#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
69# define __BYTEORDER_HAS_U64__
70# define __SWAB_64_THRU_32__
71#endif
72
73#ifdef __XTENSA_EL__
74# include <linux/byteorder/little_endian.h>
75#elif defined(__XTENSA_EB__)
76# include <linux/byteorder/big_endian.h>
77#else
78# error processor byte order undefined!
79#endif
80
81#endif /* __ASM_XTENSA_BYTEORDER_H */