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1/*
2 * include/asm-sh/cpu-sh3/cacheflush.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_CACHEFLUSH_H
11#define __ASM_CPU_SH3_CACHEFLUSH_H
12
13/*
14 * Cache flushing:
15 *
16 * - flush_cache_all() flushes entire cache
17 * - flush_cache_mm(mm) flushes the specified mm context's cache lines
18 * - flush_cache_dup mm(mm) handles cache flushing when forking
19 * - flush_cache_page(mm, vmaddr, pfn) flushes a single page
20 * - flush_cache_range(vma, start, end) flushes a range of pages
21 *
22 * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
23 * - flush_icache_range(start, end) flushes(invalidates) a range for icache
24 * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
25 *
26 * Caches are indexed (effectively) by physical address on SH-3, so
27 * we don't need them.
28 */
29
30#if defined(CONFIG_SH7705_CACHE_32KB)
31
32/* SH7705 is an SH3 processor with 32KB cache. This has alias issues like the
33 * SH4. Unlike the SH4 this is a unified cache so we need to do some work
34 * in mmap when 'exec'ing a new binary
35 */
36 /* 32KB cache, 4kb PAGE sizes need to check bit 12 */
37#define CACHE_ALIAS 0x00001000
38
39#define PG_mapped PG_arch_1
40
41void flush_cache_all(void);
42void flush_cache_mm(struct mm_struct *mm);
43#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
44void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
45 unsigned long end);
46void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
47void flush_dcache_page(struct page *pg);
48void flush_icache_range(unsigned long start, unsigned long end);
49void flush_icache_page(struct vm_area_struct *vma, struct page *page);
50#else
51#define flush_cache_all() do { } while (0)
52#define flush_cache_mm(mm) do { } while (0)
53#define flush_cache_dup_mm(mm) do { } while (0)
54#define flush_cache_range(vma, start, end) do { } while (0)
55#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
56#define flush_dcache_page(page) do { } while (0)
57#define flush_icache_range(start, end) do { } while (0)
58#define flush_icache_page(vma,pg) do { } while (0)
59#endif
60
61#define flush_dcache_mmap_lock(mapping) do { } while (0)
62#define flush_dcache_mmap_unlock(mapping) do { } while (0)
63
64/* SH3 has unified cache so no special action needed here */
65#define flush_cache_sigtramp(vaddr) do { } while (0)
66#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
67
68#define p3_cache_init() do { } while (0)
69
70#endif /* __ASM_CPU_SH3_CACHEFLUSH_H */