include/asm-powerpc/cputable.h at v2.6.21-rc7

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kernel / include / asm-powerpc / cputable.h
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  1#ifndef __ASM_POWERPC_CPUTABLE_H
  2#define __ASM_POWERPC_CPUTABLE_H
  3
  4#include <asm/asm-compat.h>
  5
  6#define PPC_FEATURE_32			0x80000000
  7#define PPC_FEATURE_64			0x40000000
  8#define PPC_FEATURE_601_INSTR		0x20000000
  9#define PPC_FEATURE_HAS_ALTIVEC		0x10000000
 10#define PPC_FEATURE_HAS_FPU		0x08000000
 11#define PPC_FEATURE_HAS_MMU		0x04000000
 12#define PPC_FEATURE_HAS_4xxMAC		0x02000000
 13#define PPC_FEATURE_UNIFIED_CACHE	0x01000000
 14#define PPC_FEATURE_HAS_SPE		0x00800000
 15#define PPC_FEATURE_HAS_EFP_SINGLE	0x00400000
 16#define PPC_FEATURE_HAS_EFP_DOUBLE	0x00200000
 17#define PPC_FEATURE_NO_TB		0x00100000
 18#define PPC_FEATURE_POWER4		0x00080000
 19#define PPC_FEATURE_POWER5		0x00040000
 20#define PPC_FEATURE_POWER5_PLUS		0x00020000
 21#define PPC_FEATURE_CELL		0x00010000
 22#define PPC_FEATURE_BOOKE		0x00008000
 23#define PPC_FEATURE_SMT			0x00004000
 24#define PPC_FEATURE_ICACHE_SNOOP	0x00002000
 25#define PPC_FEATURE_ARCH_2_05		0x00001000
 26#define PPC_FEATURE_PA6T		0x00000800
 27#define PPC_FEATURE_HAS_DFP		0x00000400
 28#define PPC_FEATURE_POWER6_EXT		0x00000200
 29
 30#define PPC_FEATURE_TRUE_LE		0x00000002
 31#define PPC_FEATURE_PPC_LE		0x00000001
 32
 33#ifdef __KERNEL__
 34#ifndef __ASSEMBLY__
 35
 36/* This structure can grow, it's real size is used by head.S code
 37 * via the mkdefs mechanism.
 38 */
 39struct cpu_spec;
 40
 41typedef	void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
 42typedef	void (*cpu_restore_t)(void);
 43
 44enum powerpc_oprofile_type {
 45	PPC_OPROFILE_INVALID = 0,
 46	PPC_OPROFILE_RS64 = 1,
 47	PPC_OPROFILE_POWER4 = 2,
 48	PPC_OPROFILE_G4 = 3,
 49	PPC_OPROFILE_BOOKE = 4,
 50	PPC_OPROFILE_CELL = 5,
 51};
 52
 53enum powerpc_pmc_type {
 54	PPC_PMC_DEFAULT = 0,
 55	PPC_PMC_IBM = 1,
 56	PPC_PMC_PA6T = 2,
 57};
 58
 59struct cpu_spec {
 60	/* CPU is matched via (PVR & pvr_mask) == pvr_value */
 61	unsigned int	pvr_mask;
 62	unsigned int	pvr_value;
 63
 64	char		*cpu_name;
 65	unsigned long	cpu_features;		/* Kernel features */
 66	unsigned int	cpu_user_features;	/* Userland features */
 67
 68	/* cache line sizes */
 69	unsigned int	icache_bsize;
 70	unsigned int	dcache_bsize;
 71
 72	/* number of performance monitor counters */
 73	unsigned int	num_pmcs;
 74	enum powerpc_pmc_type pmc_type;
 75
 76	/* this is called to initialize various CPU bits like L1 cache,
 77	 * BHT, SPD, etc... from head.S before branching to identify_machine
 78	 */
 79	cpu_setup_t	cpu_setup;
 80	/* Used to restore cpu setup on secondary processors and at resume */
 81	cpu_restore_t	cpu_restore;
 82
 83	/* Used by oprofile userspace to select the right counters */
 84	char		*oprofile_cpu_type;
 85
 86	/* Processor specific oprofile operations */
 87	enum powerpc_oprofile_type oprofile_type;
 88
 89	/* Bit locations inside the mmcra change */
 90	unsigned long	oprofile_mmcra_sihv;
 91	unsigned long	oprofile_mmcra_sipr;
 92
 93	/* Bits to clear during an oprofile exception */
 94	unsigned long	oprofile_mmcra_clear;
 95
 96	/* Name of processor class, for the ELF AT_PLATFORM entry */
 97	char		*platform;
 98};
 99
100extern struct cpu_spec		*cur_cpu_spec;
101
102extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
103
104extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
105extern void do_feature_fixups(unsigned long value, void *fixup_start,
106			      void *fixup_end);
107
108#endif /* __ASSEMBLY__ */
109
110/* CPU kernel features */
111
112/* Retain the 32b definitions all use bottom half of word */
113#define CPU_FTR_SPLIT_ID_CACHE		ASM_CONST(0x0000000000000001)
114#define CPU_FTR_L2CR			ASM_CONST(0x0000000000000002)
115#define CPU_FTR_SPEC7450		ASM_CONST(0x0000000000000004)
116#define CPU_FTR_ALTIVEC			ASM_CONST(0x0000000000000008)
117#define CPU_FTR_TAU			ASM_CONST(0x0000000000000010)
118#define CPU_FTR_CAN_DOZE		ASM_CONST(0x0000000000000020)
119#define CPU_FTR_USE_TB			ASM_CONST(0x0000000000000040)
120#define CPU_FTR_604_PERF_MON		ASM_CONST(0x0000000000000080)
121#define CPU_FTR_601			ASM_CONST(0x0000000000000100)
122#define CPU_FTR_HPTE_TABLE		ASM_CONST(0x0000000000000200)
123#define CPU_FTR_CAN_NAP			ASM_CONST(0x0000000000000400)
124#define CPU_FTR_L3CR			ASM_CONST(0x0000000000000800)
125#define CPU_FTR_L3_DISABLE_NAP		ASM_CONST(0x0000000000001000)
126#define CPU_FTR_NAP_DISABLE_L2_PR	ASM_CONST(0x0000000000002000)
127#define CPU_FTR_DUAL_PLL_750FX		ASM_CONST(0x0000000000004000)
128#define CPU_FTR_NO_DPM			ASM_CONST(0x0000000000008000)
129#define CPU_FTR_HAS_HIGH_BATS		ASM_CONST(0x0000000000010000)
130#define CPU_FTR_NEED_COHERENT		ASM_CONST(0x0000000000020000)
131#define CPU_FTR_NO_BTIC			ASM_CONST(0x0000000000040000)
132#define CPU_FTR_BIG_PHYS		ASM_CONST(0x0000000000080000)
133#define CPU_FTR_NODSISRALIGN		ASM_CONST(0x0000000000100000)
134#define CPU_FTR_PPC_LE			ASM_CONST(0x0000000000200000)
135#define CPU_FTR_REAL_LE			ASM_CONST(0x0000000000400000)
136#define CPU_FTR_FPU_UNAVAILABLE		ASM_CONST(0x0000000000800000)
137
138/*
139 * Add the 64-bit processor unique features in the top half of the word;
140 * on 32-bit, make the names available but defined to be 0.
141 */
142#ifdef __powerpc64__
143#define LONG_ASM_CONST(x)		ASM_CONST(x)
144#else
145#define LONG_ASM_CONST(x)		0
146#endif
147
148#define CPU_FTR_SLB			LONG_ASM_CONST(0x0000000100000000)
149#define CPU_FTR_16M_PAGE		LONG_ASM_CONST(0x0000000200000000)
150#define CPU_FTR_TLBIEL			LONG_ASM_CONST(0x0000000400000000)
151#define CPU_FTR_NOEXECUTE		LONG_ASM_CONST(0x0000000800000000)
152#define CPU_FTR_IABR			LONG_ASM_CONST(0x0000002000000000)
153#define CPU_FTR_MMCRA			LONG_ASM_CONST(0x0000004000000000)
154#define CPU_FTR_CTRL			LONG_ASM_CONST(0x0000008000000000)
155#define CPU_FTR_SMT			LONG_ASM_CONST(0x0000010000000000)
156#define CPU_FTR_COHERENT_ICACHE		LONG_ASM_CONST(0x0000020000000000)
157#define CPU_FTR_LOCKLESS_TLBIE		LONG_ASM_CONST(0x0000040000000000)
158#define CPU_FTR_CI_LARGE_PAGE		LONG_ASM_CONST(0x0000100000000000)
159#define CPU_FTR_PAUSE_ZERO		LONG_ASM_CONST(0x0000200000000000)
160#define CPU_FTR_PURR			LONG_ASM_CONST(0x0000400000000000)
161#define CPU_FTR_CELL_TB_BUG		LONG_ASM_CONST(0x0000800000000000)
162#define CPU_FTR_SPURR			LONG_ASM_CONST(0x0001000000000000)
163#define CPU_FTR_DSCR			LONG_ASM_CONST(0x0002000000000000)
164
165#ifndef __ASSEMBLY__
166
167#define CPU_FTR_PPCAS_ARCH_V2	(CPU_FTR_SLB | \
168				 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
169				 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
170
171/* We only set the altivec features if the kernel was compiled with altivec
172 * support
173 */
174#ifdef CONFIG_ALTIVEC
175#define CPU_FTR_ALTIVEC_COMP	CPU_FTR_ALTIVEC
176#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
177#else
178#define CPU_FTR_ALTIVEC_COMP	0
179#define PPC_FEATURE_HAS_ALTIVEC_COMP    0
180#endif
181
182/* We need to mark all pages as being coherent if we're SMP or we
183 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
184 * it for PCI "streaming/prefetch" to work properly.
185 */
186#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
187	|| defined(CONFIG_PPC_83xx)
188#define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
189#else
190#define CPU_FTR_COMMON                  0
191#endif
192
193/* The powersave features NAP & DOZE seems to confuse BDI when
194   debugging. So if a BDI is used, disable theses
195 */
196#ifndef CONFIG_BDI_SWITCH
197#define CPU_FTR_MAYBE_CAN_DOZE	CPU_FTR_CAN_DOZE
198#define CPU_FTR_MAYBE_CAN_NAP	CPU_FTR_CAN_NAP
199#else
200#define CPU_FTR_MAYBE_CAN_DOZE	0
201#define CPU_FTR_MAYBE_CAN_NAP	0
202#endif
203
204#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
205		     !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
206		     !defined(CONFIG_BOOKE))
207
208#define CPU_FTRS_PPC601	(CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
209#define CPU_FTRS_603	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
210	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
211	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
212#define CPU_FTRS_604	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
213	    CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
214	    CPU_FTR_PPC_LE)
215#define CPU_FTRS_740_NOTAU	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
216	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
217	    CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
218#define CPU_FTRS_740	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
219	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
220	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
221	    CPU_FTR_PPC_LE)
222#define CPU_FTRS_750	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
223	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
224	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
225	    CPU_FTR_PPC_LE)
226#define CPU_FTRS_750FX1	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
227	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
228	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
229	    CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
230#define CPU_FTRS_750FX2	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
231	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
232	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
233	    CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
234#define CPU_FTRS_750FX	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
235	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
236	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
237	    CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
238#define CPU_FTRS_750GX	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
239	    CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \
240	    CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
241	    CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
242#define CPU_FTRS_7400_NOTAU	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
243	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
244	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
245	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
246#define CPU_FTRS_7400	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
247	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
248	    CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
249	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
250#define CPU_FTRS_7450_20	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
251	    CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
252	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
253	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
254#define CPU_FTRS_7450_21	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
255	    CPU_FTR_USE_TB | \
256	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
257	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
258	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
259	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
260#define CPU_FTRS_7450_23	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
261	    CPU_FTR_USE_TB | \
262	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
263	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
264	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
265#define CPU_FTRS_7455_1	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
266	    CPU_FTR_USE_TB | \
267	    CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
268	    CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
269	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
270#define CPU_FTRS_7455_20	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
271	    CPU_FTR_USE_TB | \
272	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
273	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
274	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
275	    CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
276#define CPU_FTRS_7455	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
277	    CPU_FTR_USE_TB | \
278	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
279	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
280	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
281	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
282#define CPU_FTRS_7447_10	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
283	    CPU_FTR_USE_TB | \
284	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
285	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
286	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
287	    CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
288#define CPU_FTRS_7447	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
289	    CPU_FTR_USE_TB | \
290	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
291	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
292	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
293	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
294#define CPU_FTRS_7447A	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
295	    CPU_FTR_USE_TB | \
296	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
297	    CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
298	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
299	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
300#define CPU_FTRS_82XX	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
301	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
302#define CPU_FTRS_G2_LE	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
303	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
304#define CPU_FTRS_E300	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
305	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
306	    CPU_FTR_COMMON)
307#define CPU_FTRS_E300C2	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
308	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
309	    CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
310#define CPU_FTRS_CLASSIC32	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
311	    CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
312#define CPU_FTRS_8XX	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
313#define CPU_FTRS_40X	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
314	    CPU_FTR_NODSISRALIGN)
315#define CPU_FTRS_44X	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
316	    CPU_FTR_NODSISRALIGN)
317#define CPU_FTRS_E200	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
318#define CPU_FTRS_E500	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
319	    CPU_FTR_NODSISRALIGN)
320#define CPU_FTRS_E500_2	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
321	    CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
322#define CPU_FTRS_GENERIC_32	(CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
323
324/* 64-bit CPUs */
325#define CPU_FTRS_POWER3	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
326	    CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
327#define CPU_FTRS_RS64	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
328	    CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
329	    CPU_FTR_MMCRA | CPU_FTR_CTRL)
330#define CPU_FTRS_POWER4	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
331	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
332	    CPU_FTR_MMCRA)
333#define CPU_FTRS_PPC970	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
334	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
335	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
336#define CPU_FTRS_POWER5	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
337	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
338	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
339	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
340	    CPU_FTR_PURR)
341#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
342	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
343	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
344	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
345	    CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
346	    CPU_FTR_DSCR)
347#define CPU_FTRS_CELL	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
348	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
349	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
350	    CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
351#define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
352	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
353	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
354	    CPU_FTR_PURR | CPU_FTR_REAL_LE)
355#define CPU_FTRS_COMPATIBLE	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
356	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
357
358#ifdef __powerpc64__
359#define CPU_FTRS_POSSIBLE	\
360	    (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |	\
361	    CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |	\
362	    CPU_FTRS_CELL | CPU_FTRS_PA6T)
363#else
364enum {
365	CPU_FTRS_POSSIBLE =
366#if CLASSIC_PPC
367	    CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
368	    CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
369	    CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
370	    CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
371	    CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
372	    CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
373	    CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
374	    CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
375	    CPU_FTRS_CLASSIC32 |
376#else
377	    CPU_FTRS_GENERIC_32 |
378#endif
379#ifdef CONFIG_8xx
380	    CPU_FTRS_8XX |
381#endif
382#ifdef CONFIG_40x
383	    CPU_FTRS_40X |
384#endif
385#ifdef CONFIG_44x
386	    CPU_FTRS_44X |
387#endif
388#ifdef CONFIG_E200
389	    CPU_FTRS_E200 |
390#endif
391#ifdef CONFIG_E500
392	    CPU_FTRS_E500 | CPU_FTRS_E500_2 |
393#endif
394	    0,
395};
396#endif /* __powerpc64__ */
397
398#ifdef __powerpc64__
399#define CPU_FTRS_ALWAYS		\
400	    (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &	\
401	    CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 &	\
402	    CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
403#else
404enum {
405	CPU_FTRS_ALWAYS =
406#if CLASSIC_PPC
407	    CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
408	    CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
409	    CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
410	    CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
411	    CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
412	    CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
413	    CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
414	    CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
415	    CPU_FTRS_CLASSIC32 &
416#else
417	    CPU_FTRS_GENERIC_32 &
418#endif
419#ifdef CONFIG_8xx
420	    CPU_FTRS_8XX &
421#endif
422#ifdef CONFIG_40x
423	    CPU_FTRS_40X &
424#endif
425#ifdef CONFIG_44x
426	    CPU_FTRS_44X &
427#endif
428#ifdef CONFIG_E200
429	    CPU_FTRS_E200 &
430#endif
431#ifdef CONFIG_E500
432	    CPU_FTRS_E500 & CPU_FTRS_E500_2 &
433#endif
434	    CPU_FTRS_POSSIBLE,
435};
436#endif /* __powerpc64__ */
437
438static inline int cpu_has_feature(unsigned long feature)
439{
440	return (CPU_FTRS_ALWAYS & feature) ||
441	       (CPU_FTRS_POSSIBLE
442		& cur_cpu_spec->cpu_features
443		& feature);
444}
445
446#endif /* !__ASSEMBLY__ */
447
448#ifdef __ASSEMBLY__
449
450#define BEGIN_FTR_SECTION_NESTED(label)	label:
451#define BEGIN_FTR_SECTION		BEGIN_FTR_SECTION_NESTED(97)
452#define END_FTR_SECTION_NESTED(msk, val, label) \
453	MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
454#define END_FTR_SECTION(msk, val)		\
455	END_FTR_SECTION_NESTED(msk, val, 97)
456
457#define END_FTR_SECTION_IFSET(msk)	END_FTR_SECTION((msk), (msk))
458#define END_FTR_SECTION_IFCLR(msk)	END_FTR_SECTION((msk), 0)
459#endif /* __ASSEMBLY__ */
460
461#endif /* __KERNEL__ */
462#endif /* __ASM_POWERPC_CPUTABLE_H */