tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * SPU core / file system interface and HW structures
3 *
4 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
5 *
6 * Author: Arnd Bergmann <arndb@de.ibm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _SPU_H
24#define _SPU_H
25#ifdef __KERNEL__
26
27#include <linux/workqueue.h>
28#include <linux/sysdev.h>
29
30#define LS_SIZE (256 * 1024)
31#define LS_ADDR_MASK (LS_SIZE - 1)
32
33#define MFC_PUT_CMD 0x20
34#define MFC_PUTS_CMD 0x28
35#define MFC_PUTR_CMD 0x30
36#define MFC_PUTF_CMD 0x22
37#define MFC_PUTB_CMD 0x21
38#define MFC_PUTFS_CMD 0x2A
39#define MFC_PUTBS_CMD 0x29
40#define MFC_PUTRF_CMD 0x32
41#define MFC_PUTRB_CMD 0x31
42#define MFC_PUTL_CMD 0x24
43#define MFC_PUTRL_CMD 0x34
44#define MFC_PUTLF_CMD 0x26
45#define MFC_PUTLB_CMD 0x25
46#define MFC_PUTRLF_CMD 0x36
47#define MFC_PUTRLB_CMD 0x35
48
49#define MFC_GET_CMD 0x40
50#define MFC_GETS_CMD 0x48
51#define MFC_GETF_CMD 0x42
52#define MFC_GETB_CMD 0x41
53#define MFC_GETFS_CMD 0x4A
54#define MFC_GETBS_CMD 0x49
55#define MFC_GETL_CMD 0x44
56#define MFC_GETLF_CMD 0x46
57#define MFC_GETLB_CMD 0x45
58
59#define MFC_SDCRT_CMD 0x80
60#define MFC_SDCRTST_CMD 0x81
61#define MFC_SDCRZ_CMD 0x89
62#define MFC_SDCRS_CMD 0x8D
63#define MFC_SDCRF_CMD 0x8F
64
65#define MFC_GETLLAR_CMD 0xD0
66#define MFC_PUTLLC_CMD 0xB4
67#define MFC_PUTLLUC_CMD 0xB0
68#define MFC_PUTQLLUC_CMD 0xB8
69#define MFC_SNDSIG_CMD 0xA0
70#define MFC_SNDSIGB_CMD 0xA1
71#define MFC_SNDSIGF_CMD 0xA2
72#define MFC_BARRIER_CMD 0xC0
73#define MFC_EIEIO_CMD 0xC8
74#define MFC_SYNC_CMD 0xCC
75
76#define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
77#define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
78#define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
79#define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
80#define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
81#define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
82#define MFC_MIN_DMA_LIST_SIZE 0x0008 /* 8 bytes */
83#define MFC_MAX_DMA_LIST_SIZE 0x4000 /* 16K bytes */
84
85#define MFC_TAGID_TO_TAGMASK(tag_id) (1 << (tag_id & 0x1F))
86
87/* Events for Channels 0-2 */
88#define MFC_DMA_TAG_STATUS_UPDATE_EVENT 0x00000001
89#define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT 0x00000002
90#define MFC_DMA_QUEUE_AVAILABLE_EVENT 0x00000008
91#define MFC_SPU_MAILBOX_WRITTEN_EVENT 0x00000010
92#define MFC_DECREMENTER_EVENT 0x00000020
93#define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT 0x00000040
94#define MFC_PU_MAILBOX_AVAILABLE_EVENT 0x00000080
95#define MFC_SIGNAL_2_EVENT 0x00000100
96#define MFC_SIGNAL_1_EVENT 0x00000200
97#define MFC_LLR_LOST_EVENT 0x00000400
98#define MFC_PRIV_ATTN_EVENT 0x00000800
99#define MFC_MULTI_SRC_EVENT 0x00001000
100
101/* Flags indicating progress during context switch. */
102#define SPU_CONTEXT_SWITCH_PENDING 0UL
103#define SPU_CONTEXT_SWITCH_ACTIVE 1UL
104
105struct spu_context;
106struct spu_runqueue;
107
108struct spu {
109 const char *name;
110 unsigned long local_store_phys;
111 u8 *local_store;
112 unsigned long problem_phys;
113 struct spu_problem __iomem *problem;
114 struct spu_priv2 __iomem *priv2;
115 struct list_head list;
116 struct list_head sched_list;
117 struct list_head full_list;
118 int number;
119 unsigned int irqs[3];
120 u32 node;
121 u64 flags;
122 u64 dar;
123 u64 dsisr;
124 size_t ls_size;
125 unsigned int slb_replace;
126 struct mm_struct *mm;
127 struct spu_context *ctx;
128 struct spu_runqueue *rq;
129 unsigned long long timestamp;
130 pid_t pid;
131 int prio;
132 int class_0_pending;
133 spinlock_t register_lock;
134
135 void (* wbox_callback)(struct spu *spu);
136 void (* ibox_callback)(struct spu *spu);
137 void (* stop_callback)(struct spu *spu);
138 void (* mfc_callback)(struct spu *spu);
139 void (* dma_callback)(struct spu *spu, int type);
140
141 char irq_c0[8];
142 char irq_c1[8];
143 char irq_c2[8];
144
145 void* pdata; /* platform private data */
146 struct sys_device sysdev;
147};
148
149struct spu *spu_alloc(void);
150struct spu *spu_alloc_node(int node);
151void spu_free(struct spu *spu);
152int spu_irq_class_0_bottom(struct spu *spu);
153int spu_irq_class_1_bottom(struct spu *spu);
154void spu_irq_setaffinity(struct spu *spu, int cpu);
155
156/* system callbacks from the SPU */
157struct spu_syscall_block {
158 u64 nr_ret;
159 u64 parm[6];
160};
161extern long spu_sys_callback(struct spu_syscall_block *s);
162
163/* syscalls implemented in spufs */
164struct file;
165extern struct spufs_calls {
166 asmlinkage long (*create_thread)(const char __user *name,
167 unsigned int flags, mode_t mode);
168 asmlinkage long (*spu_run)(struct file *filp, __u32 __user *unpc,
169 __u32 __user *ustatus);
170 struct module *owner;
171} spufs_calls;
172
173/* coredump calls implemented in spufs */
174struct spu_coredump_calls {
175 asmlinkage int (*arch_notes_size)(void);
176 asmlinkage void (*arch_write_notes)(struct file *file);
177 struct module *owner;
178};
179
180/* return status from spu_run, same as in libspe */
181#define SPE_EVENT_DMA_ALIGNMENT 0x0008 /*A DMA alignment error */
182#define SPE_EVENT_SPE_ERROR 0x0010 /*An illegal instruction error*/
183#define SPE_EVENT_SPE_DATA_SEGMENT 0x0020 /*A DMA segmentation error */
184#define SPE_EVENT_SPE_DATA_STORAGE 0x0040 /*A DMA storage error */
185#define SPE_EVENT_INVALID_DMA 0x0800 /* Invalid MFC DMA */
186
187/*
188 * Flags for sys_spu_create.
189 */
190#define SPU_CREATE_EVENTS_ENABLED 0x0001
191#define SPU_CREATE_GANG 0x0002
192#define SPU_CREATE_NOSCHED 0x0004
193#define SPU_CREATE_ISOLATE 0x0008
194
195#define SPU_CREATE_FLAG_ALL 0x000f /* mask of all valid flags */
196
197
198#ifdef CONFIG_SPU_FS_MODULE
199int register_spu_syscalls(struct spufs_calls *calls);
200void unregister_spu_syscalls(struct spufs_calls *calls);
201#else
202static inline int register_spu_syscalls(struct spufs_calls *calls)
203{
204 return 0;
205}
206static inline void unregister_spu_syscalls(struct spufs_calls *calls)
207{
208}
209#endif /* MODULE */
210
211int register_arch_coredump_calls(struct spu_coredump_calls *calls);
212void unregister_arch_coredump_calls(struct spu_coredump_calls *calls);
213
214int spu_add_sysdev_attr(struct sysdev_attribute *attr);
215void spu_remove_sysdev_attr(struct sysdev_attribute *attr);
216
217int spu_add_sysdev_attr_group(struct attribute_group *attrs);
218void spu_remove_sysdev_attr_group(struct attribute_group *attrs);
219
220
221/*
222 * Notifier blocks:
223 *
224 * oprofile can get notified when a context switch is performed
225 * on an spe. The notifer function that gets called is passed
226 * a pointer to the SPU structure as well as the object-id that
227 * identifies the binary running on that SPU now.
228 *
229 * For a context save, the object-id that is passed is zero,
230 * identifying that the kernel will run from that moment on.
231 *
232 * For a context restore, the object-id is the value written
233 * to object-id spufs file from user space and the notifer
234 * function can assume that spu->ctx is valid.
235 */
236struct notifier_block;
237int spu_switch_event_register(struct notifier_block * n);
238int spu_switch_event_unregister(struct notifier_block * n);
239
240/*
241 * This defines the Local Store, Problem Area and Privlege Area of an SPU.
242 */
243
244union mfc_tag_size_class_cmd {
245 struct {
246 u16 mfc_size;
247 u16 mfc_tag;
248 u8 pad;
249 u8 mfc_rclassid;
250 u16 mfc_cmd;
251 } u;
252 struct {
253 u32 mfc_size_tag32;
254 u32 mfc_class_cmd32;
255 } by32;
256 u64 all64;
257};
258
259struct mfc_cq_sr {
260 u64 mfc_cq_data0_RW;
261 u64 mfc_cq_data1_RW;
262 u64 mfc_cq_data2_RW;
263 u64 mfc_cq_data3_RW;
264};
265
266struct spu_problem {
267#define MS_SYNC_PENDING 1L
268 u64 spc_mssync_RW; /* 0x0000 */
269 u8 pad_0x0008_0x3000[0x3000 - 0x0008];
270
271 /* DMA Area */
272 u8 pad_0x3000_0x3004[0x4]; /* 0x3000 */
273 u32 mfc_lsa_W; /* 0x3004 */
274 u64 mfc_ea_W; /* 0x3008 */
275 union mfc_tag_size_class_cmd mfc_union_W; /* 0x3010 */
276 u8 pad_0x3018_0x3104[0xec]; /* 0x3018 */
277 u32 dma_qstatus_R; /* 0x3104 */
278 u8 pad_0x3108_0x3204[0xfc]; /* 0x3108 */
279 u32 dma_querytype_RW; /* 0x3204 */
280 u8 pad_0x3208_0x321c[0x14]; /* 0x3208 */
281 u32 dma_querymask_RW; /* 0x321c */
282 u8 pad_0x3220_0x322c[0xc]; /* 0x3220 */
283 u32 dma_tagstatus_R; /* 0x322c */
284#define DMA_TAGSTATUS_INTR_ANY 1u
285#define DMA_TAGSTATUS_INTR_ALL 2u
286 u8 pad_0x3230_0x4000[0x4000 - 0x3230]; /* 0x3230 */
287
288 /* SPU Control Area */
289 u8 pad_0x4000_0x4004[0x4]; /* 0x4000 */
290 u32 pu_mb_R; /* 0x4004 */
291 u8 pad_0x4008_0x400c[0x4]; /* 0x4008 */
292 u32 spu_mb_W; /* 0x400c */
293 u8 pad_0x4010_0x4014[0x4]; /* 0x4010 */
294 u32 mb_stat_R; /* 0x4014 */
295 u8 pad_0x4018_0x401c[0x4]; /* 0x4018 */
296 u32 spu_runcntl_RW; /* 0x401c */
297#define SPU_RUNCNTL_STOP 0L
298#define SPU_RUNCNTL_RUNNABLE 1L
299#define SPU_RUNCNTL_ISOLATE 2L
300 u8 pad_0x4020_0x4024[0x4]; /* 0x4020 */
301 u32 spu_status_R; /* 0x4024 */
302#define SPU_STOP_STATUS_SHIFT 16
303#define SPU_STATUS_STOPPED 0x0
304#define SPU_STATUS_RUNNING 0x1
305#define SPU_STATUS_STOPPED_BY_STOP 0x2
306#define SPU_STATUS_STOPPED_BY_HALT 0x4
307#define SPU_STATUS_WAITING_FOR_CHANNEL 0x8
308#define SPU_STATUS_SINGLE_STEP 0x10
309#define SPU_STATUS_INVALID_INSTR 0x20
310#define SPU_STATUS_INVALID_CH 0x40
311#define SPU_STATUS_ISOLATED_STATE 0x80
312#define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
313#define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
314 u8 pad_0x4028_0x402c[0x4]; /* 0x4028 */
315 u32 spu_spe_R; /* 0x402c */
316 u8 pad_0x4030_0x4034[0x4]; /* 0x4030 */
317 u32 spu_npc_RW; /* 0x4034 */
318 u8 pad_0x4038_0x14000[0x14000 - 0x4038]; /* 0x4038 */
319
320 /* Signal Notification Area */
321 u8 pad_0x14000_0x1400c[0xc]; /* 0x14000 */
322 u32 signal_notify1; /* 0x1400c */
323 u8 pad_0x14010_0x1c00c[0x7ffc]; /* 0x14010 */
324 u32 signal_notify2; /* 0x1c00c */
325} __attribute__ ((aligned(0x20000)));
326
327/* SPU Privilege 2 State Area */
328struct spu_priv2 {
329 /* MFC Registers */
330 u8 pad_0x0000_0x1100[0x1100 - 0x0000]; /* 0x0000 */
331
332 /* SLB Management Registers */
333 u8 pad_0x1100_0x1108[0x8]; /* 0x1100 */
334 u64 slb_index_W; /* 0x1108 */
335#define SLB_INDEX_MASK 0x7L
336 u64 slb_esid_RW; /* 0x1110 */
337 u64 slb_vsid_RW; /* 0x1118 */
338#define SLB_VSID_SUPERVISOR_STATE (0x1ull << 11)
339#define SLB_VSID_SUPERVISOR_STATE_MASK (0x1ull << 11)
340#define SLB_VSID_PROBLEM_STATE (0x1ull << 10)
341#define SLB_VSID_PROBLEM_STATE_MASK (0x1ull << 10)
342#define SLB_VSID_EXECUTE_SEGMENT (0x1ull << 9)
343#define SLB_VSID_NO_EXECUTE_SEGMENT (0x1ull << 9)
344#define SLB_VSID_EXECUTE_SEGMENT_MASK (0x1ull << 9)
345#define SLB_VSID_4K_PAGE (0x0 << 8)
346#define SLB_VSID_LARGE_PAGE (0x1ull << 8)
347#define SLB_VSID_PAGE_SIZE_MASK (0x1ull << 8)
348#define SLB_VSID_CLASS_MASK (0x1ull << 7)
349#define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
350 u64 slb_invalidate_entry_W; /* 0x1120 */
351 u64 slb_invalidate_all_W; /* 0x1128 */
352 u8 pad_0x1130_0x2000[0x2000 - 0x1130]; /* 0x1130 */
353
354 /* Context Save / Restore Area */
355 struct mfc_cq_sr spuq[16]; /* 0x2000 */
356 struct mfc_cq_sr puq[8]; /* 0x2200 */
357 u8 pad_0x2300_0x3000[0x3000 - 0x2300]; /* 0x2300 */
358
359 /* MFC Control */
360 u64 mfc_control_RW; /* 0x3000 */
361#define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0)
362#define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0)
363#define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0)
364#define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8)
365#define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8)
366#define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8)
367#define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8)
368#define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14)
369#define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14)
370#define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15)
371#define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24)
372#define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24)
373#define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24)
374#define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32)
375#define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32)
376#define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
377#define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33)
378#define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33)
379#define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33)
380#define MFC_CNTL_DECREMENTER_HALTED (1ull << 35)
381#define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40)
382#define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40)
383 u8 pad_0x3008_0x4000[0x4000 - 0x3008]; /* 0x3008 */
384
385 /* Interrupt Mailbox */
386 u64 puint_mb_R; /* 0x4000 */
387 u8 pad_0x4008_0x4040[0x4040 - 0x4008]; /* 0x4008 */
388
389 /* SPU Control */
390 u64 spu_privcntl_RW; /* 0x4040 */
391#define SPU_PRIVCNTL_MODE_NORMAL (0x0ull << 0)
392#define SPU_PRIVCNTL_MODE_SINGLE_STEP (0x1ull << 0)
393#define SPU_PRIVCNTL_MODE_MASK (0x1ull << 0)
394#define SPU_PRIVCNTL_NO_ATTENTION_EVENT (0x0ull << 1)
395#define SPU_PRIVCNTL_ATTENTION_EVENT (0x1ull << 1)
396#define SPU_PRIVCNTL_ATTENTION_EVENT_MASK (0x1ull << 1)
397#define SPU_PRIVCNT_LOAD_REQUEST_NORMAL (0x0ull << 2)
398#define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK (0x1ull << 2)
399 u8 pad_0x4048_0x4058[0x10]; /* 0x4048 */
400 u64 spu_lslr_RW; /* 0x4058 */
401 u64 spu_chnlcntptr_RW; /* 0x4060 */
402 u64 spu_chnlcnt_RW; /* 0x4068 */
403 u64 spu_chnldata_RW; /* 0x4070 */
404 u64 spu_cfg_RW; /* 0x4078 */
405 u8 pad_0x4080_0x5000[0x5000 - 0x4080]; /* 0x4080 */
406
407 /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
408 u64 spu_pm_trace_tag_status_RW; /* 0x5000 */
409 u64 spu_tag_status_query_RW; /* 0x5008 */
410#define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
411#define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
412 u64 spu_cmd_buf1_RW; /* 0x5010 */
413#define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
414#define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
415 u64 spu_cmd_buf2_RW; /* 0x5018 */
416#define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
417#define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
418#define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
419 u64 spu_atomic_status_RW; /* 0x5020 */
420} __attribute__ ((aligned(0x20000)));
421
422/* SPU Privilege 1 State Area */
423struct spu_priv1 {
424 /* Control and Configuration Area */
425 u64 mfc_sr1_RW; /* 0x000 */
426#define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 0x01ull
427#define MFC_STATE1_BUS_TLBIE_MASK 0x02ull
428#define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
429#define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull
430#define MFC_STATE1_RELOCATE_MASK 0x10ull
431#define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull
432 u64 mfc_lpid_RW; /* 0x008 */
433 u64 spu_idr_RW; /* 0x010 */
434 u64 mfc_vr_RO; /* 0x018 */
435#define MFC_VERSION_BITS (0xffff << 16)
436#define MFC_REVISION_BITS (0xffff)
437#define MFC_GET_VERSION_BITS(vr) (((vr) & MFC_VERSION_BITS) >> 16)
438#define MFC_GET_REVISION_BITS(vr) ((vr) & MFC_REVISION_BITS)
439 u64 spu_vr_RO; /* 0x020 */
440#define SPU_VERSION_BITS (0xffff << 16)
441#define SPU_REVISION_BITS (0xffff)
442#define SPU_GET_VERSION_BITS(vr) (vr & SPU_VERSION_BITS) >> 16
443#define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS)
444 u8 pad_0x28_0x100[0x100 - 0x28]; /* 0x28 */
445
446 /* Interrupt Area */
447 u64 int_mask_RW[3]; /* 0x100 */
448#define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L
449#define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR 0x2L
450#define CLASS0_ENABLE_SPU_ERROR_INTR 0x4L
451#define CLASS0_ENABLE_MFC_FIR_INTR 0x8L
452#define CLASS1_ENABLE_SEGMENT_FAULT_INTR 0x1L
453#define CLASS1_ENABLE_STORAGE_FAULT_INTR 0x2L
454#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
455#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
456#define CLASS2_ENABLE_MAILBOX_INTR 0x1L
457#define CLASS2_ENABLE_SPU_STOP_INTR 0x2L
458#define CLASS2_ENABLE_SPU_HALT_INTR 0x4L
459#define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
460 u8 pad_0x118_0x140[0x28]; /* 0x118 */
461 u64 int_stat_RW[3]; /* 0x140 */
462 u8 pad_0x158_0x180[0x28]; /* 0x158 */
463 u64 int_route_RW; /* 0x180 */
464
465 /* Interrupt Routing */
466 u8 pad_0x188_0x200[0x200 - 0x188]; /* 0x188 */
467
468 /* Atomic Unit Control Area */
469 u64 mfc_atomic_flush_RW; /* 0x200 */
470#define mfc_atomic_flush_enable 0x1L
471 u8 pad_0x208_0x280[0x78]; /* 0x208 */
472 u64 resource_allocation_groupID_RW; /* 0x280 */
473 u64 resource_allocation_enable_RW; /* 0x288 */
474 u8 pad_0x290_0x3c8[0x3c8 - 0x290]; /* 0x290 */
475
476 /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
477
478 u64 smf_sbi_signal_sel; /* 0x3c8 */
479#define smf_sbi_mask_lsb 56
480#define smf_sbi_shift (63 - smf_sbi_mask_lsb)
481#define smf_sbi_mask (0x301LL << smf_sbi_shift)
482#define smf_sbi_bus0_bits (0x001LL << smf_sbi_shift)
483#define smf_sbi_bus2_bits (0x100LL << smf_sbi_shift)
484#define smf_sbi2_bus0_bits (0x201LL << smf_sbi_shift)
485#define smf_sbi2_bus2_bits (0x300LL << smf_sbi_shift)
486 u64 smf_ato_signal_sel; /* 0x3d0 */
487#define smf_ato_mask_lsb 35
488#define smf_ato_shift (63 - smf_ato_mask_lsb)
489#define smf_ato_mask (0x3LL << smf_ato_shift)
490#define smf_ato_bus0_bits (0x2LL << smf_ato_shift)
491#define smf_ato_bus2_bits (0x1LL << smf_ato_shift)
492 u8 pad_0x3d8_0x400[0x400 - 0x3d8]; /* 0x3d8 */
493
494 /* TLB Management Registers */
495 u64 mfc_sdr_RW; /* 0x400 */
496 u8 pad_0x408_0x500[0xf8]; /* 0x408 */
497 u64 tlb_index_hint_RO; /* 0x500 */
498 u64 tlb_index_W; /* 0x508 */
499 u64 tlb_vpn_RW; /* 0x510 */
500 u64 tlb_rpn_RW; /* 0x518 */
501 u8 pad_0x520_0x540[0x20]; /* 0x520 */
502 u64 tlb_invalidate_entry_W; /* 0x540 */
503 u64 tlb_invalidate_all_W; /* 0x548 */
504 u8 pad_0x550_0x580[0x580 - 0x550]; /* 0x550 */
505
506 /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
507 u64 smm_hid; /* 0x580 */
508#define PAGE_SIZE_MASK 0xf000000000000000ull
509#define PAGE_SIZE_16MB_64KB 0x2000000000000000ull
510 u8 pad_0x588_0x600[0x600 - 0x588]; /* 0x588 */
511
512 /* MFC Status/Control Area */
513 u64 mfc_accr_RW; /* 0x600 */
514#define MFC_ACCR_EA_ACCESS_GET (1 << 0)
515#define MFC_ACCR_EA_ACCESS_PUT (1 << 1)
516#define MFC_ACCR_LS_ACCESS_GET (1 << 3)
517#define MFC_ACCR_LS_ACCESS_PUT (1 << 4)
518 u8 pad_0x608_0x610[0x8]; /* 0x608 */
519 u64 mfc_dsisr_RW; /* 0x610 */
520#define MFC_DSISR_PTE_NOT_FOUND (1 << 30)
521#define MFC_DSISR_ACCESS_DENIED (1 << 27)
522#define MFC_DSISR_ATOMIC (1 << 26)
523#define MFC_DSISR_ACCESS_PUT (1 << 25)
524#define MFC_DSISR_ADDR_MATCH (1 << 22)
525#define MFC_DSISR_LS (1 << 17)
526#define MFC_DSISR_L (1 << 16)
527#define MFC_DSISR_ADDRESS_OVERFLOW (1 << 0)
528 u8 pad_0x618_0x620[0x8]; /* 0x618 */
529 u64 mfc_dar_RW; /* 0x620 */
530 u8 pad_0x628_0x700[0x700 - 0x628]; /* 0x628 */
531
532 /* Replacement Management Table (RMT) Area */
533 u64 rmt_index_RW; /* 0x700 */
534 u8 pad_0x708_0x710[0x8]; /* 0x708 */
535 u64 rmt_data1_RW; /* 0x710 */
536 u8 pad_0x718_0x800[0x800 - 0x718]; /* 0x718 */
537
538 /* Control/Configuration Registers */
539 u64 mfc_dsir_R; /* 0x800 */
540#define MFC_DSIR_Q (1 << 31)
541#define MFC_DSIR_SPU_QUEUE MFC_DSIR_Q
542 u64 mfc_lsacr_RW; /* 0x808 */
543#define MFC_LSACR_COMPARE_MASK ((~0ull) << 32)
544#define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32)
545 u64 mfc_lscrr_R; /* 0x810 */
546#define MFC_LSCRR_Q (1 << 31)
547#define MFC_LSCRR_SPU_QUEUE MFC_LSCRR_Q
548#define MFC_LSCRR_QI_SHIFT 32
549#define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT)
550 u8 pad_0x818_0x820[0x8]; /* 0x818 */
551 u64 mfc_tclass_id_RW; /* 0x820 */
552#define MFC_TCLASS_ID_ENABLE (1L << 0L)
553#define MFC_TCLASS_SLOT2_ENABLE (1L << 5L)
554#define MFC_TCLASS_SLOT1_ENABLE (1L << 6L)
555#define MFC_TCLASS_SLOT0_ENABLE (1L << 7L)
556#define MFC_TCLASS_QUOTA_2_SHIFT 8L
557#define MFC_TCLASS_QUOTA_1_SHIFT 16L
558#define MFC_TCLASS_QUOTA_0_SHIFT 24L
559#define MFC_TCLASS_QUOTA_2_MASK (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
560#define MFC_TCLASS_QUOTA_1_MASK (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
561#define MFC_TCLASS_QUOTA_0_MASK (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
562 u8 pad_0x828_0x900[0x900 - 0x828]; /* 0x828 */
563
564 /* Real Mode Support Registers */
565 u64 mfc_rm_boundary; /* 0x900 */
566 u8 pad_0x908_0x938[0x30]; /* 0x908 */
567 u64 smf_dma_signal_sel; /* 0x938 */
568#define mfc_dma1_mask_lsb 41
569#define mfc_dma1_shift (63 - mfc_dma1_mask_lsb)
570#define mfc_dma1_mask (0x3LL << mfc_dma1_shift)
571#define mfc_dma1_bits (0x1LL << mfc_dma1_shift)
572#define mfc_dma2_mask_lsb 43
573#define mfc_dma2_shift (63 - mfc_dma2_mask_lsb)
574#define mfc_dma2_mask (0x3LL << mfc_dma2_shift)
575#define mfc_dma2_bits (0x1LL << mfc_dma2_shift)
576 u8 pad_0x940_0xa38[0xf8]; /* 0x940 */
577 u64 smm_signal_sel; /* 0xa38 */
578#define smm_sig_mask_lsb 12
579#define smm_sig_shift (63 - smm_sig_mask_lsb)
580#define smm_sig_mask (0x3LL << smm_sig_shift)
581#define smm_sig_bus0_bits (0x2LL << smm_sig_shift)
582#define smm_sig_bus2_bits (0x1LL << smm_sig_shift)
583 u8 pad_0xa40_0xc00[0xc00 - 0xa40]; /* 0xa40 */
584
585 /* DMA Command Error Area */
586 u64 mfc_cer_R; /* 0xc00 */
587#define MFC_CER_Q (1 << 31)
588#define MFC_CER_SPU_QUEUE MFC_CER_Q
589 u8 pad_0xc08_0x1000[0x1000 - 0xc08]; /* 0xc08 */
590
591 /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
592 /* DMA Command Error Area */
593 u64 spu_ecc_cntl_RW; /* 0x1000 */
594#define SPU_ECC_CNTL_E (1ull << 0ull)
595#define SPU_ECC_CNTL_ENABLE SPU_ECC_CNTL_E
596#define SPU_ECC_CNTL_DISABLE (~SPU_ECC_CNTL_E & 1L)
597#define SPU_ECC_CNTL_S (1ull << 1ull)
598#define SPU_ECC_STOP_AFTER_ERROR SPU_ECC_CNTL_S
599#define SPU_ECC_CONTINUE_AFTER_ERROR (~SPU_ECC_CNTL_S & 2L)
600#define SPU_ECC_CNTL_B (1ull << 2ull)
601#define SPU_ECC_BACKGROUND_ENABLE SPU_ECC_CNTL_B
602#define SPU_ECC_BACKGROUND_DISABLE (~SPU_ECC_CNTL_B & 4L)
603#define SPU_ECC_CNTL_I_SHIFT 3ull
604#define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT)
605#define SPU_ECC_WRITE_ALWAYS (~SPU_ECC_CNTL_I & 12L)
606#define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT)
607#define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT)
608#define SPU_ECC_CNTL_D (1ull << 5ull)
609#define SPU_ECC_DETECTION_ENABLE SPU_ECC_CNTL_D
610#define SPU_ECC_DETECTION_DISABLE (~SPU_ECC_CNTL_D & 32L)
611 u64 spu_ecc_stat_RW; /* 0x1008 */
612#define SPU_ECC_CORRECTED_ERROR (1ull << 0ul)
613#define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul)
614#define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul)
615#define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul)
616#define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul)
617#define SPU_ECC_DATA_ERROR (1ull << 5ul)
618#define SPU_ECC_DMA_ERROR (1ull << 6ul)
619#define SPU_ECC_STATUS_CNT_MASK (256ull << 8)
620 u64 spu_ecc_addr_RW; /* 0x1010 */
621 u64 spu_err_mask_RW; /* 0x1018 */
622#define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul)
623#define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul)
624 u8 pad_0x1020_0x1028[0x1028 - 0x1020]; /* 0x1020 */
625
626 /* SPU Debug-Trace Bus (DTB) Selection Registers */
627 u64 spu_trig0_sel; /* 0x1028 */
628 u64 spu_trig1_sel; /* 0x1030 */
629 u64 spu_trig2_sel; /* 0x1038 */
630 u64 spu_trig3_sel; /* 0x1040 */
631 u64 spu_trace_sel; /* 0x1048 */
632#define spu_trace_sel_mask 0x1f1fLL
633#define spu_trace_sel_bus0_bits 0x1000LL
634#define spu_trace_sel_bus2_bits 0x0010LL
635 u64 spu_event0_sel; /* 0x1050 */
636 u64 spu_event1_sel; /* 0x1058 */
637 u64 spu_event2_sel; /* 0x1060 */
638 u64 spu_event3_sel; /* 0x1068 */
639 u64 spu_trace_cntl; /* 0x1070 */
640} __attribute__ ((aligned(0x2000)));
641
642#endif /* __KERNEL__ */
643#endif