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1/*
2 * AVR32 OCD Registers
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_AVR32_OCD_H
11#define __ASM_AVR32_OCD_H
12
13/* Debug Registers */
14#define DBGREG_DID 0
15#define DBGREG_DC 8
16#define DBGREG_DS 16
17#define DBGREG_RWCS 28
18#define DBGREG_RWA 36
19#define DBGREG_RWD 40
20#define DBGREG_WT 44
21#define DBGREG_DTC 52
22#define DBGREG_DTSA0 56
23#define DBGREG_DTSA1 60
24#define DBGREG_DTEA0 72
25#define DBGREG_DTEA1 76
26#define DBGREG_BWC0A 88
27#define DBGREG_BWC0B 92
28#define DBGREG_BWC1A 96
29#define DBGREG_BWC1B 100
30#define DBGREG_BWC2A 104
31#define DBGREG_BWC2B 108
32#define DBGREG_BWC3A 112
33#define DBGREG_BWC3B 116
34#define DBGREG_BWA0A 120
35#define DBGREG_BWA0B 124
36#define DBGREG_BWA1A 128
37#define DBGREG_BWA1B 132
38#define DBGREG_BWA2A 136
39#define DBGREG_BWA2B 140
40#define DBGREG_BWA3A 144
41#define DBGREG_BWA3B 148
42#define DBGREG_BWD3A 153
43#define DBGREG_BWD3B 156
44
45#define DBGREG_PID 284
46
47#define SABAH_OCD 0x01
48#define SABAH_ICACHE 0x02
49#define SABAH_MEM_CACHED 0x04
50#define SABAH_MEM_UNCACHED 0x05
51
52/* Fields in the Development Control register */
53#define DC_SS_BIT 8
54
55#define DC_SS (1 << DC_SS_BIT)
56#define DC_DBE (1 << 13)
57#define DC_RID (1 << 27)
58#define DC_ORP (1 << 28)
59#define DC_MM (1 << 29)
60#define DC_RES (1 << 30)
61
62/* Fields in the Development Status register */
63#define DS_SSS (1 << 0)
64#define DS_SWB (1 << 1)
65#define DS_HWB (1 << 2)
66#define DS_BP_SHIFT 8
67#define DS_BP_MASK (0xff << DS_BP_SHIFT)
68
69#define __mfdr(addr) \
70({ \
71 register unsigned long value; \
72 asm volatile("mfdr %0, %1" : "=r"(value) : "i"(addr)); \
73 value; \
74})
75#define __mtdr(addr, value) \
76 asm volatile("mtdr %0, %1" : : "i"(addr), "r"(value))
77
78#endif /* __ASM_AVR32_OCD_H */