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Linux kernel mirror (for testing)
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linux
1/*
2 * linux/include/asm-arm/arch-omap/pm.h
3 *
4 * Header file for OMAP Power Management Routines
5 *
6 * Author: MontaVista Software, Inc.
7 * support@mvista.com
8 *
9 * Copyright 2002 MontaVista Software Inc.
10 *
11 * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 */
33
34#ifndef __ASM_ARCH_OMAP_PM_H
35#define __ASM_ARCH_OMAP_PM_H
36
37/*
38 * ----------------------------------------------------------------------------
39 * Register and offset definitions to be used in PM assembler code
40 * ----------------------------------------------------------------------------
41 */
42#define CLKGEN_REG_ASM_BASE io_p2v(0xfffece00)
43#define ARM_IDLECT1_ASM_OFFSET 0x04
44#define ARM_IDLECT2_ASM_OFFSET 0x08
45
46#define TCMIF_ASM_BASE io_p2v(0xfffecc00)
47#define EMIFS_CONFIG_ASM_OFFSET 0x0c
48#define EMIFF_SDRAM_CONFIG_ASM_OFFSET 0x20
49
50/*
51 * ----------------------------------------------------------------------------
52 * Power management bitmasks
53 * ----------------------------------------------------------------------------
54 */
55#define IDLE_WAIT_CYCLES 0x00000fff
56#define PERIPHERAL_ENABLE 0x2
57
58#define SELF_REFRESH_MODE 0x0c000001
59#define IDLE_EMIFS_REQUEST 0xc
60#define MODEM_32K_EN 0x1
61#define PER_EN 0x1
62
63#define CPU_SUSPEND_SIZE 200
64#define ULPD_LOW_PWR_EN 0x0001
65#define ULPD_DEEP_SLEEP_TRANSITION_EN 0x0010
66#define ULPD_SETUP_ANALOG_CELL_3_VAL 0
67#define ULPD_POWER_CTRL_REG_VAL 0x0219
68
69#define DSP_IDLE_DELAY 10
70#define DSP_IDLE 0x0040
71#define DSP_RST 0x0004
72#define DSP_ENABLE 0x0002
73#define SUFFICIENT_DSP_RESET_TIME 1000
74#define DEFAULT_MPUI_CONFIG 0x05cf
75#define ENABLE_XORCLK 0x2
76#define DSP_CLOCK_ENABLE 0x2000
77#define DSP_IDLE_MODE 0x2
78#define TC_IDLE_REQUEST (0x0000000c)
79
80#define IRQ_LEVEL2 (1<<0)
81#define IRQ_KEYBOARD (1<<1)
82#define IRQ_UART2 (1<<15)
83
84#define PDE_BIT 0x08
85#define PWD_EN_BIT 0x04
86#define EN_PERCK_BIT 0x04
87
88#define OMAP1510_DEEP_SLEEP_REQUEST 0x0ec7
89#define OMAP1510_BIG_SLEEP_REQUEST 0x0cc5
90#define OMAP1510_IDLE_LOOP_REQUEST 0x0c00
91#define OMAP1510_IDLE_CLOCK_DOMAINS 0x2
92
93/* Both big sleep and deep sleep use same values. Difference is in ULPD. */
94#define OMAP1610_IDLECT1_SLEEP_VAL 0x13c7
95#define OMAP1610_IDLECT2_SLEEP_VAL 0x09c7
96#define OMAP1610_IDLECT3_VAL 0x3f
97#define OMAP1610_IDLECT3_SLEEP_ORMASK 0x2c
98#define OMAP1610_IDLECT3 0xfffece24
99#define OMAP1610_IDLE_LOOP_REQUEST 0x0400
100
101#define OMAP730_IDLECT1_SLEEP_VAL 0x16c7
102#define OMAP730_IDLECT2_SLEEP_VAL 0x09c7
103#define OMAP730_IDLECT3_VAL 0x3f
104#define OMAP730_IDLECT3 0xfffece24
105#define OMAP730_IDLE_LOOP_REQUEST 0x0C00
106
107#if !defined(CONFIG_ARCH_OMAP730) && \
108 !defined(CONFIG_ARCH_OMAP15XX) && \
109 !defined(CONFIG_ARCH_OMAP16XX) && \
110 !defined(CONFIG_ARCH_OMAP24XX)
111#error "Power management for this processor not implemented yet"
112#endif
113
114#ifndef __ASSEMBLER__
115
116#include <linux/clk.h>
117
118extern void prevent_idle_sleep(void);
119extern void allow_idle_sleep(void);
120
121/**
122 * clk_deny_idle - Prevents the clock from being idled during MPU idle
123 * @clk: clock signal handle
124 */
125void clk_deny_idle(struct clk *clk);
126
127/**
128 * clk_allow_idle - Counters previous clk_deny_idle
129 * @clk: clock signal handle
130 */
131void clk_deny_idle(struct clk *clk);
132
133extern void omap_pm_idle(void);
134extern void omap_pm_suspend(void);
135extern void omap730_cpu_suspend(unsigned short, unsigned short);
136extern void omap1510_cpu_suspend(unsigned short, unsigned short);
137extern void omap1610_cpu_suspend(unsigned short, unsigned short);
138extern void omap24xx_cpu_suspend(u32 dll_ctrl, u32 cpu_revision);
139extern void omap730_idle_loop_suspend(void);
140extern void omap1510_idle_loop_suspend(void);
141extern void omap1610_idle_loop_suspend(void);
142extern void omap24xx_idle_loop_suspend(void);
143
144extern unsigned int omap730_cpu_suspend_sz;
145extern unsigned int omap1510_cpu_suspend_sz;
146extern unsigned int omap1610_cpu_suspend_sz;
147extern unsigned int omap24xx_cpu_suspend_sz;
148extern unsigned int omap730_idle_loop_suspend_sz;
149extern unsigned int omap1510_idle_loop_suspend_sz;
150extern unsigned int omap1610_idle_loop_suspend_sz;
151extern unsigned int omap24xx_idle_loop_suspend_sz;
152
153#ifdef CONFIG_OMAP_SERIAL_WAKE
154extern void omap_serial_wake_trigger(int enable);
155#else
156#define omap_serial_wakeup_init() {}
157#define omap_serial_wake_trigger(x) {}
158#endif /* CONFIG_OMAP_SERIAL_WAKE */
159
160#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
161#define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
162#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
163
164#define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x)
165#define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x))
166#define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x]
167
168#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
169#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
170#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
171
172#define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x)
173#define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x))
174#define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]
175
176#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
177#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
178#define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
179
180#define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x)
181#define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
182#define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
183
184#define OMAP24XX_SAVE(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x] = x
185#define OMAP24XX_RESTORE(x) x = omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
186#define OMAP24XX_SHOW(x) omap24xx_sleep_save[OMAP24XX_SLEEP_SAVE_##x]
187
188/*
189 * List of global OMAP registers to preserve.
190 * More ones like CP and general purpose register values are preserved
191 * with the stack pointer in sleep.S.
192 */
193
194enum arm_save_state {
195 ARM_SLEEP_SAVE_START = 0,
196 /*
197 * MPU control registers 32 bits
198 */
199 ARM_SLEEP_SAVE_ARM_CKCTL,
200 ARM_SLEEP_SAVE_ARM_IDLECT1,
201 ARM_SLEEP_SAVE_ARM_IDLECT2,
202 ARM_SLEEP_SAVE_ARM_IDLECT3,
203 ARM_SLEEP_SAVE_ARM_EWUPCT,
204 ARM_SLEEP_SAVE_ARM_RSTCT1,
205 ARM_SLEEP_SAVE_ARM_RSTCT2,
206 ARM_SLEEP_SAVE_ARM_SYSST,
207 ARM_SLEEP_SAVE_SIZE
208};
209
210enum dsp_save_state {
211 DSP_SLEEP_SAVE_START = 0,
212 /*
213 * DSP registers 16 bits
214 */
215 DSP_SLEEP_SAVE_DSP_IDLECT2,
216 DSP_SLEEP_SAVE_SIZE
217};
218
219enum ulpd_save_state {
220 ULPD_SLEEP_SAVE_START = 0,
221 /*
222 * ULPD registers 16 bits
223 */
224 ULPD_SLEEP_SAVE_ULPD_IT_STATUS,
225 ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL,
226 ULPD_SLEEP_SAVE_ULPD_SOFT_REQ,
227 ULPD_SLEEP_SAVE_ULPD_STATUS_REQ,
228 ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL,
229 ULPD_SLEEP_SAVE_ULPD_POWER_CTRL,
230 ULPD_SLEEP_SAVE_SIZE
231};
232
233enum mpui1510_save_state {
234 MPUI1510_SLEEP_SAVE_START = 0,
235 /*
236 * MPUI registers 32 bits
237 */
238 MPUI1510_SLEEP_SAVE_MPUI_CTRL,
239 MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
240 MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
241 MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS,
242 MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
243 MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
244 MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
245 MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
246#if defined(CONFIG_ARCH_OMAP15XX)
247 MPUI1510_SLEEP_SAVE_SIZE
248#else
249 MPUI1510_SLEEP_SAVE_SIZE = 0
250#endif
251};
252
253enum mpui730_save_state {
254 MPUI730_SLEEP_SAVE_START = 0,
255 /*
256 * MPUI registers 32 bits
257 */
258 MPUI730_SLEEP_SAVE_MPUI_CTRL,
259 MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
260 MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
261 MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS,
262 MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
263 MPUI730_SLEEP_SAVE_EMIFS_CONFIG,
264 MPUI730_SLEEP_SAVE_OMAP_IH1_MIR,
265 MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR,
266 MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR,
267#if defined(CONFIG_ARCH_OMAP730)
268 MPUI730_SLEEP_SAVE_SIZE
269#else
270 MPUI730_SLEEP_SAVE_SIZE = 0
271#endif
272};
273
274enum mpui1610_save_state {
275 MPUI1610_SLEEP_SAVE_START = 0,
276 /*
277 * MPUI registers 32 bits
278 */
279 MPUI1610_SLEEP_SAVE_MPUI_CTRL,
280 MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
281 MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
282 MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS,
283 MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
284 MPUI1610_SLEEP_SAVE_EMIFS_CONFIG,
285 MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR,
286 MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR,
287 MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR,
288 MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR,
289 MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR,
290#if defined(CONFIG_ARCH_OMAP16XX)
291 MPUI1610_SLEEP_SAVE_SIZE
292#else
293 MPUI1610_SLEEP_SAVE_SIZE = 0
294#endif
295};
296
297enum omap24xx_save_state {
298 OMAP24XX_SLEEP_SAVE_START = 0,
299 OMAP24XX_SLEEP_SAVE_INTC_MIR0,
300 OMAP24XX_SLEEP_SAVE_INTC_MIR1,
301 OMAP24XX_SLEEP_SAVE_INTC_MIR2,
302
303 OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MPU,
304 OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_CORE,
305 OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_GFX,
306 OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_DSP,
307 OMAP24XX_SLEEP_SAVE_CM_CLKSTCTRL_MDM,
308
309 OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MPU,
310 OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_CORE,
311 OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_GFX,
312 OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_DSP,
313 OMAP24XX_SLEEP_SAVE_PM_PWSTCTRL_MDM,
314
315 OMAP24XX_SLEEP_SAVE_CM_IDLEST1_CORE,
316 OMAP24XX_SLEEP_SAVE_CM_IDLEST2_CORE,
317 OMAP24XX_SLEEP_SAVE_CM_IDLEST3_CORE,
318 OMAP24XX_SLEEP_SAVE_CM_IDLEST4_CORE,
319 OMAP24XX_SLEEP_SAVE_CM_IDLEST_GFX,
320 OMAP24XX_SLEEP_SAVE_CM_IDLEST_WKUP,
321 OMAP24XX_SLEEP_SAVE_CM_IDLEST_CKGEN,
322 OMAP24XX_SLEEP_SAVE_CM_IDLEST_DSP,
323 OMAP24XX_SLEEP_SAVE_CM_IDLEST_MDM,
324
325 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE1_CORE,
326 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE2_CORE,
327 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE3_CORE,
328 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE4_CORE,
329 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_WKUP,
330 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_PLL,
331 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_DSP,
332 OMAP24XX_SLEEP_SAVE_CM_AUTOIDLE_MDM,
333
334 OMAP24XX_SLEEP_SAVE_CM_FCLKEN1_CORE,
335 OMAP24XX_SLEEP_SAVE_CM_FCLKEN2_CORE,
336 OMAP24XX_SLEEP_SAVE_CM_ICLKEN1_CORE,
337 OMAP24XX_SLEEP_SAVE_CM_ICLKEN2_CORE,
338 OMAP24XX_SLEEP_SAVE_CM_ICLKEN3_CORE,
339 OMAP24XX_SLEEP_SAVE_CM_ICLKEN4_CORE,
340 OMAP24XX_SLEEP_SAVE_GPIO1_IRQENABLE1,
341 OMAP24XX_SLEEP_SAVE_GPIO2_IRQENABLE1,
342 OMAP24XX_SLEEP_SAVE_GPIO3_IRQENABLE1,
343 OMAP24XX_SLEEP_SAVE_GPIO4_IRQENABLE1,
344 OMAP24XX_SLEEP_SAVE_GPIO3_OE,
345 OMAP24XX_SLEEP_SAVE_GPIO4_OE,
346 OMAP24XX_SLEEP_SAVE_GPIO3_RISINGDETECT,
347 OMAP24XX_SLEEP_SAVE_GPIO3_FALLINGDETECT,
348 OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SPI1_NCS2,
349 OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_MCBSP1_DX,
350 OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SSI1_FLAG_TX,
351 OMAP24XX_SLEEP_SAVE_CONTROL_PADCONF_SYS_NIRQW0,
352 OMAP24XX_SLEEP_SAVE_SIZE
353};
354
355#endif /* ASSEMBLER */
356#endif /* __ASM_ARCH_OMAP_PM_H */