tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * This file contains the routines for initializing the MMU
3 * on the 4xx series of chips.
4 * -- paulus
5 *
6 * Derived from arch/ppc/mm/init.c:
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 *
9 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
10 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
11 * Copyright (C) 1996 Paul Mackerras
12 * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
13 *
14 * Derived from "arch/i386/mm/init.c"
15 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation; either version
20 * 2 of the License, or (at your option) any later version.
21 *
22 */
23
24#include <linux/signal.h>
25#include <linux/sched.h>
26#include <linux/kernel.h>
27#include <linux/errno.h>
28#include <linux/string.h>
29#include <linux/types.h>
30#include <linux/ptrace.h>
31#include <linux/mman.h>
32#include <linux/mm.h>
33#include <linux/swap.h>
34#include <linux/stddef.h>
35#include <linux/vmalloc.h>
36#include <linux/init.h>
37#include <linux/delay.h>
38#include <linux/highmem.h>
39
40#include <asm/pgalloc.h>
41#include <asm/prom.h>
42#include <asm/io.h>
43#include <asm/mmu_context.h>
44#include <asm/pgtable.h>
45#include <asm/mmu.h>
46#include <asm/uaccess.h>
47#include <asm/smp.h>
48#include <asm/bootx.h>
49#include <asm/machdep.h>
50#include <asm/setup.h>
51#include "mmu_decl.h"
52
53extern int __map_without_ltlbs;
54/*
55 * MMU_init_hw does the chip-specific initialization of the MMU hardware.
56 */
57void __init MMU_init_hw(void)
58{
59 /*
60 * The Zone Protection Register (ZPR) defines how protection will
61 * be applied to every page which is a member of a given zone. At
62 * present, we utilize only two of the 4xx's zones.
63 * The zone index bits (of ZSEL) in the PTE are used for software
64 * indicators, except the LSB. For user access, zone 1 is used,
65 * for kernel access, zone 0 is used. We set all but zone 1
66 * to zero, allowing only kernel access as indicated in the PTE.
67 * For zone 1, we set a 01 binary (a value of 10 will not work)
68 * to allow user access as indicated in the PTE. This also allows
69 * kernel access as indicated in the PTE.
70 */
71
72 mtspr(SPRN_ZPR, 0x10000000);
73
74 flush_instruction_cache();
75
76 /*
77 * Set up the real-mode cache parameters for the exception vector
78 * handlers (which are run in real-mode).
79 */
80
81 mtspr(SPRN_DCWR, 0x00000000); /* All caching is write-back */
82
83 /*
84 * Cache instruction and data space where the exception
85 * vectors and the kernel live in real-mode.
86 */
87
88 mtspr(SPRN_DCCR, 0xF0000000); /* 512 MB of data space at 0x0. */
89 mtspr(SPRN_ICCR, 0xF0000000); /* 512 MB of instr. space at 0x0. */
90}
91
92#define LARGE_PAGE_SIZE_16M (1<<24)
93#define LARGE_PAGE_SIZE_4M (1<<22)
94
95unsigned long __init mmu_mapin_ram(void)
96{
97 unsigned long v, s;
98 phys_addr_t p;
99
100 v = KERNELBASE;
101 p = PPC_MEMSTART;
102 s = 0;
103
104 if (__map_without_ltlbs) {
105 return s;
106 }
107
108 while (s <= (total_lowmem - LARGE_PAGE_SIZE_16M)) {
109 pmd_t *pmdp;
110 unsigned long val = p | _PMD_SIZE_16M | _PAGE_HWEXEC | _PAGE_HWWRITE;
111
112 pmdp = pmd_offset(pgd_offset_k(v), v);
113 pmd_val(*pmdp++) = val;
114 pmd_val(*pmdp++) = val;
115 pmd_val(*pmdp++) = val;
116 pmd_val(*pmdp++) = val;
117
118 v += LARGE_PAGE_SIZE_16M;
119 p += LARGE_PAGE_SIZE_16M;
120 s += LARGE_PAGE_SIZE_16M;
121 }
122
123 while (s <= (total_lowmem - LARGE_PAGE_SIZE_4M)) {
124 pmd_t *pmdp;
125 unsigned long val = p | _PMD_SIZE_4M | _PAGE_HWEXEC | _PAGE_HWWRITE;
126
127 pmdp = pmd_offset(pgd_offset_k(v), v);
128 pmd_val(*pmdp) = val;
129
130 v += LARGE_PAGE_SIZE_4M;
131 p += LARGE_PAGE_SIZE_4M;
132 s += LARGE_PAGE_SIZE_4M;
133 }
134
135 return s;
136}