tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1#ifndef VMX_H
2#define VMX_H
3
4/*
5 * vmx.h: VMX Architecture related definitions
6 * Copyright (c) 2004, Intel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
19 * Place - Suite 330, Boston, MA 02111-1307 USA.
20 *
21 * A few random additions are:
22 * Copyright (C) 2006 Qumranet
23 * Avi Kivity <avi@qumranet.com>
24 * Yaniv Kamay <yaniv@qumranet.com>
25 *
26 */
27
28#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
29#define CPU_BASED_USE_TSC_OFFSETING 0x00000008
30#define CPU_BASED_HLT_EXITING 0x00000080
31#define CPU_BASED_INVDPG_EXITING 0x00000200
32#define CPU_BASED_MWAIT_EXITING 0x00000400
33#define CPU_BASED_RDPMC_EXITING 0x00000800
34#define CPU_BASED_RDTSC_EXITING 0x00001000
35#define CPU_BASED_CR8_LOAD_EXITING 0x00080000
36#define CPU_BASED_CR8_STORE_EXITING 0x00100000
37#define CPU_BASED_TPR_SHADOW 0x00200000
38#define CPU_BASED_MOV_DR_EXITING 0x00800000
39#define CPU_BASED_UNCOND_IO_EXITING 0x01000000
40#define CPU_BASED_ACTIVATE_IO_BITMAP 0x02000000
41#define CPU_BASED_MSR_BITMAPS 0x10000000
42#define CPU_BASED_MONITOR_EXITING 0x20000000
43#define CPU_BASED_PAUSE_EXITING 0x40000000
44
45#define PIN_BASED_EXT_INTR_MASK 0x1
46#define PIN_BASED_NMI_EXITING 0x8
47
48#define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
49#define VM_EXIT_HOST_ADD_SPACE_SIZE 0x00000200
50
51
52/* VMCS Encodings */
53enum vmcs_field {
54 GUEST_ES_SELECTOR = 0x00000800,
55 GUEST_CS_SELECTOR = 0x00000802,
56 GUEST_SS_SELECTOR = 0x00000804,
57 GUEST_DS_SELECTOR = 0x00000806,
58 GUEST_FS_SELECTOR = 0x00000808,
59 GUEST_GS_SELECTOR = 0x0000080a,
60 GUEST_LDTR_SELECTOR = 0x0000080c,
61 GUEST_TR_SELECTOR = 0x0000080e,
62 HOST_ES_SELECTOR = 0x00000c00,
63 HOST_CS_SELECTOR = 0x00000c02,
64 HOST_SS_SELECTOR = 0x00000c04,
65 HOST_DS_SELECTOR = 0x00000c06,
66 HOST_FS_SELECTOR = 0x00000c08,
67 HOST_GS_SELECTOR = 0x00000c0a,
68 HOST_TR_SELECTOR = 0x00000c0c,
69 IO_BITMAP_A = 0x00002000,
70 IO_BITMAP_A_HIGH = 0x00002001,
71 IO_BITMAP_B = 0x00002002,
72 IO_BITMAP_B_HIGH = 0x00002003,
73 MSR_BITMAP = 0x00002004,
74 MSR_BITMAP_HIGH = 0x00002005,
75 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
76 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
77 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
78 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
79 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
80 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
81 TSC_OFFSET = 0x00002010,
82 TSC_OFFSET_HIGH = 0x00002011,
83 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
84 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
85 VMCS_LINK_POINTER = 0x00002800,
86 VMCS_LINK_POINTER_HIGH = 0x00002801,
87 GUEST_IA32_DEBUGCTL = 0x00002802,
88 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
89 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
90 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
91 EXCEPTION_BITMAP = 0x00004004,
92 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
93 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
94 CR3_TARGET_COUNT = 0x0000400a,
95 VM_EXIT_CONTROLS = 0x0000400c,
96 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
97 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
98 VM_ENTRY_CONTROLS = 0x00004012,
99 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
100 VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
101 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
102 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
103 TPR_THRESHOLD = 0x0000401c,
104 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
105 VM_INSTRUCTION_ERROR = 0x00004400,
106 VM_EXIT_REASON = 0x00004402,
107 VM_EXIT_INTR_INFO = 0x00004404,
108 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
109 IDT_VECTORING_INFO_FIELD = 0x00004408,
110 IDT_VECTORING_ERROR_CODE = 0x0000440a,
111 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
112 VMX_INSTRUCTION_INFO = 0x0000440e,
113 GUEST_ES_LIMIT = 0x00004800,
114 GUEST_CS_LIMIT = 0x00004802,
115 GUEST_SS_LIMIT = 0x00004804,
116 GUEST_DS_LIMIT = 0x00004806,
117 GUEST_FS_LIMIT = 0x00004808,
118 GUEST_GS_LIMIT = 0x0000480a,
119 GUEST_LDTR_LIMIT = 0x0000480c,
120 GUEST_TR_LIMIT = 0x0000480e,
121 GUEST_GDTR_LIMIT = 0x00004810,
122 GUEST_IDTR_LIMIT = 0x00004812,
123 GUEST_ES_AR_BYTES = 0x00004814,
124 GUEST_CS_AR_BYTES = 0x00004816,
125 GUEST_SS_AR_BYTES = 0x00004818,
126 GUEST_DS_AR_BYTES = 0x0000481a,
127 GUEST_FS_AR_BYTES = 0x0000481c,
128 GUEST_GS_AR_BYTES = 0x0000481e,
129 GUEST_LDTR_AR_BYTES = 0x00004820,
130 GUEST_TR_AR_BYTES = 0x00004822,
131 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
132 GUEST_ACTIVITY_STATE = 0X00004826,
133 GUEST_SYSENTER_CS = 0x0000482A,
134 HOST_IA32_SYSENTER_CS = 0x00004c00,
135 CR0_GUEST_HOST_MASK = 0x00006000,
136 CR4_GUEST_HOST_MASK = 0x00006002,
137 CR0_READ_SHADOW = 0x00006004,
138 CR4_READ_SHADOW = 0x00006006,
139 CR3_TARGET_VALUE0 = 0x00006008,
140 CR3_TARGET_VALUE1 = 0x0000600a,
141 CR3_TARGET_VALUE2 = 0x0000600c,
142 CR3_TARGET_VALUE3 = 0x0000600e,
143 EXIT_QUALIFICATION = 0x00006400,
144 GUEST_LINEAR_ADDRESS = 0x0000640a,
145 GUEST_CR0 = 0x00006800,
146 GUEST_CR3 = 0x00006802,
147 GUEST_CR4 = 0x00006804,
148 GUEST_ES_BASE = 0x00006806,
149 GUEST_CS_BASE = 0x00006808,
150 GUEST_SS_BASE = 0x0000680a,
151 GUEST_DS_BASE = 0x0000680c,
152 GUEST_FS_BASE = 0x0000680e,
153 GUEST_GS_BASE = 0x00006810,
154 GUEST_LDTR_BASE = 0x00006812,
155 GUEST_TR_BASE = 0x00006814,
156 GUEST_GDTR_BASE = 0x00006816,
157 GUEST_IDTR_BASE = 0x00006818,
158 GUEST_DR7 = 0x0000681a,
159 GUEST_RSP = 0x0000681c,
160 GUEST_RIP = 0x0000681e,
161 GUEST_RFLAGS = 0x00006820,
162 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
163 GUEST_SYSENTER_ESP = 0x00006824,
164 GUEST_SYSENTER_EIP = 0x00006826,
165 HOST_CR0 = 0x00006c00,
166 HOST_CR3 = 0x00006c02,
167 HOST_CR4 = 0x00006c04,
168 HOST_FS_BASE = 0x00006c06,
169 HOST_GS_BASE = 0x00006c08,
170 HOST_TR_BASE = 0x00006c0a,
171 HOST_GDTR_BASE = 0x00006c0c,
172 HOST_IDTR_BASE = 0x00006c0e,
173 HOST_IA32_SYSENTER_ESP = 0x00006c10,
174 HOST_IA32_SYSENTER_EIP = 0x00006c12,
175 HOST_RSP = 0x00006c14,
176 HOST_RIP = 0x00006c16,
177};
178
179#define VMX_EXIT_REASONS_FAILED_VMENTRY 0x80000000
180
181#define EXIT_REASON_EXCEPTION_NMI 0
182#define EXIT_REASON_EXTERNAL_INTERRUPT 1
183
184#define EXIT_REASON_PENDING_INTERRUPT 7
185
186#define EXIT_REASON_TASK_SWITCH 9
187#define EXIT_REASON_CPUID 10
188#define EXIT_REASON_HLT 12
189#define EXIT_REASON_INVLPG 14
190#define EXIT_REASON_RDPMC 15
191#define EXIT_REASON_RDTSC 16
192#define EXIT_REASON_VMCALL 18
193#define EXIT_REASON_VMCLEAR 19
194#define EXIT_REASON_VMLAUNCH 20
195#define EXIT_REASON_VMPTRLD 21
196#define EXIT_REASON_VMPTRST 22
197#define EXIT_REASON_VMREAD 23
198#define EXIT_REASON_VMRESUME 24
199#define EXIT_REASON_VMWRITE 25
200#define EXIT_REASON_VMOFF 26
201#define EXIT_REASON_VMON 27
202#define EXIT_REASON_CR_ACCESS 28
203#define EXIT_REASON_DR_ACCESS 29
204#define EXIT_REASON_IO_INSTRUCTION 30
205#define EXIT_REASON_MSR_READ 31
206#define EXIT_REASON_MSR_WRITE 32
207#define EXIT_REASON_MWAIT_INSTRUCTION 36
208
209/*
210 * Interruption-information format
211 */
212#define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
213#define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
214#define INTR_INFO_DELIEVER_CODE_MASK 0x800 /* 11 */
215#define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
216
217#define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK
218#define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK
219#define VECTORING_INFO_DELIEVER_CODE_MASK INTR_INFO_DELIEVER_CODE_MASK
220#define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK
221
222#define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */
223#define INTR_TYPE_EXCEPTION (3 << 8) /* processor exception */
224
225/*
226 * Exit Qualifications for MOV for Control Register Access
227 */
228#define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control register */
229#define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
230#define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose register */
231#define LMSW_SOURCE_DATA_SHIFT 16
232#define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
233#define REG_EAX (0 << 8)
234#define REG_ECX (1 << 8)
235#define REG_EDX (2 << 8)
236#define REG_EBX (3 << 8)
237#define REG_ESP (4 << 8)
238#define REG_EBP (5 << 8)
239#define REG_ESI (6 << 8)
240#define REG_EDI (7 << 8)
241#define REG_R8 (8 << 8)
242#define REG_R9 (9 << 8)
243#define REG_R10 (10 << 8)
244#define REG_R11 (11 << 8)
245#define REG_R12 (12 << 8)
246#define REG_R13 (13 << 8)
247#define REG_R14 (14 << 8)
248#define REG_R15 (15 << 8)
249
250/*
251 * Exit Qualifications for MOV for Debug Register Access
252 */
253#define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug register */
254#define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
255#define TYPE_MOV_TO_DR (0 << 4)
256#define TYPE_MOV_FROM_DR (1 << 4)
257#define DEBUG_REG_ACCESS_REG 0xf00 /* 11:8, general purpose register */
258
259
260/* segment AR */
261#define SEGMENT_AR_L_MASK (1 << 13)
262
263/* entry controls */
264#define VM_ENTRY_CONTROLS_IA32E_MASK (1 << 9)
265
266#define AR_TYPE_ACCESSES_MASK 1
267#define AR_TYPE_READABLE_MASK (1 << 1)
268#define AR_TYPE_WRITEABLE_MASK (1 << 2)
269#define AR_TYPE_CODE_MASK (1 << 3)
270#define AR_TYPE_MASK 0x0f
271#define AR_TYPE_BUSY_64_TSS 11
272#define AR_TYPE_BUSY_32_TSS 11
273#define AR_TYPE_BUSY_16_TSS 3
274#define AR_TYPE_LDT 2
275
276#define AR_UNUSABLE_MASK (1 << 16)
277#define AR_S_MASK (1 << 4)
278#define AR_P_MASK (1 << 7)
279#define AR_L_MASK (1 << 13)
280#define AR_DB_MASK (1 << 14)
281#define AR_G_MASK (1 << 15)
282#define AR_DPL_SHIFT 5
283#define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
284
285#define AR_RESERVD_MASK 0xfffe0f00
286
287#define CR4_VMXE 0x2000
288
289#define MSR_IA32_VMX_BASIC_MSR 0x480
290#define MSR_IA32_FEATURE_CONTROL 0x03a
291#define MSR_IA32_VMX_PINBASED_CTLS_MSR 0x481
292#define MSR_IA32_VMX_PROCBASED_CTLS_MSR 0x482
293#define MSR_IA32_VMX_EXIT_CTLS_MSR 0x483
294#define MSR_IA32_VMX_ENTRY_CTLS_MSR 0x484
295
296#endif