Linux kernel mirror (for testing)
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linux
1#ifndef _M68K_SYSTEM_H
2#define _M68K_SYSTEM_H
3
4#include <linux/linkage.h>
5#include <linux/kernel.h>
6#include <asm/segment.h>
7#include <asm/entry.h>
8
9#ifdef __KERNEL__
10
11/*
12 * switch_to(n) should switch tasks to task ptr, first checking that
13 * ptr isn't the current task, in which case it does nothing. This
14 * also clears the TS-flag if the task we switched to has used the
15 * math co-processor latest.
16 */
17/*
18 * switch_to() saves the extra registers, that are not saved
19 * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
20 * a0-a1. Some of these are used by schedule() and its predecessors
21 * and so we might get see unexpected behaviors when a task returns
22 * with unexpected register values.
23 *
24 * syscall stores these registers itself and none of them are used
25 * by syscall after the function in the syscall has been called.
26 *
27 * Beware that resume now expects *next to be in d1 and the offset of
28 * tss to be in a1. This saves a few instructions as we no longer have
29 * to push them onto the stack and read them back right after.
30 *
31 * 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
32 *
33 * Changed 96/09/19 by Andreas Schwab
34 * pass prev in a0, next in a1
35 */
36asmlinkage void resume(void);
37#define switch_to(prev,next,last) do { \
38 register void *_prev __asm__ ("a0") = (prev); \
39 register void *_next __asm__ ("a1") = (next); \
40 register void *_last __asm__ ("d1"); \
41 __asm__ __volatile__("jbsr resume" \
42 : "=a" (_prev), "=a" (_next), "=d" (_last) \
43 : "0" (_prev), "1" (_next) \
44 : "d0", "d2", "d3", "d4", "d5"); \
45 (last) = _last; \
46} while (0)
47
48
49/* interrupt control.. */
50#if 0
51#define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory")
52#else
53#include <linux/hardirq.h>
54#define local_irq_enable() ({ \
55 if (MACH_IS_Q40 || !hardirq_count()) \
56 asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory"); \
57})
58#endif
59#define local_irq_disable() asm volatile ("oriw #0x0700,%%sr": : : "memory")
60#define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory")
61#define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory")
62
63static inline int irqs_disabled(void)
64{
65 unsigned long flags;
66 local_save_flags(flags);
67 return flags & ~ALLOWINT;
68}
69
70/* For spinlocks etc */
71#define local_irq_save(x) ({ local_save_flags(x); local_irq_disable(); })
72
73/*
74 * Force strict CPU ordering.
75 * Not really required on m68k...
76 */
77#define nop() do { asm volatile ("nop"); barrier(); } while (0)
78#define mb() barrier()
79#define rmb() barrier()
80#define wmb() barrier()
81#define read_barrier_depends() ((void)0)
82#define set_mb(var, value) ({ (var) = (value); wmb(); })
83
84#define smp_mb() barrier()
85#define smp_rmb() barrier()
86#define smp_wmb() barrier()
87#define smp_read_barrier_depends() ((void)0)
88
89
90#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
91#define tas(ptr) (xchg((ptr),1))
92
93struct __xchg_dummy { unsigned long a[100]; };
94#define __xg(x) ((volatile struct __xchg_dummy *)(x))
95
96#ifndef CONFIG_RMW_INSNS
97static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
98{
99 unsigned long flags, tmp;
100
101 local_irq_save(flags);
102
103 switch (size) {
104 case 1:
105 tmp = *(u8 *)ptr;
106 *(u8 *)ptr = x;
107 x = tmp;
108 break;
109 case 2:
110 tmp = *(u16 *)ptr;
111 *(u16 *)ptr = x;
112 x = tmp;
113 break;
114 case 4:
115 tmp = *(u32 *)ptr;
116 *(u32 *)ptr = x;
117 x = tmp;
118 break;
119 default:
120 BUG();
121 }
122
123 local_irq_restore(flags);
124 return x;
125}
126#else
127static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
128{
129 switch (size) {
130 case 1:
131 __asm__ __volatile__
132 ("moveb %2,%0\n\t"
133 "1:\n\t"
134 "casb %0,%1,%2\n\t"
135 "jne 1b"
136 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
137 break;
138 case 2:
139 __asm__ __volatile__
140 ("movew %2,%0\n\t"
141 "1:\n\t"
142 "casw %0,%1,%2\n\t"
143 "jne 1b"
144 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
145 break;
146 case 4:
147 __asm__ __volatile__
148 ("movel %2,%0\n\t"
149 "1:\n\t"
150 "casl %0,%1,%2\n\t"
151 "jne 1b"
152 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
153 break;
154 }
155 return x;
156}
157#endif
158
159/*
160 * Atomic compare and exchange. Compare OLD with MEM, if identical,
161 * store NEW in MEM. Return the initial value in MEM. Success is
162 * indicated by comparing RETURN with OLD.
163 */
164#ifdef CONFIG_RMW_INSNS
165#define __HAVE_ARCH_CMPXCHG 1
166
167static inline unsigned long __cmpxchg(volatile void *p, unsigned long old,
168 unsigned long new, int size)
169{
170 switch (size) {
171 case 1:
172 __asm__ __volatile__ ("casb %0,%2,%1"
173 : "=d" (old), "=m" (*(char *)p)
174 : "d" (new), "0" (old), "m" (*(char *)p));
175 break;
176 case 2:
177 __asm__ __volatile__ ("casw %0,%2,%1"
178 : "=d" (old), "=m" (*(short *)p)
179 : "d" (new), "0" (old), "m" (*(short *)p));
180 break;
181 case 4:
182 __asm__ __volatile__ ("casl %0,%2,%1"
183 : "=d" (old), "=m" (*(int *)p)
184 : "d" (new), "0" (old), "m" (*(int *)p));
185 break;
186 }
187 return old;
188}
189
190#define cmpxchg(ptr,o,n)\
191 ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
192 (unsigned long)(n),sizeof(*(ptr))))
193#endif
194
195#define arch_align_stack(x) (x)
196
197#endif /* __KERNEL__ */
198
199#endif /* _M68K_SYSTEM_H */