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1/*
2 * include/asm-i386/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
6
7#ifndef __ASM_I386_PROCESSOR_H
8#define __ASM_I386_PROCESSOR_H
9
10#include <asm/vm86.h>
11#include <asm/math_emu.h>
12#include <asm/segment.h>
13#include <asm/page.h>
14#include <asm/types.h>
15#include <asm/sigcontext.h>
16#include <asm/cpufeature.h>
17#include <asm/msr.h>
18#include <asm/system.h>
19#include <linux/cache.h>
20#include <linux/threads.h>
21#include <asm/percpu.h>
22#include <linux/cpumask.h>
23
24/* flag for disabling the tsc */
25extern int tsc_disable;
26
27struct desc_struct {
28 unsigned long a,b;
29};
30
31#define desc_empty(desc) \
32 (!((desc)->a | (desc)->b))
33
34#define desc_equal(desc1, desc2) \
35 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
36/*
37 * Default implementation of macro that returns current
38 * instruction pointer ("program counter").
39 */
40#define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
41
42/*
43 * CPU type and hardware bug flags. Kept separately for each CPU.
44 * Members of this structure are referenced in head.S, so think twice
45 * before touching them. [mj]
46 */
47
48struct cpuinfo_x86 {
49 __u8 x86; /* CPU family */
50 __u8 x86_vendor; /* CPU vendor */
51 __u8 x86_model;
52 __u8 x86_mask;
53 char wp_works_ok; /* It doesn't on 386's */
54 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
55 char hard_math;
56 char rfu;
57 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
58 unsigned long x86_capability[NCAPINTS];
59 char x86_vendor_id[16];
60 char x86_model_id[64];
61 int x86_cache_size; /* in KB - valid for CPUS which support this
62 call */
63 int x86_cache_alignment; /* In bytes */
64 char fdiv_bug;
65 char f00f_bug;
66 char coma_bug;
67 char pad0;
68 int x86_power;
69 unsigned long loops_per_jiffy;
70#ifdef CONFIG_SMP
71 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
72#endif
73 unsigned char x86_max_cores; /* cpuid returned max cores value */
74 unsigned char apicid;
75#ifdef CONFIG_SMP
76 unsigned char booted_cores; /* number of cores as seen by OS */
77 __u8 phys_proc_id; /* Physical processor id. */
78 __u8 cpu_core_id; /* Core id */
79#endif
80} __attribute__((__aligned__(SMP_CACHE_BYTES)));
81
82#define X86_VENDOR_INTEL 0
83#define X86_VENDOR_CYRIX 1
84#define X86_VENDOR_AMD 2
85#define X86_VENDOR_UMC 3
86#define X86_VENDOR_NEXGEN 4
87#define X86_VENDOR_CENTAUR 5
88#define X86_VENDOR_RISE 6
89#define X86_VENDOR_TRANSMETA 7
90#define X86_VENDOR_NSC 8
91#define X86_VENDOR_NUM 9
92#define X86_VENDOR_UNKNOWN 0xff
93
94/*
95 * capabilities of CPUs
96 */
97
98extern struct cpuinfo_x86 boot_cpu_data;
99extern struct cpuinfo_x86 new_cpu_data;
100extern struct tss_struct doublefault_tss;
101DECLARE_PER_CPU(struct tss_struct, init_tss);
102
103#ifdef CONFIG_SMP
104extern struct cpuinfo_x86 cpu_data[];
105#define current_cpu_data cpu_data[smp_processor_id()]
106#else
107#define cpu_data (&boot_cpu_data)
108#define current_cpu_data boot_cpu_data
109#endif
110
111extern int cpu_llc_id[NR_CPUS];
112extern char ignore_fpu_irq;
113
114extern void identify_cpu(struct cpuinfo_x86 *);
115extern void print_cpu_info(struct cpuinfo_x86 *);
116extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
117extern unsigned short num_cache_leaves;
118
119#ifdef CONFIG_X86_HT
120extern void detect_ht(struct cpuinfo_x86 *c);
121#else
122static inline void detect_ht(struct cpuinfo_x86 *c) {}
123#endif
124
125/*
126 * EFLAGS bits
127 */
128#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
129#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
130#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
131#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
132#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
133#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
134#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
135#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
136#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
137#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
138#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
139#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
140#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
141#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
142#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
143#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
144#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
145
146static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
147 unsigned int *ecx, unsigned int *edx)
148{
149 /* ecx is often an input as well as an output. */
150 __asm__("cpuid"
151 : "=a" (*eax),
152 "=b" (*ebx),
153 "=c" (*ecx),
154 "=d" (*edx)
155 : "0" (*eax), "2" (*ecx));
156}
157
158/*
159 * Generic CPUID function
160 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
161 * resulting in stale register contents being returned.
162 */
163static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
164{
165 *eax = op;
166 *ecx = 0;
167 __cpuid(eax, ebx, ecx, edx);
168}
169
170/* Some CPUID calls want 'count' to be placed in ecx */
171static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
172 int *edx)
173{
174 *eax = op;
175 *ecx = count;
176 __cpuid(eax, ebx, ecx, edx);
177}
178
179/*
180 * CPUID functions returning a single datum
181 */
182static inline unsigned int cpuid_eax(unsigned int op)
183{
184 unsigned int eax, ebx, ecx, edx;
185
186 cpuid(op, &eax, &ebx, &ecx, &edx);
187 return eax;
188}
189static inline unsigned int cpuid_ebx(unsigned int op)
190{
191 unsigned int eax, ebx, ecx, edx;
192
193 cpuid(op, &eax, &ebx, &ecx, &edx);
194 return ebx;
195}
196static inline unsigned int cpuid_ecx(unsigned int op)
197{
198 unsigned int eax, ebx, ecx, edx;
199
200 cpuid(op, &eax, &ebx, &ecx, &edx);
201 return ecx;
202}
203static inline unsigned int cpuid_edx(unsigned int op)
204{
205 unsigned int eax, ebx, ecx, edx;
206
207 cpuid(op, &eax, &ebx, &ecx, &edx);
208 return edx;
209}
210
211#define load_cr3(pgdir) write_cr3(__pa(pgdir))
212
213/*
214 * Intel CPU features in CR4
215 */
216#define X86_CR4_VME 0x0001 /* enable vm86 extensions */
217#define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
218#define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
219#define X86_CR4_DE 0x0008 /* enable debugging extensions */
220#define X86_CR4_PSE 0x0010 /* enable page size extensions */
221#define X86_CR4_PAE 0x0020 /* enable physical address extensions */
222#define X86_CR4_MCE 0x0040 /* Machine check enable */
223#define X86_CR4_PGE 0x0080 /* enable global pages */
224#define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
225#define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
226#define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
227
228/*
229 * Save the cr4 feature set we're using (ie
230 * Pentium 4MB enable and PPro Global page
231 * enable), so that any CPU's that boot up
232 * after us can get the correct flags.
233 */
234extern unsigned long mmu_cr4_features;
235
236static inline void set_in_cr4 (unsigned long mask)
237{
238 unsigned cr4;
239 mmu_cr4_features |= mask;
240 cr4 = read_cr4();
241 cr4 |= mask;
242 write_cr4(cr4);
243}
244
245static inline void clear_in_cr4 (unsigned long mask)
246{
247 unsigned cr4;
248 mmu_cr4_features &= ~mask;
249 cr4 = read_cr4();
250 cr4 &= ~mask;
251 write_cr4(cr4);
252}
253
254/*
255 * NSC/Cyrix CPU configuration register indexes
256 */
257
258#define CX86_PCR0 0x20
259#define CX86_GCR 0xb8
260#define CX86_CCR0 0xc0
261#define CX86_CCR1 0xc1
262#define CX86_CCR2 0xc2
263#define CX86_CCR3 0xc3
264#define CX86_CCR4 0xe8
265#define CX86_CCR5 0xe9
266#define CX86_CCR6 0xea
267#define CX86_CCR7 0xeb
268#define CX86_PCR1 0xf0
269#define CX86_DIR0 0xfe
270#define CX86_DIR1 0xff
271#define CX86_ARR_BASE 0xc4
272#define CX86_RCR_BASE 0xdc
273
274/*
275 * NSC/Cyrix CPU indexed register access macros
276 */
277
278#define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
279
280#define setCx86(reg, data) do { \
281 outb((reg), 0x22); \
282 outb((data), 0x23); \
283} while (0)
284
285/* Stop speculative execution */
286static inline void sync_core(void)
287{
288 int tmp;
289 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
290}
291
292static inline void __monitor(const void *eax, unsigned long ecx,
293 unsigned long edx)
294{
295 /* "monitor %eax,%ecx,%edx;" */
296 asm volatile(
297 ".byte 0x0f,0x01,0xc8;"
298 : :"a" (eax), "c" (ecx), "d"(edx));
299}
300
301static inline void __mwait(unsigned long eax, unsigned long ecx)
302{
303 /* "mwait %eax,%ecx;" */
304 asm volatile(
305 ".byte 0x0f,0x01,0xc9;"
306 : :"a" (eax), "c" (ecx));
307}
308
309extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
310
311/* from system description table in BIOS. Mostly for MCA use, but
312others may find it useful. */
313extern unsigned int machine_id;
314extern unsigned int machine_submodel_id;
315extern unsigned int BIOS_revision;
316extern unsigned int mca_pentium_flag;
317
318/* Boot loader type from the setup header */
319extern int bootloader_type;
320
321/*
322 * User space process size: 3GB (default).
323 */
324#define TASK_SIZE (PAGE_OFFSET)
325
326/* This decides where the kernel will search for a free chunk of vm
327 * space during mmap's.
328 */
329#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
330
331#define HAVE_ARCH_PICK_MMAP_LAYOUT
332
333/*
334 * Size of io_bitmap.
335 */
336#define IO_BITMAP_BITS 65536
337#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
338#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
339#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
340#define INVALID_IO_BITMAP_OFFSET 0x8000
341#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
342
343struct i387_fsave_struct {
344 long cwd;
345 long swd;
346 long twd;
347 long fip;
348 long fcs;
349 long foo;
350 long fos;
351 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
352 long status; /* software status information */
353};
354
355struct i387_fxsave_struct {
356 unsigned short cwd;
357 unsigned short swd;
358 unsigned short twd;
359 unsigned short fop;
360 long fip;
361 long fcs;
362 long foo;
363 long fos;
364 long mxcsr;
365 long mxcsr_mask;
366 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
367 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
368 long padding[56];
369} __attribute__ ((aligned (16)));
370
371struct i387_soft_struct {
372 long cwd;
373 long swd;
374 long twd;
375 long fip;
376 long fcs;
377 long foo;
378 long fos;
379 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
380 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
381 struct info *info;
382 unsigned long entry_eip;
383};
384
385union i387_union {
386 struct i387_fsave_struct fsave;
387 struct i387_fxsave_struct fxsave;
388 struct i387_soft_struct soft;
389};
390
391typedef struct {
392 unsigned long seg;
393} mm_segment_t;
394
395struct thread_struct;
396
397struct tss_struct {
398 unsigned short back_link,__blh;
399 unsigned long esp0;
400 unsigned short ss0,__ss0h;
401 unsigned long esp1;
402 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
403 unsigned long esp2;
404 unsigned short ss2,__ss2h;
405 unsigned long __cr3;
406 unsigned long eip;
407 unsigned long eflags;
408 unsigned long eax,ecx,edx,ebx;
409 unsigned long esp;
410 unsigned long ebp;
411 unsigned long esi;
412 unsigned long edi;
413 unsigned short es, __esh;
414 unsigned short cs, __csh;
415 unsigned short ss, __ssh;
416 unsigned short ds, __dsh;
417 unsigned short fs, __fsh;
418 unsigned short gs, __gsh;
419 unsigned short ldt, __ldth;
420 unsigned short trace, io_bitmap_base;
421 /*
422 * The extra 1 is there because the CPU will access an
423 * additional byte beyond the end of the IO permission
424 * bitmap. The extra byte must be all 1 bits, and must
425 * be within the limit.
426 */
427 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
428 /*
429 * Cache the current maximum and the last task that used the bitmap:
430 */
431 unsigned long io_bitmap_max;
432 struct thread_struct *io_bitmap_owner;
433 /*
434 * pads the TSS to be cacheline-aligned (size is 0x100)
435 */
436 unsigned long __cacheline_filler[35];
437 /*
438 * .. and then another 0x100 bytes for emergency kernel stack
439 */
440 unsigned long stack[64];
441} __attribute__((packed));
442
443#define ARCH_MIN_TASKALIGN 16
444
445struct thread_struct {
446/* cached TLS descriptors. */
447 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
448 unsigned long esp0;
449 unsigned long sysenter_cs;
450 unsigned long eip;
451 unsigned long esp;
452 unsigned long fs;
453 unsigned long gs;
454/* Hardware debugging registers */
455 unsigned long debugreg[8]; /* %%db0-7 debug registers */
456/* fault info */
457 unsigned long cr2, trap_no, error_code;
458/* floating point info */
459 union i387_union i387;
460/* virtual 86 mode info */
461 struct vm86_struct __user * vm86_info;
462 unsigned long screen_bitmap;
463 unsigned long v86flags, v86mask, saved_esp0;
464 unsigned int saved_fs, saved_gs;
465/* IO permissions */
466 unsigned long *io_bitmap_ptr;
467 unsigned long iopl;
468/* max allowed port in the bitmap, in bytes: */
469 unsigned long io_bitmap_max;
470};
471
472#define INIT_THREAD { \
473 .vm86_info = NULL, \
474 .sysenter_cs = __KERNEL_CS, \
475 .io_bitmap_ptr = NULL, \
476}
477
478/*
479 * Note that the .io_bitmap member must be extra-big. This is because
480 * the CPU will access an additional byte beyond the end of the IO
481 * permission bitmap. The extra byte must be all 1 bits, and must
482 * be within the limit.
483 */
484#define INIT_TSS { \
485 .esp0 = sizeof(init_stack) + (long)&init_stack, \
486 .ss0 = __KERNEL_DS, \
487 .ss1 = __KERNEL_CS, \
488 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
489 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
490}
491
492static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
493{
494 tss->esp0 = thread->esp0;
495 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
496 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
497 tss->ss1 = thread->sysenter_cs;
498 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
499 }
500}
501
502#define start_thread(regs, new_eip, new_esp) do { \
503 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
504 set_fs(USER_DS); \
505 regs->xds = __USER_DS; \
506 regs->xes = __USER_DS; \
507 regs->xss = __USER_DS; \
508 regs->xcs = __USER_CS; \
509 regs->eip = new_eip; \
510 regs->esp = new_esp; \
511} while (0)
512
513/*
514 * These special macros can be used to get or set a debugging register
515 */
516#define get_debugreg(var, register) \
517 __asm__("movl %%db" #register ", %0" \
518 :"=r" (var))
519#define set_debugreg(value, register) \
520 __asm__("movl %0,%%db" #register \
521 : /* no output */ \
522 :"r" (value))
523
524/*
525 * Set IOPL bits in EFLAGS from given mask
526 */
527static inline void set_iopl_mask(unsigned mask)
528{
529 unsigned int reg;
530 __asm__ __volatile__ ("pushfl;"
531 "popl %0;"
532 "andl %1, %0;"
533 "orl %2, %0;"
534 "pushl %0;"
535 "popfl"
536 : "=&r" (reg)
537 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
538}
539
540/* Forward declaration, a strange C thing */
541struct task_struct;
542struct mm_struct;
543
544/* Free all resources held by a thread. */
545extern void release_thread(struct task_struct *);
546
547/* Prepare to copy thread state - unlazy all lazy status */
548extern void prepare_to_copy(struct task_struct *tsk);
549
550/*
551 * create a kernel thread without removing it from tasklists
552 */
553extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
554
555extern unsigned long thread_saved_pc(struct task_struct *tsk);
556void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack);
557
558unsigned long get_wchan(struct task_struct *p);
559
560#define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
561#define KSTK_TOP(info) \
562({ \
563 unsigned long *__ptr = (unsigned long *)(info); \
564 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
565})
566
567/*
568 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
569 * This is necessary to guarantee that the entire "struct pt_regs"
570 * is accessable even if the CPU haven't stored the SS/ESP registers
571 * on the stack (interrupt gate does not save these registers
572 * when switching to the same priv ring).
573 * Therefore beware: accessing the xss/esp fields of the
574 * "struct pt_regs" is possible, but they may contain the
575 * completely wrong values.
576 */
577#define task_pt_regs(task) \
578({ \
579 struct pt_regs *__regs__; \
580 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
581 __regs__ - 1; \
582})
583
584#define KSTK_EIP(task) (task_pt_regs(task)->eip)
585#define KSTK_ESP(task) (task_pt_regs(task)->esp)
586
587
588struct microcode_header {
589 unsigned int hdrver;
590 unsigned int rev;
591 unsigned int date;
592 unsigned int sig;
593 unsigned int cksum;
594 unsigned int ldrver;
595 unsigned int pf;
596 unsigned int datasize;
597 unsigned int totalsize;
598 unsigned int reserved[3];
599};
600
601struct microcode {
602 struct microcode_header hdr;
603 unsigned int bits[0];
604};
605
606typedef struct microcode microcode_t;
607typedef struct microcode_header microcode_header_t;
608
609/* microcode format is extended from prescott processors */
610struct extended_signature {
611 unsigned int sig;
612 unsigned int pf;
613 unsigned int cksum;
614};
615
616struct extended_sigtable {
617 unsigned int count;
618 unsigned int cksum;
619 unsigned int reserved[3];
620 struct extended_signature sigs[0];
621};
622
623/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
624static inline void rep_nop(void)
625{
626 __asm__ __volatile__("rep;nop": : :"memory");
627}
628
629#define cpu_relax() rep_nop()
630
631/* generic versions from gas */
632#define GENERIC_NOP1 ".byte 0x90\n"
633#define GENERIC_NOP2 ".byte 0x89,0xf6\n"
634#define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
635#define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
636#define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
637#define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
638#define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
639#define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
640
641/* Opteron nops */
642#define K8_NOP1 GENERIC_NOP1
643#define K8_NOP2 ".byte 0x66,0x90\n"
644#define K8_NOP3 ".byte 0x66,0x66,0x90\n"
645#define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
646#define K8_NOP5 K8_NOP3 K8_NOP2
647#define K8_NOP6 K8_NOP3 K8_NOP3
648#define K8_NOP7 K8_NOP4 K8_NOP3
649#define K8_NOP8 K8_NOP4 K8_NOP4
650
651/* K7 nops */
652/* uses eax dependencies (arbitary choice) */
653#define K7_NOP1 GENERIC_NOP1
654#define K7_NOP2 ".byte 0x8b,0xc0\n"
655#define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
656#define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
657#define K7_NOP5 K7_NOP4 ASM_NOP1
658#define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
659#define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
660#define K7_NOP8 K7_NOP7 ASM_NOP1
661
662#ifdef CONFIG_MK8
663#define ASM_NOP1 K8_NOP1
664#define ASM_NOP2 K8_NOP2
665#define ASM_NOP3 K8_NOP3
666#define ASM_NOP4 K8_NOP4
667#define ASM_NOP5 K8_NOP5
668#define ASM_NOP6 K8_NOP6
669#define ASM_NOP7 K8_NOP7
670#define ASM_NOP8 K8_NOP8
671#elif defined(CONFIG_MK7)
672#define ASM_NOP1 K7_NOP1
673#define ASM_NOP2 K7_NOP2
674#define ASM_NOP3 K7_NOP3
675#define ASM_NOP4 K7_NOP4
676#define ASM_NOP5 K7_NOP5
677#define ASM_NOP6 K7_NOP6
678#define ASM_NOP7 K7_NOP7
679#define ASM_NOP8 K7_NOP8
680#else
681#define ASM_NOP1 GENERIC_NOP1
682#define ASM_NOP2 GENERIC_NOP2
683#define ASM_NOP3 GENERIC_NOP3
684#define ASM_NOP4 GENERIC_NOP4
685#define ASM_NOP5 GENERIC_NOP5
686#define ASM_NOP6 GENERIC_NOP6
687#define ASM_NOP7 GENERIC_NOP7
688#define ASM_NOP8 GENERIC_NOP8
689#endif
690
691#define ASM_NOP_MAX 8
692
693/* Prefetch instructions for Pentium III and AMD Athlon */
694/* It's not worth to care about 3dnow! prefetches for the K6
695 because they are microcoded there and very slow.
696 However we don't do prefetches for pre XP Athlons currently
697 That should be fixed. */
698#define ARCH_HAS_PREFETCH
699static inline void prefetch(const void *x)
700{
701 alternative_input(ASM_NOP4,
702 "prefetchnta (%1)",
703 X86_FEATURE_XMM,
704 "r" (x));
705}
706
707#define ARCH_HAS_PREFETCH
708#define ARCH_HAS_PREFETCHW
709#define ARCH_HAS_SPINLOCK_PREFETCH
710
711/* 3dnow! prefetch to get an exclusive cache line. Useful for
712 spinlocks to avoid one state transition in the cache coherency protocol. */
713static inline void prefetchw(const void *x)
714{
715 alternative_input(ASM_NOP4,
716 "prefetchw (%1)",
717 X86_FEATURE_3DNOW,
718 "r" (x));
719}
720#define spin_lock_prefetch(x) prefetchw(x)
721
722extern void select_idle_routine(const struct cpuinfo_x86 *c);
723
724#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
725
726extern unsigned long boot_option_idle_override;
727extern void enable_sep_cpu(void);
728extern int sysenter_setup(void);
729
730#endif /* __ASM_I386_PROCESSOR_H */