tjh.dev
Linux kernel mirror (for testing)
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1/*
2 * wd33c93.h - Linux device driver definitions for the
3 * Commodore Amiga A2091/590 SCSI controller card
4 *
5 * IMPORTANT: This file is for version 1.25 - 09/Jul/1997
6 *
7 * Copyright (c) 1996 John Shifflett, GeoLog Consulting
8 * john@geolog.com
9 * jshiffle@netcom.com
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 */
22#ifndef WD33C93_H
23#define WD33C93_H
24
25
26#define PROC_INTERFACE /* add code for /proc/scsi/wd33c93/xxx interface */
27#ifdef PROC_INTERFACE
28#define PROC_STATISTICS /* add code for keeping various real time stats */
29#endif
30
31#define SYNC_DEBUG /* extra info on sync negotiation printed */
32#define DEBUGGING_ON /* enable command-line debugging bitmask */
33#define DEBUG_DEFAULTS 0 /* default debugging bitmask */
34
35
36#ifdef DEBUGGING_ON
37#define DB(f,a) if (hostdata->args & (f)) a;
38#else
39#define DB(f,a)
40#endif
41
42#define uchar unsigned char
43
44
45/* wd register names */
46#define WD_OWN_ID 0x00
47#define WD_CONTROL 0x01
48#define WD_TIMEOUT_PERIOD 0x02
49#define WD_CDB_1 0x03
50#define WD_CDB_2 0x04
51#define WD_CDB_3 0x05
52#define WD_CDB_4 0x06
53#define WD_CDB_5 0x07
54#define WD_CDB_6 0x08
55#define WD_CDB_7 0x09
56#define WD_CDB_8 0x0a
57#define WD_CDB_9 0x0b
58#define WD_CDB_10 0x0c
59#define WD_CDB_11 0x0d
60#define WD_CDB_12 0x0e
61#define WD_TARGET_LUN 0x0f
62#define WD_COMMAND_PHASE 0x10
63#define WD_SYNCHRONOUS_TRANSFER 0x11
64#define WD_TRANSFER_COUNT_MSB 0x12
65#define WD_TRANSFER_COUNT 0x13
66#define WD_TRANSFER_COUNT_LSB 0x14
67#define WD_DESTINATION_ID 0x15
68#define WD_SOURCE_ID 0x16
69#define WD_SCSI_STATUS 0x17
70#define WD_COMMAND 0x18
71#define WD_DATA 0x19
72#define WD_QUEUE_TAG 0x1a
73#define WD_AUXILIARY_STATUS 0x1f
74
75/* WD commands */
76#define WD_CMD_RESET 0x00
77#define WD_CMD_ABORT 0x01
78#define WD_CMD_ASSERT_ATN 0x02
79#define WD_CMD_NEGATE_ACK 0x03
80#define WD_CMD_DISCONNECT 0x04
81#define WD_CMD_RESELECT 0x05
82#define WD_CMD_SEL_ATN 0x06
83#define WD_CMD_SEL 0x07
84#define WD_CMD_SEL_ATN_XFER 0x08
85#define WD_CMD_SEL_XFER 0x09
86#define WD_CMD_RESEL_RECEIVE 0x0a
87#define WD_CMD_RESEL_SEND 0x0b
88#define WD_CMD_WAIT_SEL_RECEIVE 0x0c
89#define WD_CMD_TRANS_ADDR 0x18
90#define WD_CMD_TRANS_INFO 0x20
91#define WD_CMD_TRANSFER_PAD 0x21
92#define WD_CMD_SBT_MODE 0x80
93
94/* ASR register */
95#define ASR_INT (0x80)
96#define ASR_LCI (0x40)
97#define ASR_BSY (0x20)
98#define ASR_CIP (0x10)
99#define ASR_PE (0x02)
100#define ASR_DBR (0x01)
101
102/* SCSI Bus Phases */
103#define PHS_DATA_OUT 0x00
104#define PHS_DATA_IN 0x01
105#define PHS_COMMAND 0x02
106#define PHS_STATUS 0x03
107#define PHS_MESS_OUT 0x06
108#define PHS_MESS_IN 0x07
109
110/* Command Status Register definitions */
111
112 /* reset state interrupts */
113#define CSR_RESET 0x00
114#define CSR_RESET_AF 0x01
115
116 /* successful completion interrupts */
117#define CSR_RESELECT 0x10
118#define CSR_SELECT 0x11
119#define CSR_SEL_XFER_DONE 0x16
120#define CSR_XFER_DONE 0x18
121
122 /* paused or aborted interrupts */
123#define CSR_MSGIN 0x20
124#define CSR_SDP 0x21
125#define CSR_SEL_ABORT 0x22
126#define CSR_RESEL_ABORT 0x25
127#define CSR_RESEL_ABORT_AM 0x27
128#define CSR_ABORT 0x28
129
130 /* terminated interrupts */
131#define CSR_INVALID 0x40
132#define CSR_UNEXP_DISC 0x41
133#define CSR_TIMEOUT 0x42
134#define CSR_PARITY 0x43
135#define CSR_PARITY_ATN 0x44
136#define CSR_BAD_STATUS 0x45
137#define CSR_UNEXP 0x48
138
139 /* service required interrupts */
140#define CSR_RESEL 0x80
141#define CSR_RESEL_AM 0x81
142#define CSR_DISC 0x85
143#define CSR_SRV_REQ 0x88
144
145 /* Own ID/CDB Size register */
146#define OWNID_EAF 0x08
147#define OWNID_EHP 0x10
148#define OWNID_RAF 0x20
149#define OWNID_FS_8 0x00
150#define OWNID_FS_12 0x40
151#define OWNID_FS_16 0x80
152
153 /* define these so we don't have to change a2091.c, etc. */
154#define WD33C93_FS_8_10 OWNID_FS_8
155#define WD33C93_FS_12_15 OWNID_FS_12
156#define WD33C93_FS_16_20 OWNID_FS_16
157
158 /* Control register */
159#define CTRL_HSP 0x01
160#define CTRL_HA 0x02
161#define CTRL_IDI 0x04
162#define CTRL_EDI 0x08
163#define CTRL_HHP 0x10
164#define CTRL_POLLED 0x00
165#define CTRL_BURST 0x20
166#define CTRL_BUS 0x40
167#define CTRL_DMA 0x80
168
169 /* Timeout Period register */
170#define TIMEOUT_PERIOD_VALUE 20 /* 20 = 200 ms */
171
172 /* Synchronous Transfer Register */
173#define STR_FSS 0x80
174
175 /* Destination ID register */
176#define DSTID_DPD 0x40
177#define DATA_OUT_DIR 0
178#define DATA_IN_DIR 1
179#define DSTID_SCC 0x80
180
181 /* Source ID register */
182#define SRCID_MASK 0x07
183#define SRCID_SIV 0x08
184#define SRCID_DSP 0x20
185#define SRCID_ES 0x40
186#define SRCID_ER 0x80
187
188 /* This is what the 3393 chip looks like to us */
189typedef struct {
190#ifdef CONFIG_WD33C93_PIO
191 unsigned int SASR;
192 unsigned int SCMD;
193#else
194 volatile unsigned char *SASR;
195 volatile unsigned char *SCMD;
196#endif
197} wd33c93_regs;
198
199
200typedef int (*dma_setup_t) (struct scsi_cmnd *SCpnt, int dir_in);
201typedef void (*dma_stop_t) (struct Scsi_Host *instance,
202 struct scsi_cmnd *SCpnt, int status);
203
204
205#define ILLEGAL_STATUS_BYTE 0xff
206
207#define DEFAULT_SX_PER 376 /* (ns) fairly safe */
208#define DEFAULT_SX_OFF 0 /* aka async */
209
210#define OPTIMUM_SX_PER 252 /* (ns) best we can do (mult-of-4) */
211#define OPTIMUM_SX_OFF 12 /* size of wd3393 fifo */
212
213struct sx_period {
214 unsigned int period_ns;
215 uchar reg_value;
216 };
217
218/* FEF: defines for hostdata->dma_buffer_pool */
219
220#define BUF_CHIP_ALLOCED 0
221#define BUF_SCSI_ALLOCED 1
222
223struct WD33C93_hostdata {
224 struct Scsi_Host *next;
225 wd33c93_regs regs;
226 spinlock_t lock;
227 uchar clock_freq;
228 uchar chip; /* what kind of wd33c93? */
229 uchar microcode; /* microcode rev */
230 uchar dma_buffer_pool; /* FEF: buffer from chip_ram? */
231 int dma_dir; /* data transfer dir. */
232 dma_setup_t dma_setup;
233 dma_stop_t dma_stop;
234 unsigned int dma_xfer_mask;
235 uchar *dma_bounce_buffer;
236 unsigned int dma_bounce_len;
237 volatile uchar busy[8]; /* index = target, bit = lun */
238 volatile struct scsi_cmnd *input_Q; /* commands waiting to be started */
239 volatile struct scsi_cmnd *selecting; /* trying to select this command */
240 volatile struct scsi_cmnd *connected; /* currently connected command */
241 volatile struct scsi_cmnd *disconnected_Q;/* commands waiting for reconnect */
242 uchar state; /* what we are currently doing */
243 uchar dma; /* current state of DMA (on/off) */
244 uchar level2; /* extent to which Level-2 commands are used */
245 uchar disconnect; /* disconnect/reselect policy */
246 unsigned int args; /* set from command-line argument */
247 uchar incoming_msg[8]; /* filled during message_in phase */
248 int incoming_ptr; /* mainly used with EXTENDED messages */
249 uchar outgoing_msg[8]; /* send this during next message_out */
250 int outgoing_len; /* length of outgoing message */
251 unsigned int default_sx_per; /* default transfer period for SCSI bus */
252 uchar sync_xfer[8]; /* sync_xfer reg settings per target */
253 uchar sync_stat[8]; /* status of sync negotiation per target */
254 uchar no_sync; /* bitmask: don't do sync on these targets */
255 uchar no_dma; /* set this flag to disable DMA */
256#ifdef PROC_INTERFACE
257 uchar proc; /* bitmask: what's in proc output */
258#ifdef PROC_STATISTICS
259 unsigned long cmd_cnt[8]; /* # of commands issued per target */
260 unsigned long int_cnt; /* # of interrupts serviced */
261 unsigned long pio_cnt; /* # of pio data transfers */
262 unsigned long dma_cnt; /* # of DMA data transfers */
263 unsigned long disc_allowed_cnt[8]; /* # of disconnects allowed per target */
264 unsigned long disc_done_cnt[8]; /* # of disconnects done per target*/
265#endif
266#endif
267 };
268
269
270/* defines for hostdata->chip */
271
272#define C_WD33C93 0
273#define C_WD33C93A 1
274#define C_WD33C93B 2
275#define C_UNKNOWN_CHIP 100
276
277/* defines for hostdata->state */
278
279#define S_UNCONNECTED 0
280#define S_SELECTING 1
281#define S_RUNNING_LEVEL2 2
282#define S_CONNECTED 3
283#define S_PRE_TMP_DISC 4
284#define S_PRE_CMP_DISC 5
285
286/* defines for hostdata->dma */
287
288#define D_DMA_OFF 0
289#define D_DMA_RUNNING 1
290
291/* defines for hostdata->level2 */
292/* NOTE: only the first 3 are implemented so far */
293
294#define L2_NONE 1 /* no combination commands - we get lots of ints */
295#define L2_SELECT 2 /* start with SEL_ATN_XFER, but never resume it */
296#define L2_BASIC 3 /* resume after STATUS ints & RDP messages */
297#define L2_DATA 4 /* resume after DATA_IN/OUT ints */
298#define L2_MOST 5 /* resume after anything except a RESELECT int */
299#define L2_RESELECT 6 /* resume after everything, including RESELECT ints */
300#define L2_ALL 7 /* always resume */
301
302/* defines for hostdata->disconnect */
303
304#define DIS_NEVER 0
305#define DIS_ADAPTIVE 1
306#define DIS_ALWAYS 2
307
308/* defines for hostdata->args */
309
310#define DB_TEST1 1<<0
311#define DB_TEST2 1<<1
312#define DB_QUEUE_COMMAND 1<<2
313#define DB_EXECUTE 1<<3
314#define DB_INTR 1<<4
315#define DB_TRANSFER 1<<5
316#define DB_MASK 0x3f
317
318/* defines for hostdata->sync_stat[] */
319
320#define SS_UNSET 0
321#define SS_FIRST 1
322#define SS_WAITING 2
323#define SS_SET 3
324
325/* defines for hostdata->proc */
326
327#define PR_VERSION 1<<0
328#define PR_INFO 1<<1
329#define PR_STATISTICS 1<<2
330#define PR_CONNECTED 1<<3
331#define PR_INPUTQ 1<<4
332#define PR_DISCQ 1<<5
333#define PR_TEST 1<<6
334#define PR_STOP 1<<7
335
336
337void wd33c93_init (struct Scsi_Host *instance, const wd33c93_regs regs,
338 dma_setup_t setup, dma_stop_t stop, int clock_freq);
339int wd33c93_abort (struct scsi_cmnd *cmd);
340int wd33c93_queuecommand (struct scsi_cmnd *cmd,
341 void (*done)(struct scsi_cmnd *));
342void wd33c93_intr (struct Scsi_Host *instance);
343int wd33c93_proc_info(struct Scsi_Host *, char *, char **, off_t, int, int);
344int wd33c93_host_reset (struct scsi_cmnd *);
345void wd33c93_release(void);
346
347#endif /* WD33C93_H */