tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * linux/drivers/net/ehea/ehea.h
3 *
4 * eHEA ethernet device driver for IBM eServer System p
5 *
6 * (C) Copyright IBM Corp. 2006
7 *
8 * Authors:
9 * Christoph Raisch <raisch@de.ibm.com>
10 * Jan-Bernd Themann <themann@de.ibm.com>
11 * Thomas Klein <tklein@de.ibm.com>
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2, or (at your option)
17 * any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#ifndef __EHEA_H__
30#define __EHEA_H__
31
32#include <linux/module.h>
33#include <linux/ethtool.h>
34#include <linux/vmalloc.h>
35#include <linux/if_vlan.h>
36
37#include <asm/ibmebus.h>
38#include <asm/abs_addr.h>
39#include <asm/io.h>
40
41#define DRV_NAME "ehea"
42#define DRV_VERSION "EHEA_0043"
43
44#define EHEA_MSG_DEFAULT (NETIF_MSG_LINK | NETIF_MSG_TIMER \
45 | NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
46
47#define EHEA_MAX_ENTRIES_RQ1 32767
48#define EHEA_MAX_ENTRIES_RQ2 16383
49#define EHEA_MAX_ENTRIES_RQ3 16383
50#define EHEA_MAX_ENTRIES_SQ 32767
51#define EHEA_MIN_ENTRIES_QP 127
52
53#define EHEA_SMALL_QUEUES
54#define EHEA_NUM_TX_QP 1
55
56#ifdef EHEA_SMALL_QUEUES
57#define EHEA_MAX_CQE_COUNT 1023
58#define EHEA_DEF_ENTRIES_SQ 1023
59#define EHEA_DEF_ENTRIES_RQ1 4095
60#define EHEA_DEF_ENTRIES_RQ2 1023
61#define EHEA_DEF_ENTRIES_RQ3 1023
62#else
63#define EHEA_MAX_CQE_COUNT 4080
64#define EHEA_DEF_ENTRIES_SQ 4080
65#define EHEA_DEF_ENTRIES_RQ1 8160
66#define EHEA_DEF_ENTRIES_RQ2 2040
67#define EHEA_DEF_ENTRIES_RQ3 2040
68#endif
69
70#define EHEA_MAX_ENTRIES_EQ 20
71
72#define EHEA_SG_SQ 2
73#define EHEA_SG_RQ1 1
74#define EHEA_SG_RQ2 0
75#define EHEA_SG_RQ3 0
76
77#define EHEA_MAX_PACKET_SIZE 9022 /* for jumbo frames */
78#define EHEA_RQ2_PKT_SIZE 1522
79#define EHEA_L_PKT_SIZE 256 /* low latency */
80
81#define EHEA_POLL_MAX_RWQE 1000
82
83/* Send completion signaling */
84#define EHEA_SIG_IV_LONG 1
85
86/* Protection Domain Identifier */
87#define EHEA_PD_ID 0xaabcdeff
88
89#define EHEA_RQ2_THRESHOLD 1
90#define EHEA_RQ3_THRESHOLD 9 /* use RQ3 threshold of 1522 bytes */
91
92#define EHEA_SPEED_10G 10000
93#define EHEA_SPEED_1G 1000
94#define EHEA_SPEED_100M 100
95#define EHEA_SPEED_10M 10
96#define EHEA_SPEED_AUTONEG 0
97
98/* Broadcast/Multicast registration types */
99#define EHEA_BCMC_SCOPE_ALL 0x08
100#define EHEA_BCMC_SCOPE_SINGLE 0x00
101#define EHEA_BCMC_MULTICAST 0x04
102#define EHEA_BCMC_BROADCAST 0x00
103#define EHEA_BCMC_UNTAGGED 0x02
104#define EHEA_BCMC_TAGGED 0x00
105#define EHEA_BCMC_VLANID_ALL 0x01
106#define EHEA_BCMC_VLANID_SINGLE 0x00
107
108#define EHEA_CACHE_LINE 128
109
110/* Memory Regions */
111#define EHEA_MR_MAX_TX_PAGES 20
112#define EHEA_MR_TX_DATA_PN 3
113#define EHEA_MR_ACC_CTRL 0x00800000
114#define EHEA_RWQES_PER_MR_RQ2 10
115#define EHEA_RWQES_PER_MR_RQ3 10
116
117#define EHEA_WATCH_DOG_TIMEOUT 10*HZ
118
119/* utility functions */
120
121#define ehea_info(fmt, args...) \
122 printk(KERN_INFO DRV_NAME ": " fmt "\n", ## args)
123
124#define ehea_error(fmt, args...) \
125 printk(KERN_ERR DRV_NAME ": Error in %s: " fmt "\n", __func__, ## args)
126
127#ifdef DEBUG
128#define ehea_debug(fmt, args...) \
129 printk(KERN_DEBUG DRV_NAME ": " fmt, ## args)
130#else
131#define ehea_debug(fmt, args...) do {} while (0)
132#endif
133
134void ehea_dump(void *adr, int len, char *msg);
135
136#define EHEA_BMASK(pos, length) (((pos) << 16) + (length))
137
138#define EHEA_BMASK_IBM(from, to) (((63 - to) << 16) + ((to) - (from) + 1))
139
140#define EHEA_BMASK_SHIFTPOS(mask) (((mask) >> 16) & 0xffff)
141
142#define EHEA_BMASK_MASK(mask) \
143 (0xffffffffffffffffULL >> ((64 - (mask)) & 0xffff))
144
145#define EHEA_BMASK_SET(mask, value) \
146 ((EHEA_BMASK_MASK(mask) & ((u64)(value))) << EHEA_BMASK_SHIFTPOS(mask))
147
148#define EHEA_BMASK_GET(mask, value) \
149 (EHEA_BMASK_MASK(mask) & (((u64)(value)) >> EHEA_BMASK_SHIFTPOS(mask)))
150
151/*
152 * Generic ehea page
153 */
154struct ehea_page {
155 u8 entries[PAGE_SIZE];
156};
157
158/*
159 * Generic queue in linux kernel virtual memory
160 */
161struct hw_queue {
162 u64 current_q_offset; /* current queue entry */
163 struct ehea_page **queue_pages; /* array of pages belonging to queue */
164 u32 qe_size; /* queue entry size */
165 u32 queue_length; /* queue length allocated in bytes */
166 u32 pagesize;
167 u32 toggle_state; /* toggle flag - per page */
168 u32 reserved; /* 64 bit alignment */
169};
170
171/*
172 * For pSeries this is a 64bit memory address where
173 * I/O memory is mapped into CPU address space
174 */
175struct h_epa {
176 void __iomem *addr;
177};
178
179struct h_epa_user {
180 u64 addr;
181};
182
183struct h_epas {
184 struct h_epa kernel; /* kernel space accessible resource,
185 set to 0 if unused */
186 struct h_epa_user user; /* user space accessible resource
187 set to 0 if unused */
188};
189
190struct ehea_qp;
191struct ehea_cq;
192struct ehea_eq;
193struct ehea_port;
194struct ehea_av;
195
196/*
197 * Queue attributes passed to ehea_create_qp()
198 */
199struct ehea_qp_init_attr {
200 /* input parameter */
201 u32 qp_token; /* queue token */
202 u8 low_lat_rq1;
203 u8 signalingtype; /* cqe generation flag */
204 u8 rq_count; /* num of receive queues */
205 u8 eqe_gen; /* eqe generation flag */
206 u16 max_nr_send_wqes; /* max number of send wqes */
207 u16 max_nr_rwqes_rq1; /* max number of receive wqes */
208 u16 max_nr_rwqes_rq2;
209 u16 max_nr_rwqes_rq3;
210 u8 wqe_size_enc_sq;
211 u8 wqe_size_enc_rq1;
212 u8 wqe_size_enc_rq2;
213 u8 wqe_size_enc_rq3;
214 u8 swqe_imm_data_len; /* immediate data length for swqes */
215 u16 port_nr;
216 u16 rq2_threshold;
217 u16 rq3_threshold;
218 u64 send_cq_handle;
219 u64 recv_cq_handle;
220 u64 aff_eq_handle;
221
222 /* output parameter */
223 u32 qp_nr;
224 u16 act_nr_send_wqes;
225 u16 act_nr_rwqes_rq1;
226 u16 act_nr_rwqes_rq2;
227 u16 act_nr_rwqes_rq3;
228 u8 act_wqe_size_enc_sq;
229 u8 act_wqe_size_enc_rq1;
230 u8 act_wqe_size_enc_rq2;
231 u8 act_wqe_size_enc_rq3;
232 u32 nr_sq_pages;
233 u32 nr_rq1_pages;
234 u32 nr_rq2_pages;
235 u32 nr_rq3_pages;
236 u32 liobn_sq;
237 u32 liobn_rq1;
238 u32 liobn_rq2;
239 u32 liobn_rq3;
240};
241
242/*
243 * Event Queue attributes, passed as paramter
244 */
245struct ehea_eq_attr {
246 u32 type;
247 u32 max_nr_of_eqes;
248 u8 eqe_gen; /* generate eqe flag */
249 u64 eq_handle;
250 u32 act_nr_of_eqes;
251 u32 nr_pages;
252 u32 ist1; /* Interrupt service token */
253 u32 ist2;
254 u32 ist3;
255 u32 ist4;
256};
257
258
259/*
260 * Event Queue
261 */
262struct ehea_eq {
263 struct ehea_adapter *adapter;
264 struct hw_queue hw_queue;
265 u64 fw_handle;
266 struct h_epas epas;
267 spinlock_t spinlock;
268 struct ehea_eq_attr attr;
269};
270
271/*
272 * HEA Queues
273 */
274struct ehea_qp {
275 struct ehea_adapter *adapter;
276 u64 fw_handle; /* QP handle for firmware calls */
277 struct hw_queue hw_squeue;
278 struct hw_queue hw_rqueue1;
279 struct hw_queue hw_rqueue2;
280 struct hw_queue hw_rqueue3;
281 struct h_epas epas;
282 struct ehea_qp_init_attr init_attr;
283};
284
285/*
286 * Completion Queue attributes
287 */
288struct ehea_cq_attr {
289 /* input parameter */
290 u32 max_nr_of_cqes;
291 u32 cq_token;
292 u64 eq_handle;
293
294 /* output parameter */
295 u32 act_nr_of_cqes;
296 u32 nr_pages;
297};
298
299/*
300 * Completion Queue
301 */
302struct ehea_cq {
303 struct ehea_adapter *adapter;
304 u64 fw_handle;
305 struct hw_queue hw_queue;
306 struct h_epas epas;
307 struct ehea_cq_attr attr;
308};
309
310/*
311 * Memory Region
312 */
313struct ehea_mr {
314 u64 handle;
315 u64 vaddr;
316 u32 lkey;
317};
318
319/*
320 * Port state information
321 */
322struct port_state {
323 int poll_max_processed;
324 int poll_receive_errors;
325 int ehea_poll;
326 int queue_stopped;
327 int min_swqe_avail;
328 u64 sqc_stop_sum;
329 int pkt_send;
330 int pkt_xmit;
331 int send_tasklet;
332 int nwqe;
333};
334
335#define EHEA_IRQ_NAME_SIZE 20
336
337/*
338 * Queue SKB Array
339 */
340struct ehea_q_skb_arr {
341 struct sk_buff **arr; /* skb array for queue */
342 int len; /* array length */
343 int index; /* array index */
344 int os_skbs; /* rq2/rq3 only: outstanding skbs */
345};
346
347/*
348 * Port resources
349 */
350struct ehea_port_res {
351 struct ehea_mr send_mr; /* send memory region */
352 struct ehea_mr recv_mr; /* receive memory region */
353 spinlock_t xmit_lock;
354 struct ehea_port *port;
355 char int_recv_name[EHEA_IRQ_NAME_SIZE];
356 char int_send_name[EHEA_IRQ_NAME_SIZE];
357 struct ehea_qp *qp;
358 struct ehea_cq *send_cq;
359 struct ehea_cq *recv_cq;
360 struct ehea_eq *send_eq;
361 struct ehea_eq *recv_eq;
362 spinlock_t send_lock;
363 struct ehea_q_skb_arr rq1_skba;
364 struct ehea_q_skb_arr rq2_skba;
365 struct ehea_q_skb_arr rq3_skba;
366 struct ehea_q_skb_arr sq_skba;
367 spinlock_t netif_queue;
368 int queue_stopped;
369 int swqe_refill_th;
370 atomic_t swqe_avail;
371 int swqe_ll_count;
372 int swqe_count;
373 u32 swqe_id_counter;
374 u64 tx_packets;
375 struct tasklet_struct send_comp_task;
376 spinlock_t recv_lock;
377 struct port_state p_state;
378 u64 rx_packets;
379 u32 poll_counter;
380};
381
382
383struct ehea_adapter {
384 u64 handle;
385 u8 num_ports;
386 struct ehea_port *port[16];
387 struct ehea_eq *neq; /* notification event queue */
388 struct workqueue_struct *ehea_wq;
389 struct tasklet_struct neq_tasklet;
390 struct ehea_mr mr;
391 u32 pd; /* protection domain */
392 u64 max_mc_mac; /* max number of multicast mac addresses */
393};
394
395
396struct ehea_mc_list {
397 struct list_head list;
398 u64 macaddr;
399};
400
401#define EHEA_PORT_UP 1
402#define EHEA_PORT_DOWN 0
403#define EHEA_MAX_PORT_RES 16
404struct ehea_port {
405 struct ehea_adapter *adapter; /* adapter that owns this port */
406 struct net_device *netdev;
407 struct net_device_stats stats;
408 struct ehea_port_res port_res[EHEA_MAX_PORT_RES];
409 struct device_node *of_dev_node; /* Open Firmware Device Node */
410 struct ehea_mc_list *mc_list; /* Multicast MAC addresses */
411 struct vlan_group *vgrp;
412 struct ehea_eq *qp_eq;
413 struct work_struct reset_task;
414 struct semaphore port_lock;
415 char int_aff_name[EHEA_IRQ_NAME_SIZE];
416 int allmulti; /* Indicates IFF_ALLMULTI state */
417 int promisc; /* Indicates IFF_PROMISC state */
418 int num_add_tx_qps;
419 int resets;
420 u64 mac_addr;
421 u32 logical_port_id;
422 u32 port_speed;
423 u32 msg_enable;
424 u32 sig_comp_iv;
425 u32 state;
426 u8 full_duplex;
427 u8 autoneg;
428 u8 num_def_qps;
429};
430
431struct port_res_cfg {
432 int max_entries_rcq;
433 int max_entries_scq;
434 int max_entries_sq;
435 int max_entries_rq1;
436 int max_entries_rq2;
437 int max_entries_rq3;
438};
439
440
441void ehea_set_ethtool_ops(struct net_device *netdev);
442int ehea_sense_port_attr(struct ehea_port *port);
443int ehea_set_portspeed(struct ehea_port *port, u32 port_speed);
444
445#endif /* __EHEA_H__ */