tjh.dev
Linux kernel mirror (for testing)
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1/*
2 * Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
3 *
4 * Author: Mark A. Greerinclude/asm-ppc/hawk.h
5 * mgreer@mvista.com
6 *
7 * Modified by Randy Vinson (rvinson@mvista.com)
8 *
9 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14
15#ifndef __PPC_PPLUS_H
16#define __PPC_PPLUS_H
17
18#include <asm/io.h>
19
20/*
21 * Due to limiations imposed by legacy hardware (primaryily IDE controllers),
22 * the PPLUS boards operate using a PReP address map.
23 *
24 * From Processor (physical) -> PCI:
25 * PCI Mem Space: 0xc0000000 - 0xfe000000 -> 0x00000000 - 0x3e000000 (768 MB)
26 * PCI I/O Space: 0x80000000 - 0x90000000 -> 0x00000000 - 0x10000000 (256 MB)
27 * Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
28 *
29 * From PCI -> Processor (physical):
30 * System Memory: 0x80000000 -> 0x00000000
31 */
32
33#define PPLUS_ISA_MEM_BASE PREP_ISA_MEM_BASE
34#define PPLUS_ISA_IO_BASE PREP_ISA_IO_BASE
35
36/* PCI Memory space mapping info */
37#define PPLUS_PCI_MEM_SIZE 0x30000000U
38#define PPLUS_PROC_PCI_MEM_START PPLUS_ISA_MEM_BASE
39#define PPLUS_PROC_PCI_MEM_END (PPLUS_PROC_PCI_MEM_START + \
40 PPLUS_PCI_MEM_SIZE - 1)
41#define PPLUS_PCI_MEM_START 0x00000000U
42#define PPLUS_PCI_MEM_END (PPLUS_PCI_MEM_START + \
43 PPLUS_PCI_MEM_SIZE - 1)
44
45/* PCI I/O space mapping info */
46#define PPLUS_PCI_IO_SIZE 0x10000000U
47#define PPLUS_PROC_PCI_IO_START PPLUS_ISA_IO_BASE
48#define PPLUS_PROC_PCI_IO_END (PPLUS_PROC_PCI_IO_START + \
49 PPLUS_PCI_IO_SIZE - 1)
50#define PPLUS_PCI_IO_START 0x00000000U
51#define PPLUS_PCI_IO_END (PPLUS_PCI_IO_START + \
52 PPLUS_PCI_IO_SIZE - 1)
53/* System memory mapping info */
54#define PPLUS_PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET
55#define PPLUS_PCI_PHY_MEM_OFFSET (PPLUS_ISA_MEM_BASE-PPLUS_PCI_MEM_START)
56
57/* Define base addresses for important sets of registers */
58#define PPLUS_HAWK_SMC_BASE 0xfef80000U
59#define PPLUS_HAWK_PPC_REG_BASE 0xfeff0000U
60#define PPLUS_SYS_CONFIG_REG 0xfef80400U
61#define PPLUS_L2_CONTROL_REG 0x8000081cU
62
63#define PPLUS_VGA_MEM_BASE 0xf0000000U
64
65#endif /* __PPC_PPLUS_H */