tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 Waldorf GMBH
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 * Copyright (C) 2004 Maciej W. Rozycki
11 */
12#ifndef __ASM_CPU_INFO_H
13#define __ASM_CPU_INFO_H
14
15#include <asm/cache.h>
16
17#ifdef CONFIG_SGI_IP27
18#include <asm/sn/types.h>
19#endif
20
21/*
22 * Descriptor for a cache
23 */
24struct cache_desc {
25 unsigned short linesz; /* Size of line in bytes */
26 unsigned short ways; /* Number of ways */
27 unsigned short sets; /* Number of lines per set */
28 unsigned int waysize; /* Bytes per way */
29 unsigned int waybit; /* Bits to select in a cache set */
30 unsigned int flags; /* Flags describing cache properties */
31};
32
33/*
34 * Flag definitions
35 */
36#define MIPS_CACHE_NOT_PRESENT 0x00000001
37#define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
38#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
39#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
40#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
41#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
42
43struct cpuinfo_mips {
44 unsigned long udelay_val;
45 unsigned long asid_cache;
46#if defined(CONFIG_SGI_IP27)
47// cpuid_t p_cpuid; /* PROM assigned cpuid */
48 cnodeid_t p_nodeid; /* my node ID in compact-id-space */
49 nasid_t p_nasid; /* my node ID in numa-as-id-space */
50 unsigned char p_slice; /* Physical position on node board */
51#endif
52#if 0
53 unsigned long loops_per_sec;
54 unsigned long ipi_count;
55 unsigned long irq_attempt[NR_IRQS];
56 unsigned long smp_local_irq_count;
57 unsigned long prof_multiplier;
58 unsigned long prof_counter;
59#endif
60
61 /*
62 * Capability and feature descriptor structure for MIPS CPU
63 */
64 unsigned long options;
65 unsigned long ases;
66 unsigned int processor_id;
67 unsigned int fpu_id;
68 unsigned int cputype;
69 int isa_level;
70 int tlbsize;
71 struct cache_desc icache; /* Primary I-cache */
72 struct cache_desc dcache; /* Primary D or combined I/D cache */
73 struct cache_desc scache; /* Secondary cache */
74 struct cache_desc tcache; /* Tertiary/split secondary cache */
75#if defined(CONFIG_MIPS_MT_SMTC)
76 /*
77 * In the MIPS MT "SMTC" model, each TC is considered
78 * to be a "CPU" for the purposes of scheduling, but
79 * exception resources, ASID spaces, etc, are common
80 * to all TCs within the same VPE.
81 */
82 int vpe_id; /* Virtual Processor number */
83 int tc_id; /* Thread Context number */
84#endif /* CONFIG_MIPS_MT */
85 void *data; /* Additional data */
86} __attribute__((aligned(SMP_CACHE_BYTES)));
87
88extern struct cpuinfo_mips cpu_data[];
89#define current_cpu_data cpu_data[smp_processor_id()]
90
91extern void cpu_probe(void);
92extern void cpu_report(void);
93
94#endif /* __ASM_CPU_INFO_H */