tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * include/asm-ppc/mpc85xx.h
3 *
4 * MPC85xx definitions
5 *
6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 *
8 * Copyright 2004 Freescale Semiconductor, Inc
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#ifdef __KERNEL__
17#ifndef __ASM_MPC85xx_H__
18#define __ASM_MPC85xx_H__
19
20#include <asm/mmu.h>
21
22#ifdef CONFIG_85xx
23
24#ifdef CONFIG_MPC8540_ADS
25#include <platforms/85xx/mpc8540_ads.h>
26#endif
27#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
28#include <platforms/85xx/mpc8555_cds.h>
29#endif
30#ifdef CONFIG_MPC85xx_CDS
31#include <platforms/85xx/mpc85xx_cds.h>
32#endif
33#ifdef CONFIG_MPC8560_ADS
34#include <platforms/85xx/mpc8560_ads.h>
35#endif
36#ifdef CONFIG_SBC8560
37#include <platforms/85xx/sbc8560.h>
38#endif
39#ifdef CONFIG_STX_GP3
40#include <platforms/85xx/stx_gp3.h>
41#endif
42#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8541) || \
43 defined(CONFIG_TQM8555) || defined(CONFIG_TQM8560)
44#include <platforms/85xx/tqm85xx.h>
45#endif
46
47#define _IO_BASE isa_io_base
48#define _ISA_MEM_BASE isa_mem_base
49#ifdef CONFIG_PCI
50#define PCI_DRAM_OFFSET pci_dram_offset
51#else
52#define PCI_DRAM_OFFSET 0
53#endif
54
55/*
56 * The "residual" board information structure the boot loader passes
57 * into the kernel.
58 */
59extern unsigned char __res[];
60
61/* Offset from CCSRBAR */
62#define MPC85xx_CPM_OFFSET (0x80000)
63#define MPC85xx_CPM_SIZE (0x40000)
64#define MPC85xx_DMA_OFFSET (0x21000)
65#define MPC85xx_DMA_SIZE (0x01000)
66#define MPC85xx_DMA0_OFFSET (0x21100)
67#define MPC85xx_DMA0_SIZE (0x00080)
68#define MPC85xx_DMA1_OFFSET (0x21180)
69#define MPC85xx_DMA1_SIZE (0x00080)
70#define MPC85xx_DMA2_OFFSET (0x21200)
71#define MPC85xx_DMA2_SIZE (0x00080)
72#define MPC85xx_DMA3_OFFSET (0x21280)
73#define MPC85xx_DMA3_SIZE (0x00080)
74#define MPC85xx_ENET1_OFFSET (0x24000)
75#define MPC85xx_ENET1_SIZE (0x01000)
76#define MPC85xx_MIIM_OFFSET (0x24520)
77#define MPC85xx_MIIM_SIZE (0x00018)
78#define MPC85xx_ENET2_OFFSET (0x25000)
79#define MPC85xx_ENET2_SIZE (0x01000)
80#define MPC85xx_ENET3_OFFSET (0x26000)
81#define MPC85xx_ENET3_SIZE (0x01000)
82#define MPC85xx_GUTS_OFFSET (0xe0000)
83#define MPC85xx_GUTS_SIZE (0x01000)
84#define MPC85xx_IIC1_OFFSET (0x03000)
85#define MPC85xx_IIC1_SIZE (0x00100)
86#define MPC85xx_OPENPIC_OFFSET (0x40000)
87#define MPC85xx_OPENPIC_SIZE (0x40000)
88#define MPC85xx_PCI1_OFFSET (0x08000)
89#define MPC85xx_PCI1_SIZE (0x01000)
90#define MPC85xx_PCI2_OFFSET (0x09000)
91#define MPC85xx_PCI2_SIZE (0x01000)
92#define MPC85xx_PERFMON_OFFSET (0xe1000)
93#define MPC85xx_PERFMON_SIZE (0x01000)
94#define MPC85xx_SEC2_OFFSET (0x30000)
95#define MPC85xx_SEC2_SIZE (0x10000)
96#define MPC85xx_UART0_OFFSET (0x04500)
97#define MPC85xx_UART0_SIZE (0x00100)
98#define MPC85xx_UART1_OFFSET (0x04600)
99#define MPC85xx_UART1_SIZE (0x00100)
100
101#define MPC85xx_CCSRBAR_SIZE (1024*1024)
102
103/* Let modules/drivers get at CCSRBAR */
104extern phys_addr_t get_ccsrbar(void);
105
106#ifdef MODULE
107#define CCSRBAR get_ccsrbar()
108#else
109#define CCSRBAR BOARD_CCSRBAR
110#endif
111
112enum ppc_sys_devices {
113 MPC85xx_TSEC1,
114 MPC85xx_TSEC2,
115 MPC85xx_FEC,
116 MPC85xx_IIC1,
117 MPC85xx_DMA0,
118 MPC85xx_DMA1,
119 MPC85xx_DMA2,
120 MPC85xx_DMA3,
121 MPC85xx_DUART,
122 MPC85xx_PERFMON,
123 MPC85xx_SEC2,
124 MPC85xx_CPM_SPI,
125 MPC85xx_CPM_I2C,
126 MPC85xx_CPM_USB,
127 MPC85xx_CPM_SCC1,
128 MPC85xx_CPM_SCC2,
129 MPC85xx_CPM_SCC3,
130 MPC85xx_CPM_SCC4,
131 MPC85xx_CPM_FCC1,
132 MPC85xx_CPM_FCC2,
133 MPC85xx_CPM_FCC3,
134 MPC85xx_CPM_MCC1,
135 MPC85xx_CPM_MCC2,
136 MPC85xx_CPM_SMC1,
137 MPC85xx_CPM_SMC2,
138 MPC85xx_eTSEC1,
139 MPC85xx_eTSEC2,
140 MPC85xx_eTSEC3,
141 MPC85xx_eTSEC4,
142 MPC85xx_IIC2,
143 MPC85xx_MDIO,
144 NUM_PPC_SYS_DEVS,
145};
146
147/* Internal interrupts are all Level Sensitive, and Positive Polarity */
148#define MPC85XX_INTERNAL_IRQ_SENSES \
149 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0 */ \
150 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1 */ \
151 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2 */ \
152 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3 */ \
153 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4 */ \
154 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5 */ \
155 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6 */ \
156 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7 */ \
157 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8 */ \
158 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9 */ \
159 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10 */ \
160 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11 */ \
161 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12 */ \
162 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13 */ \
163 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14 */ \
164 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15 */ \
165 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16 */ \
166 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17 */ \
167 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18 */ \
168 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19 */ \
169 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20 */ \
170 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21 */ \
171 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22 */ \
172 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23 */ \
173 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24 */ \
174 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25 */ \
175 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26 */ \
176 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27 */ \
177 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28 */ \
178 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29 */ \
179 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30 */ \
180 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31 */ \
181 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32 */ \
182 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33 */ \
183 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34 */ \
184 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35 */ \
185 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36 */ \
186 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37 */ \
187 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38 */ \
188 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39 */ \
189 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40 */ \
190 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41 */ \
191 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42 */ \
192 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43 */ \
193 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44 */ \
194 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45 */ \
195 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46 */ \
196 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE) /* Internal 47 */
197
198#endif /* CONFIG_85xx */
199#endif /* __ASM_MPC85xx_H__ */
200#endif /* __KERNEL__ */