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1/* 2 * File: mca.h 3 * Purpose: Machine check handling specific defines 4 * 5 * Copyright (C) 1999, 2004 Silicon Graphics, Inc. 6 * Copyright (C) Vijay Chander (vijay@engr.sgi.com) 7 * Copyright (C) Srinivasa Thirumalachar (sprasad@engr.sgi.com) 8 * Copyright (C) Russ Anderson (rja@sgi.com) 9 */ 10 11#ifndef _ASM_IA64_MCA_H 12#define _ASM_IA64_MCA_H 13 14#if !defined(__ASSEMBLY__) 15 16#include <linux/interrupt.h> 17#include <linux/types.h> 18 19#include <asm/param.h> 20#include <asm/sal.h> 21#include <asm/processor.h> 22#include <asm/mca_asm.h> 23 24#define IA64_MCA_RENDEZ_TIMEOUT (20 * 1000) /* value in milliseconds - 20 seconds */ 25 26typedef struct ia64_fptr { 27 unsigned long fp; 28 unsigned long gp; 29} ia64_fptr_t; 30 31typedef union cmcv_reg_u { 32 u64 cmcv_regval; 33 struct { 34 u64 cmcr_vector : 8; 35 u64 cmcr_reserved1 : 4; 36 u64 cmcr_ignored1 : 1; 37 u64 cmcr_reserved2 : 3; 38 u64 cmcr_mask : 1; 39 u64 cmcr_ignored2 : 47; 40 } cmcv_reg_s; 41 42} cmcv_reg_t; 43 44#define cmcv_mask cmcv_reg_s.cmcr_mask 45#define cmcv_vector cmcv_reg_s.cmcr_vector 46 47enum { 48 IA64_MCA_RENDEZ_CHECKIN_NOTDONE = 0x0, 49 IA64_MCA_RENDEZ_CHECKIN_DONE = 0x1, 50 IA64_MCA_RENDEZ_CHECKIN_INIT = 0x2, 51}; 52 53/* Information maintained by the MC infrastructure */ 54typedef struct ia64_mc_info_s { 55 u64 imi_mca_handler; 56 size_t imi_mca_handler_size; 57 u64 imi_monarch_init_handler; 58 size_t imi_monarch_init_handler_size; 59 u64 imi_slave_init_handler; 60 size_t imi_slave_init_handler_size; 61 u8 imi_rendez_checkin[NR_CPUS]; 62 63} ia64_mc_info_t; 64 65/* Handover state from SAL to OS and vice versa, for both MCA and INIT events. 66 * Besides the handover state, it also contains some saved registers from the 67 * time of the event. 68 * Note: mca_asm.S depends on the precise layout of this structure. 69 */ 70 71struct ia64_sal_os_state { 72 73 /* SAL to OS */ 74 u64 os_gp; /* GP of the os registered with the SAL, physical */ 75 u64 pal_proc; /* PAL_PROC entry point, physical */ 76 u64 sal_proc; /* SAL_PROC entry point, physical */ 77 u64 rv_rc; /* MCA - Rendezvous state, INIT - reason code */ 78 u64 proc_state_param; /* from R18 */ 79 u64 monarch; /* 1 for a monarch event, 0 for a slave */ 80 81 /* common */ 82 u64 sal_ra; /* Return address in SAL, physical */ 83 u64 sal_gp; /* GP of the SAL - physical */ 84 pal_min_state_area_t *pal_min_state; /* from R17. physical in asm, virtual in C */ 85 /* Previous values of IA64_KR(CURRENT) and IA64_KR(CURRENT_STACK). 86 * Note: if the MCA/INIT recovery code wants to resume to a new context 87 * then it must change these values to reflect the new kernel stack. 88 */ 89 u64 prev_IA64_KR_CURRENT; /* previous value of IA64_KR(CURRENT) */ 90 u64 prev_IA64_KR_CURRENT_STACK; 91 struct task_struct *prev_task; /* previous task, NULL if it is not useful */ 92 /* Some interrupt registers are not saved in minstate, pt_regs or 93 * switch_stack. Because MCA/INIT can occur when interrupts are 94 * disabled, we need to save the additional interrupt registers over 95 * MCA/INIT and resume. 96 */ 97 u64 isr; 98 u64 ifa; 99 u64 itir; 100 u64 iipa; 101 u64 iim; 102 u64 iha; 103 104 /* OS to SAL */ 105 u64 os_status; /* OS status to SAL, enum below */ 106 u64 context; /* 0 if return to same context 107 1 if return to new context */ 108}; 109 110enum { 111 IA64_MCA_CORRECTED = 0x0, /* Error has been corrected by OS_MCA */ 112 IA64_MCA_WARM_BOOT = -1, /* Warm boot of the system need from SAL */ 113 IA64_MCA_COLD_BOOT = -2, /* Cold boot of the system need from SAL */ 114 IA64_MCA_HALT = -3 /* System to be halted by SAL */ 115}; 116 117enum { 118 IA64_INIT_RESUME = 0x0, /* Resume after return from INIT */ 119 IA64_INIT_WARM_BOOT = -1, /* Warm boot of the system need from SAL */ 120}; 121 122enum { 123 IA64_MCA_SAME_CONTEXT = 0x0, /* SAL to return to same context */ 124 IA64_MCA_NEW_CONTEXT = -1 /* SAL to return to new context */ 125}; 126 127/* Per-CPU MCA state that is too big for normal per-CPU variables. */ 128 129struct ia64_mca_cpu { 130 u64 mca_stack[KERNEL_STACK_SIZE/8]; 131 u64 init_stack[KERNEL_STACK_SIZE/8]; 132}; 133 134/* Array of physical addresses of each CPU's MCA area. */ 135extern unsigned long __per_cpu_mca[NR_CPUS]; 136 137extern int cpe_vector; 138extern int ia64_cpe_irq; 139extern void ia64_mca_init(void); 140extern void ia64_mca_cpu_init(void *); 141extern void ia64_os_mca_dispatch(void); 142extern void ia64_os_mca_dispatch_end(void); 143extern void ia64_mca_ucmc_handler(struct pt_regs *, struct ia64_sal_os_state *); 144extern void ia64_init_handler(struct pt_regs *, 145 struct switch_stack *, 146 struct ia64_sal_os_state *); 147extern void ia64_monarch_init_handler(void); 148extern void ia64_slave_init_handler(void); 149extern void ia64_mca_cmc_vector_setup(void); 150extern int ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *)); 151extern void ia64_unreg_MCA_extension(void); 152extern u64 ia64_get_rnat(u64 *); 153 154struct ia64_mca_notify_die { 155 struct ia64_sal_os_state *sos; 156 int *monarch_cpu; 157}; 158 159#else /* __ASSEMBLY__ */ 160 161#define IA64_MCA_CORRECTED 0x0 /* Error has been corrected by OS_MCA */ 162#define IA64_MCA_WARM_BOOT -1 /* Warm boot of the system need from SAL */ 163#define IA64_MCA_COLD_BOOT -2 /* Cold boot of the system need from SAL */ 164#define IA64_MCA_HALT -3 /* System to be halted by SAL */ 165 166#define IA64_INIT_RESUME 0x0 /* Resume after return from INIT */ 167#define IA64_INIT_WARM_BOOT -1 /* Warm boot of the system need from SAL */ 168 169#define IA64_MCA_SAME_CONTEXT 0x0 /* SAL to return to same context */ 170#define IA64_MCA_NEW_CONTEXT -1 /* SAL to return to new context */ 171 172#endif /* !__ASSEMBLY__ */ 173#endif /* _ASM_IA64_MCA_H */