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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1 /*
2 Driver for Philips tda1004xh OFDM Demodulator
3
4 (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 */
22/*
23 * This driver needs external firmware. Please use the commands
24 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
25 * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
26 * download/extract them, and then copy them to /usr/lib/hotplug/firmware
27 * or /lib/firmware (depending on configuration of firmware hotplug).
28 */
29#define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
30#define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
31
32#include <linux/init.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/device.h>
36#include <linux/jiffies.h>
37#include <linux/string.h>
38#include <linux/slab.h>
39
40#include "dvb_frontend.h"
41#include "tda1004x.h"
42
43enum tda1004x_demod {
44 TDA1004X_DEMOD_TDA10045,
45 TDA1004X_DEMOD_TDA10046,
46};
47
48struct tda1004x_state {
49 struct i2c_adapter* i2c;
50 const struct tda1004x_config* config;
51 struct dvb_frontend frontend;
52
53 /* private demod data */
54 enum tda1004x_demod demod_type;
55};
56
57static int debug;
58#define dprintk(args...) \
59 do { \
60 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
61 } while (0)
62
63#define TDA1004X_CHIPID 0x00
64#define TDA1004X_AUTO 0x01
65#define TDA1004X_IN_CONF1 0x02
66#define TDA1004X_IN_CONF2 0x03
67#define TDA1004X_OUT_CONF1 0x04
68#define TDA1004X_OUT_CONF2 0x05
69#define TDA1004X_STATUS_CD 0x06
70#define TDA1004X_CONFC4 0x07
71#define TDA1004X_DSSPARE2 0x0C
72#define TDA10045H_CODE_IN 0x0D
73#define TDA10045H_FWPAGE 0x0E
74#define TDA1004X_SCAN_CPT 0x10
75#define TDA1004X_DSP_CMD 0x11
76#define TDA1004X_DSP_ARG 0x12
77#define TDA1004X_DSP_DATA1 0x13
78#define TDA1004X_DSP_DATA2 0x14
79#define TDA1004X_CONFADC1 0x15
80#define TDA1004X_CONFC1 0x16
81#define TDA10045H_S_AGC 0x1a
82#define TDA10046H_AGC_TUN_LEVEL 0x1a
83#define TDA1004X_SNR 0x1c
84#define TDA1004X_CONF_TS1 0x1e
85#define TDA1004X_CONF_TS2 0x1f
86#define TDA1004X_CBER_RESET 0x20
87#define TDA1004X_CBER_MSB 0x21
88#define TDA1004X_CBER_LSB 0x22
89#define TDA1004X_CVBER_LUT 0x23
90#define TDA1004X_VBER_MSB 0x24
91#define TDA1004X_VBER_MID 0x25
92#define TDA1004X_VBER_LSB 0x26
93#define TDA1004X_UNCOR 0x27
94
95#define TDA10045H_CONFPLL_P 0x2D
96#define TDA10045H_CONFPLL_M_MSB 0x2E
97#define TDA10045H_CONFPLL_M_LSB 0x2F
98#define TDA10045H_CONFPLL_N 0x30
99
100#define TDA10046H_CONFPLL1 0x2D
101#define TDA10046H_CONFPLL2 0x2F
102#define TDA10046H_CONFPLL3 0x30
103#define TDA10046H_TIME_WREF1 0x31
104#define TDA10046H_TIME_WREF2 0x32
105#define TDA10046H_TIME_WREF3 0x33
106#define TDA10046H_TIME_WREF4 0x34
107#define TDA10046H_TIME_WREF5 0x35
108
109#define TDA10045H_UNSURW_MSB 0x31
110#define TDA10045H_UNSURW_LSB 0x32
111#define TDA10045H_WREF_MSB 0x33
112#define TDA10045H_WREF_MID 0x34
113#define TDA10045H_WREF_LSB 0x35
114#define TDA10045H_MUXOUT 0x36
115#define TDA1004X_CONFADC2 0x37
116
117#define TDA10045H_IOFFSET 0x38
118
119#define TDA10046H_CONF_TRISTATE1 0x3B
120#define TDA10046H_CONF_TRISTATE2 0x3C
121#define TDA10046H_CONF_POLARITY 0x3D
122#define TDA10046H_FREQ_OFFSET 0x3E
123#define TDA10046H_GPIO_OUT_SEL 0x41
124#define TDA10046H_GPIO_SELECT 0x42
125#define TDA10046H_AGC_CONF 0x43
126#define TDA10046H_AGC_THR 0x44
127#define TDA10046H_AGC_RENORM 0x45
128#define TDA10046H_AGC_GAINS 0x46
129#define TDA10046H_AGC_TUN_MIN 0x47
130#define TDA10046H_AGC_TUN_MAX 0x48
131#define TDA10046H_AGC_IF_MIN 0x49
132#define TDA10046H_AGC_IF_MAX 0x4A
133
134#define TDA10046H_FREQ_PHY2_MSB 0x4D
135#define TDA10046H_FREQ_PHY2_LSB 0x4E
136
137#define TDA10046H_CVBER_CTRL 0x4F
138#define TDA10046H_AGC_IF_LEVEL 0x52
139#define TDA10046H_CODE_CPT 0x57
140#define TDA10046H_CODE_IN 0x58
141
142
143static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
144{
145 int ret;
146 u8 buf[] = { reg, data };
147 struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
148
149 dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
150
151 msg.addr = state->config->demod_address;
152 ret = i2c_transfer(state->i2c, &msg, 1);
153
154 if (ret != 1)
155 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
156 __FUNCTION__, reg, data, ret);
157
158 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
159 reg, data, ret);
160 return (ret != 1) ? -1 : 0;
161}
162
163static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
164{
165 int ret;
166 u8 b0[] = { reg };
167 u8 b1[] = { 0 };
168 struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
169 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
170
171 dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
172
173 msg[0].addr = state->config->demod_address;
174 msg[1].addr = state->config->demod_address;
175 ret = i2c_transfer(state->i2c, msg, 2);
176
177 if (ret != 2) {
178 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
179 ret);
180 return -1;
181 }
182
183 dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
184 reg, b1[0], ret);
185 return b1[0];
186}
187
188static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
189{
190 int val;
191 dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
192 mask, data);
193
194 // read a byte and check
195 val = tda1004x_read_byte(state, reg);
196 if (val < 0)
197 return val;
198
199 // mask if off
200 val = val & ~mask;
201 val |= data & 0xff;
202
203 // write it out again
204 return tda1004x_write_byteI(state, reg, val);
205}
206
207static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
208{
209 int i;
210 int result;
211
212 dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
213
214 result = 0;
215 for (i = 0; i < len; i++) {
216 result = tda1004x_write_byteI(state, reg + i, buf[i]);
217 if (result != 0)
218 break;
219 }
220
221 return result;
222}
223
224static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
225{
226 int result;
227 dprintk("%s\n", __FUNCTION__);
228
229 result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
230 msleep(20);
231 return result;
232}
233
234static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
235{
236 dprintk("%s\n", __FUNCTION__);
237
238 return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
239}
240
241static int tda10045h_set_bandwidth(struct tda1004x_state *state,
242 fe_bandwidth_t bandwidth)
243{
244 static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
245 static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
246 static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
247
248 switch (bandwidth) {
249 case BANDWIDTH_6_MHZ:
250 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
251 break;
252
253 case BANDWIDTH_7_MHZ:
254 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
255 break;
256
257 case BANDWIDTH_8_MHZ:
258 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
259 break;
260
261 default:
262 return -EINVAL;
263 }
264
265 tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
266
267 return 0;
268}
269
270static int tda10046h_set_bandwidth(struct tda1004x_state *state,
271 fe_bandwidth_t bandwidth)
272{
273 static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
274 static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
275 static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d };
276
277 static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 };
278 static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab };
279 static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 };
280 int tda10046_clk53m;
281
282 if ((state->config->if_freq == TDA10046_FREQ_045) ||
283 (state->config->if_freq == TDA10046_FREQ_052))
284 tda10046_clk53m = 0;
285 else
286 tda10046_clk53m = 1;
287 switch (bandwidth) {
288 case BANDWIDTH_6_MHZ:
289 if (tda10046_clk53m)
290 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
291 sizeof(bandwidth_6mhz_53M));
292 else
293 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M,
294 sizeof(bandwidth_6mhz_48M));
295 if (state->config->if_freq == TDA10046_FREQ_045) {
296 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
297 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
298 }
299 break;
300
301 case BANDWIDTH_7_MHZ:
302 if (tda10046_clk53m)
303 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
304 sizeof(bandwidth_7mhz_53M));
305 else
306 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M,
307 sizeof(bandwidth_7mhz_48M));
308 if (state->config->if_freq == TDA10046_FREQ_045) {
309 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
310 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
311 }
312 break;
313
314 case BANDWIDTH_8_MHZ:
315 if (tda10046_clk53m)
316 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
317 sizeof(bandwidth_8mhz_53M));
318 else
319 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M,
320 sizeof(bandwidth_8mhz_48M));
321 if (state->config->if_freq == TDA10046_FREQ_045) {
322 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
323 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
324 }
325 break;
326
327 default:
328 return -EINVAL;
329 }
330
331 return 0;
332}
333
334static int tda1004x_do_upload(struct tda1004x_state *state,
335 unsigned char *mem, unsigned int len,
336 u8 dspCodeCounterReg, u8 dspCodeInReg)
337{
338 u8 buf[65];
339 struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
340 int tx_size;
341 int pos = 0;
342
343 /* clear code counter */
344 tda1004x_write_byteI(state, dspCodeCounterReg, 0);
345 fw_msg.addr = state->config->demod_address;
346
347 buf[0] = dspCodeInReg;
348 while (pos != len) {
349 // work out how much to send this time
350 tx_size = len - pos;
351 if (tx_size > 0x10)
352 tx_size = 0x10;
353
354 // send the chunk
355 memcpy(buf + 1, mem + pos, tx_size);
356 fw_msg.len = tx_size + 1;
357 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
358 printk(KERN_ERR "tda1004x: Error during firmware upload\n");
359 return -EIO;
360 }
361 pos += tx_size;
362
363 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos);
364 }
365 // give the DSP a chance to settle 03/10/05 Hac
366 msleep(100);
367
368 return 0;
369}
370
371static int tda1004x_check_upload_ok(struct tda1004x_state *state)
372{
373 u8 data1, data2;
374 unsigned long timeout;
375
376 if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
377 timeout = jiffies + 2 * HZ;
378 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
379 if (time_after(jiffies, timeout)) {
380 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
381 break;
382 }
383 msleep(1);
384 }
385 } else
386 msleep(100);
387
388 // check upload was OK
389 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
390 tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
391
392 data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
393 data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
394 if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) {
395 printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
396 return -EIO;
397 }
398 printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
399 return 0;
400}
401
402static int tda10045_fwupload(struct dvb_frontend* fe)
403{
404 struct tda1004x_state* state = fe->demodulator_priv;
405 int ret;
406 const struct firmware *fw;
407
408 /* don't re-upload unless necessary */
409 if (tda1004x_check_upload_ok(state) == 0)
410 return 0;
411
412 /* request the firmware, this will block until someone uploads it */
413 printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
414 ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
415 if (ret) {
416 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
417 return ret;
418 }
419
420 /* reset chip */
421 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
422 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
423 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
424 msleep(10);
425
426 /* set parameters */
427 tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ);
428
429 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
430 release_firmware(fw);
431 if (ret)
432 return ret;
433 printk(KERN_INFO "tda1004x: firmware upload complete\n");
434
435 /* wait for DSP to initialise */
436 /* DSPREADY doesn't seem to work on the TDA10045H */
437 msleep(100);
438
439 return tda1004x_check_upload_ok(state);
440}
441
442static void tda10046_init_plls(struct dvb_frontend* fe)
443{
444 struct tda1004x_state* state = fe->demodulator_priv;
445 int tda10046_clk53m;
446
447 if ((state->config->if_freq == TDA10046_FREQ_045) ||
448 (state->config->if_freq == TDA10046_FREQ_052))
449 tda10046_clk53m = 0;
450 else
451 tda10046_clk53m = 1;
452
453 tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
454 if(tda10046_clk53m) {
455 printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n");
456 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
457 } else {
458 printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n");
459 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
460 }
461 if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
462 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__);
463 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
464 } else {
465 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__);
466 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
467 }
468 if(tda10046_clk53m)
469 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
470 else
471 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
472 /* Note clock frequency is handled implicitly */
473 switch (state->config->if_freq) {
474 case TDA10046_FREQ_045:
475 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
476 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
477 break;
478 case TDA10046_FREQ_052:
479 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
480 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
481 break;
482 case TDA10046_FREQ_3617:
483 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
484 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
485 break;
486 case TDA10046_FREQ_3613:
487 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
488 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
489 break;
490 }
491 tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
492 /* let the PLLs settle */
493 msleep(120);
494}
495
496static int tda10046_fwupload(struct dvb_frontend* fe)
497{
498 struct tda1004x_state* state = fe->demodulator_priv;
499 int ret;
500 const struct firmware *fw;
501
502 /* reset + wake up chip */
503 if (state->config->xtal_freq == TDA10046_XTAL_4M) {
504 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0);
505 } else {
506 dprintk("%s: 16MHz Xtal, reducing I2C speed\n", __FUNCTION__);
507 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0x80);
508 }
509 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
510 /* let the clocks recover from sleep */
511 msleep(5);
512
513 /* The PLLs need to be reprogrammed after sleep */
514 tda10046_init_plls(fe);
515
516 /* don't re-upload unless necessary */
517 if (tda1004x_check_upload_ok(state) == 0)
518 return 0;
519
520 if (state->config->request_firmware != NULL) {
521 /* request the firmware, this will block until someone uploads it */
522 printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
523 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
524 if (ret) {
525 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
526 return ret;
527 }
528 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
529 ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
530 release_firmware(fw);
531 if (ret)
532 return ret;
533 } else {
534 /* boot from firmware eeprom */
535 printk(KERN_INFO "tda1004x: booting from eeprom\n");
536 tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4);
537 msleep(300);
538 }
539 return tda1004x_check_upload_ok(state);
540}
541
542static int tda1004x_encode_fec(int fec)
543{
544 // convert known FEC values
545 switch (fec) {
546 case FEC_1_2:
547 return 0;
548 case FEC_2_3:
549 return 1;
550 case FEC_3_4:
551 return 2;
552 case FEC_5_6:
553 return 3;
554 case FEC_7_8:
555 return 4;
556 }
557
558 // unsupported
559 return -EINVAL;
560}
561
562static int tda1004x_decode_fec(int tdafec)
563{
564 // convert known FEC values
565 switch (tdafec) {
566 case 0:
567 return FEC_1_2;
568 case 1:
569 return FEC_2_3;
570 case 2:
571 return FEC_3_4;
572 case 3:
573 return FEC_5_6;
574 case 4:
575 return FEC_7_8;
576 }
577
578 // unsupported
579 return -1;
580}
581
582int tda1004x_write_byte(struct dvb_frontend* fe, int reg, int data)
583{
584 struct tda1004x_state* state = fe->demodulator_priv;
585
586 return tda1004x_write_byteI(state, reg, data);
587}
588
589static int tda10045_init(struct dvb_frontend* fe)
590{
591 struct tda1004x_state* state = fe->demodulator_priv;
592
593 dprintk("%s\n", __FUNCTION__);
594
595 if (tda10045_fwupload(fe)) {
596 printk("tda1004x: firmware upload failed\n");
597 return -EIO;
598 }
599
600 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
601
602 // tda setup
603 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
604 tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
605 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
606 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
607 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
608 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
609 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
610 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
611 tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
612 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
613 tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
614
615 tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
616
617 return 0;
618}
619
620static int tda10046_init(struct dvb_frontend* fe)
621{
622 struct tda1004x_state* state = fe->demodulator_priv;
623 dprintk("%s\n", __FUNCTION__);
624
625 if (tda10046_fwupload(fe)) {
626 printk("tda1004x: firmware upload failed\n");
627 return -EIO;
628 }
629
630 // tda setup
631 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
632 tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87); // 100 ppm crystal, select HP stream
633 tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88); // enable pulse killer
634
635 switch (state->config->agc_config) {
636 case TDA10046_AGC_DEFAULT:
637 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
638 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
639 break;
640 case TDA10046_AGC_IFO_AUTO_NEG:
641 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
642 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
643 break;
644 case TDA10046_AGC_IFO_AUTO_POS:
645 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
646 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x00); // set AGC polarities
647 break;
648 case TDA10046_AGC_TDA827X:
649 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup
650 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold
651 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
652 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x6a); // set AGC polarities
653 break;
654 case TDA10046_AGC_TDA827X_GPL:
655 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup
656 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold
657 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
658 tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities
659 break;
660 }
661 tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
662 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x61); // Turn both AGC outputs on
663 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // }
664 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
665 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // }
666 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // }
667 tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
668 tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
669 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
670 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
671 // tda1004x_write_mask(state, 0x50, 0x80, 0x80); // handle out of guard echoes
672 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
673
674 return 0;
675}
676
677static int tda1004x_set_fe(struct dvb_frontend* fe,
678 struct dvb_frontend_parameters *fe_params)
679{
680 struct tda1004x_state* state = fe->demodulator_priv;
681 int tmp;
682 int inversion;
683
684 dprintk("%s\n", __FUNCTION__);
685
686 if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
687 // setup auto offset
688 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
689 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
690 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
691
692 // disable agc_conf[2]
693 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
694 }
695
696 // set frequency
697 if (fe->ops.tuner_ops.set_params) {
698 fe->ops.tuner_ops.set_params(fe, fe_params);
699 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
700 }
701
702 // Hardcoded to use auto as much as possible on the TDA10045 as it
703 // is very unreliable if AUTO mode is _not_ used.
704 if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
705 fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
706 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
707 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
708 }
709
710 // Set standard params.. or put them to auto
711 if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
712 (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
713 (fe_params->u.ofdm.constellation == QAM_AUTO) ||
714 (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
715 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto
716 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
717 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
718 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
719 } else {
720 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto
721
722 // set HP FEC
723 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
724 if (tmp < 0)
725 return tmp;
726 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
727
728 // set LP FEC
729 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
730 if (tmp < 0)
731 return tmp;
732 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
733
734 // set constellation
735 switch (fe_params->u.ofdm.constellation) {
736 case QPSK:
737 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
738 break;
739
740 case QAM_16:
741 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
742 break;
743
744 case QAM_64:
745 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
746 break;
747
748 default:
749 return -EINVAL;
750 }
751
752 // set hierarchy
753 switch (fe_params->u.ofdm.hierarchy_information) {
754 case HIERARCHY_NONE:
755 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
756 break;
757
758 case HIERARCHY_1:
759 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
760 break;
761
762 case HIERARCHY_2:
763 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
764 break;
765
766 case HIERARCHY_4:
767 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
768 break;
769
770 default:
771 return -EINVAL;
772 }
773 }
774
775 // set bandwidth
776 switch (state->demod_type) {
777 case TDA1004X_DEMOD_TDA10045:
778 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
779 break;
780
781 case TDA1004X_DEMOD_TDA10046:
782 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
783 break;
784 }
785
786 // set inversion
787 inversion = fe_params->inversion;
788 if (state->config->invert)
789 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
790 switch (inversion) {
791 case INVERSION_OFF:
792 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
793 break;
794
795 case INVERSION_ON:
796 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
797 break;
798
799 default:
800 return -EINVAL;
801 }
802
803 // set guard interval
804 switch (fe_params->u.ofdm.guard_interval) {
805 case GUARD_INTERVAL_1_32:
806 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
807 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
808 break;
809
810 case GUARD_INTERVAL_1_16:
811 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
812 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
813 break;
814
815 case GUARD_INTERVAL_1_8:
816 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
817 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
818 break;
819
820 case GUARD_INTERVAL_1_4:
821 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
822 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
823 break;
824
825 case GUARD_INTERVAL_AUTO:
826 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
827 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
828 break;
829
830 default:
831 return -EINVAL;
832 }
833
834 // set transmission mode
835 switch (fe_params->u.ofdm.transmission_mode) {
836 case TRANSMISSION_MODE_2K:
837 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
838 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
839 break;
840
841 case TRANSMISSION_MODE_8K:
842 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
843 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
844 break;
845
846 case TRANSMISSION_MODE_AUTO:
847 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
848 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
849 break;
850
851 default:
852 return -EINVAL;
853 }
854
855 // start the lock
856 switch (state->demod_type) {
857 case TDA1004X_DEMOD_TDA10045:
858 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
859 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
860 break;
861
862 case TDA1004X_DEMOD_TDA10046:
863 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
864 msleep(1);
865 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
866 break;
867 }
868
869 msleep(10);
870
871 return 0;
872}
873
874static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params)
875{
876 struct tda1004x_state* state = fe->demodulator_priv;
877
878 dprintk("%s\n", __FUNCTION__);
879
880 // inversion status
881 fe_params->inversion = INVERSION_OFF;
882 if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
883 fe_params->inversion = INVERSION_ON;
884 if (state->config->invert)
885 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
886
887 // bandwidth
888 switch (state->demod_type) {
889 case TDA1004X_DEMOD_TDA10045:
890 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
891 case 0x14:
892 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
893 break;
894 case 0xdb:
895 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
896 break;
897 case 0x4f:
898 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
899 break;
900 }
901 break;
902 case TDA1004X_DEMOD_TDA10046:
903 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
904 case 0x5c:
905 case 0x54:
906 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
907 break;
908 case 0x6a:
909 case 0x60:
910 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
911 break;
912 case 0x7b:
913 case 0x70:
914 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
915 break;
916 }
917 break;
918 }
919
920 // FEC
921 fe_params->u.ofdm.code_rate_HP =
922 tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
923 fe_params->u.ofdm.code_rate_LP =
924 tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
925
926 // constellation
927 switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
928 case 0:
929 fe_params->u.ofdm.constellation = QPSK;
930 break;
931 case 1:
932 fe_params->u.ofdm.constellation = QAM_16;
933 break;
934 case 2:
935 fe_params->u.ofdm.constellation = QAM_64;
936 break;
937 }
938
939 // transmission mode
940 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
941 if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
942 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
943
944 // guard interval
945 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
946 case 0:
947 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
948 break;
949 case 1:
950 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
951 break;
952 case 2:
953 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
954 break;
955 case 3:
956 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
957 break;
958 }
959
960 // hierarchy
961 switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
962 case 0:
963 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
964 break;
965 case 1:
966 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
967 break;
968 case 2:
969 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
970 break;
971 case 3:
972 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
973 break;
974 }
975
976 return 0;
977}
978
979static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
980{
981 struct tda1004x_state* state = fe->demodulator_priv;
982 int status;
983 int cber;
984 int vber;
985
986 dprintk("%s\n", __FUNCTION__);
987
988 // read status
989 status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
990 if (status == -1)
991 return -EIO;
992
993 // decode
994 *fe_status = 0;
995 if (status & 4)
996 *fe_status |= FE_HAS_SIGNAL;
997 if (status & 2)
998 *fe_status |= FE_HAS_CARRIER;
999 if (status & 8)
1000 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1001
1002 // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1003 // is getting anything valid
1004 if (!(*fe_status & FE_HAS_VITERBI)) {
1005 // read the CBER
1006 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1007 if (cber == -1)
1008 return -EIO;
1009 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1010 if (status == -1)
1011 return -EIO;
1012 cber |= (status << 8);
1013 // The address 0x20 should be read to cope with a TDA10046 bug
1014 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1015
1016 if (cber != 65535)
1017 *fe_status |= FE_HAS_VITERBI;
1018 }
1019
1020 // if we DO have some valid VITERBI output, but don't already have SYNC
1021 // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1022 if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1023 // read the VBER
1024 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
1025 if (vber == -1)
1026 return -EIO;
1027 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
1028 if (status == -1)
1029 return -EIO;
1030 vber |= (status << 8);
1031 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
1032 if (status == -1)
1033 return -EIO;
1034 vber |= (status & 0x0f) << 16;
1035 // The CVBER_LUT should be read to cope with TDA10046 hardware bug
1036 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
1037
1038 // if RS has passed some valid TS packets, then we must be
1039 // getting some SYNC bytes
1040 if (vber < 16632)
1041 *fe_status |= FE_HAS_SYNC;
1042 }
1043
1044 // success
1045 dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
1046 return 0;
1047}
1048
1049static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
1050{
1051 struct tda1004x_state* state = fe->demodulator_priv;
1052 int tmp;
1053 int reg = 0;
1054
1055 dprintk("%s\n", __FUNCTION__);
1056
1057 // determine the register to use
1058 switch (state->demod_type) {
1059 case TDA1004X_DEMOD_TDA10045:
1060 reg = TDA10045H_S_AGC;
1061 break;
1062
1063 case TDA1004X_DEMOD_TDA10046:
1064 reg = TDA10046H_AGC_IF_LEVEL;
1065 break;
1066 }
1067
1068 // read it
1069 tmp = tda1004x_read_byte(state, reg);
1070 if (tmp < 0)
1071 return -EIO;
1072
1073 *signal = (tmp << 8) | tmp;
1074 dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
1075 return 0;
1076}
1077
1078static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
1079{
1080 struct tda1004x_state* state = fe->demodulator_priv;
1081 int tmp;
1082
1083 dprintk("%s\n", __FUNCTION__);
1084
1085 // read it
1086 tmp = tda1004x_read_byte(state, TDA1004X_SNR);
1087 if (tmp < 0)
1088 return -EIO;
1089 tmp = 255 - tmp;
1090
1091 *snr = ((tmp << 8) | tmp);
1092 dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1093 return 0;
1094}
1095
1096static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
1097{
1098 struct tda1004x_state* state = fe->demodulator_priv;
1099 int tmp;
1100 int tmp2;
1101 int counter;
1102
1103 dprintk("%s\n", __FUNCTION__);
1104
1105 // read the UCBLOCKS and reset
1106 counter = 0;
1107 tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1108 if (tmp < 0)
1109 return -EIO;
1110 tmp &= 0x7f;
1111 while (counter++ < 5) {
1112 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1113 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1114 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1115
1116 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1117 if (tmp2 < 0)
1118 return -EIO;
1119 tmp2 &= 0x7f;
1120 if ((tmp2 < tmp) || (tmp2 == 0))
1121 break;
1122 }
1123
1124 if (tmp != 0x7f)
1125 *ucblocks = tmp;
1126 else
1127 *ucblocks = 0xffffffff;
1128
1129 dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1130 return 0;
1131}
1132
1133static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1134{
1135 struct tda1004x_state* state = fe->demodulator_priv;
1136 int tmp;
1137
1138 dprintk("%s\n", __FUNCTION__);
1139
1140 // read it in
1141 tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1142 if (tmp < 0)
1143 return -EIO;
1144 *ber = tmp << 1;
1145 tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1146 if (tmp < 0)
1147 return -EIO;
1148 *ber |= (tmp << 9);
1149 // The address 0x20 should be read to cope with a TDA10046 bug
1150 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1151
1152 dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1153 return 0;
1154}
1155
1156static int tda1004x_sleep(struct dvb_frontend* fe)
1157{
1158 struct tda1004x_state* state = fe->demodulator_priv;
1159
1160 switch (state->demod_type) {
1161 case TDA1004X_DEMOD_TDA10045:
1162 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1163 break;
1164
1165 case TDA1004X_DEMOD_TDA10046:
1166 /* set outputs to tristate */
1167 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff);
1168 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1169 break;
1170 }
1171
1172 return 0;
1173}
1174
1175static int tda1004x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
1176{
1177 struct tda1004x_state* state = fe->demodulator_priv;
1178
1179 if (enable) {
1180 return tda1004x_enable_tuner_i2c(state);
1181 } else {
1182 return tda1004x_disable_tuner_i2c(state);
1183 }
1184}
1185
1186static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1187{
1188 fesettings->min_delay_ms = 800;
1189 /* Drift compensation makes no sense for DVB-T */
1190 fesettings->step_size = 0;
1191 fesettings->max_drift = 0;
1192 return 0;
1193}
1194
1195static void tda1004x_release(struct dvb_frontend* fe)
1196{
1197 struct tda1004x_state *state = fe->demodulator_priv;
1198 kfree(state);
1199}
1200
1201static struct dvb_frontend_ops tda10045_ops = {
1202 .info = {
1203 .name = "Philips TDA10045H DVB-T",
1204 .type = FE_OFDM,
1205 .frequency_min = 51000000,
1206 .frequency_max = 858000000,
1207 .frequency_stepsize = 166667,
1208 .caps =
1209 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1210 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1211 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1212 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1213 },
1214
1215 .release = tda1004x_release,
1216
1217 .init = tda10045_init,
1218 .sleep = tda1004x_sleep,
1219 .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1220
1221 .set_frontend = tda1004x_set_fe,
1222 .get_frontend = tda1004x_get_fe,
1223 .get_tune_settings = tda1004x_get_tune_settings,
1224
1225 .read_status = tda1004x_read_status,
1226 .read_ber = tda1004x_read_ber,
1227 .read_signal_strength = tda1004x_read_signal_strength,
1228 .read_snr = tda1004x_read_snr,
1229 .read_ucblocks = tda1004x_read_ucblocks,
1230};
1231
1232struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1233 struct i2c_adapter* i2c)
1234{
1235 struct tda1004x_state *state;
1236
1237 /* allocate memory for the internal state */
1238 state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1239 if (!state)
1240 return NULL;
1241
1242 /* setup the state */
1243 state->config = config;
1244 state->i2c = i2c;
1245 state->demod_type = TDA1004X_DEMOD_TDA10045;
1246
1247 /* check if the demod is there */
1248 if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x25) {
1249 kfree(state);
1250 return NULL;
1251 }
1252
1253 /* create dvb_frontend */
1254 memcpy(&state->frontend.ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1255 state->frontend.demodulator_priv = state;
1256 return &state->frontend;
1257}
1258
1259static struct dvb_frontend_ops tda10046_ops = {
1260 .info = {
1261 .name = "Philips TDA10046H DVB-T",
1262 .type = FE_OFDM,
1263 .frequency_min = 51000000,
1264 .frequency_max = 858000000,
1265 .frequency_stepsize = 166667,
1266 .caps =
1267 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1268 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1269 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1270 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1271 },
1272
1273 .release = tda1004x_release,
1274
1275 .init = tda10046_init,
1276 .sleep = tda1004x_sleep,
1277 .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1278
1279 .set_frontend = tda1004x_set_fe,
1280 .get_frontend = tda1004x_get_fe,
1281 .get_tune_settings = tda1004x_get_tune_settings,
1282
1283 .read_status = tda1004x_read_status,
1284 .read_ber = tda1004x_read_ber,
1285 .read_signal_strength = tda1004x_read_signal_strength,
1286 .read_snr = tda1004x_read_snr,
1287 .read_ucblocks = tda1004x_read_ucblocks,
1288};
1289
1290struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1291 struct i2c_adapter* i2c)
1292{
1293 struct tda1004x_state *state;
1294
1295 /* allocate memory for the internal state */
1296 state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1297 if (!state)
1298 return NULL;
1299
1300 /* setup the state */
1301 state->config = config;
1302 state->i2c = i2c;
1303 state->demod_type = TDA1004X_DEMOD_TDA10046;
1304
1305 /* check if the demod is there */
1306 if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) {
1307 kfree(state);
1308 return NULL;
1309 }
1310
1311 /* create dvb_frontend */
1312 memcpy(&state->frontend.ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1313 state->frontend.demodulator_priv = state;
1314 return &state->frontend;
1315}
1316
1317module_param(debug, int, 0644);
1318MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1319
1320MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1321MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1322MODULE_LICENSE("GPL");
1323
1324EXPORT_SYMBOL(tda10045_attach);
1325EXPORT_SYMBOL(tda10046_attach);
1326EXPORT_SYMBOL(tda1004x_write_byte);